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| ASAHI KASEI [AKD5701-A] AKD5701-A AK5701 Evaluation board Rev.0 GENERAL DESCRIPTION AKD5701-A is an evaluation board for the portable digital audio 16bit A/D converter, AK5701. AKD5701-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD5701-A --- Evaluation board for AK5701 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION * DIT with optical output * RCA connector for an external clock input * 10pin Header for serial control interface AVDD 3.3V Regulator DVDD VD AGND DGND Control Data 10pin Header LIN1/ LIN2 MIC RIN1/ RIN2 AK4114 (DIT) Opt Out EXT/LRCK EXT/BCLK CLOCK GEN 5V AK5701 DSP 2 10pin Header DSP 1 10pin Header Figure 1. AKD5701-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. 2005/04 ASAHI KASEI [AKD5701-A] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. 1-1) When AVDD, DVDD and VD are supplied from the regulator. [REG] [AVDD] [DVDD] [VD] [AGND] [DGND] (Red) (Orange) (Orange) (Orange) (Black) (Black) = 5V = open = open = open (for logic) = 0V : for analog ground = 0V : for logic ground 1-2) When AVDD, DVDD and VD are not supplied from the regulator. [REG] [AVDD] [DVDD] [VD] [AGND] [DGND] (Red) (Orange) (Orange) (Orange) (Black) (Black) = "REG" jack should be open. = 2.4 3.6V : for AVDD of AK5701 (typ. 3.0V) = 1.6 3.6V : for DVDD of AK5701 (typ. 3.0V) = 2.7 3.6V : for logic (typ. 3.0V) = 0V : for analog ground = 0V : for logic ground Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5701 and AK4114 should be reset once by bringing SW1, 2 "L" upon power-up. Evaluation mode In case of AK5701 evaluation using AK4114, same audio interface format should be set for both AK5701 and AK4114. About AK5701's audio interface format, refer to datasheet of AK5701. About AK4114's audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) Evaluation of PLL, Master Mode (Default) (2) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) (3) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: BCLK or LRCK pin) (4) Evaluation of using DIT of AK4114 (opt-connector): EXT, Slave Mode (5) Slave & Bypass Mode (6) Bypass Mode 2005/04 ASAHI KASEI [AKD5701-A] (1) Evaluation of PLL, Master Mode (Default) Connect PORT2 DSP1 with DSP. Figure below shows PORT2 pin assign. PORT2 MCKO BCLK LRCK SDTO VD GND GND NC NC NC a) Set up jumper pins of MCKI clock When using X'tal as MCKI clock, X'tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set to X1. X'tal of 11.2896MHz (Default) is set on the AKD5701-A. When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) is supplied through an RCA connector (J3: EXT/BCLK), select EXTCLK/BCLK on JP16 (XTI) and select EXTCLK/BCLK on JP19 (MCLK_SEL). JP14 (EXT1) and R20 should be properly selected in order to match the output impedance of the clock generator. JP16 JP19 JP11 XTI MCLK_SEL MKFS 5701MCKO EXTCLK /BCLK 4114MCKO MCKI EXTCLK /BCLK 256fs 512fs 1024fs MCKO b) Set up jumper pins of BCLK clock Output frequency (32fs/64fs) of BCLK should be set by "BCKO1-0 bit" in the AK5701. There is no necessity for set up JP12. JP17 JP12 BCLK_SEL BCLK EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT 64fs 32fs 16fs c) Set up jumper pins of LRCK clock JP18 LRCK_SEL JP13 LRCK EXT EXT EXTLRCK/ LRCK/ DIT 2fs 1fs LRCK DIT 2005/04 ASAHI KASEI [AKD5701-A] (2) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) Connect PORT4 (DSP2) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI EXBCLK EXLRCK EXSDTI VD GND GND NC NC SDTO a) Set up jumper pins of MCKI clock X'tal of 11.2896MHz (Default) is set on the AKD5701-A. In this case, the AK5701 corresponds to PLL reference clock of 11.2896MHz. In this evaluation mode, the output clock from MCKO pin of the AK5701 is supplied to a divider (U3: 74VHC4040), EXBCLK and LRCK clocks are generated by the divider. Then "MCKO bit" in the AK5701 should be set to "1". When an external clock is supplied through an RCA connector (J3: EXT/BCLK), select EXTCLK/BCLK on JP16 (XTI) and select EXTCLK/BCLK on JP17 (MCLK_SEL). JP14 (EXT1) and R20 should be properly selected in order too match the output impedance of the clock generator. JP16 XTI JP19 MCLK_SEL JP11 MKFS 5701MCKO EXTCLK /BCLK 4114MCKO MCKI EXTCLK /BCLK 256fs 512fs 1024fs MCKO b) Set up jumper pins of BCLK clock JP17 BCLK_SEL JP12 BCLK EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT 64fs 32fs 16fs c) Set up jumper pins of LRCK clock JP18 LRCK_SEL JP13 LRCK EXT EXT EXTLRCK/ LRCK/ DIT 2fs 1fs LRCK DIT 2005/04 ASAHI KASEI [AKD5701-A] (2-a) In the case of using AK4114. *This mode is BCLK=64fs, LRCK=1fs only. Set up jumper pins of MCKI clock *In the case of using X1, JP16 should be open. JP16 JP19 XTI MCLK_SEL JP11 MKFS 256fs 512fs 1024fs MCKO Set up jumper pins of BCLK clock JP18 LRCK_SEL JP13 LRCK EXT EXT EXTLRCK/ LRCK/ DIT 2fs 1fs LRCK DIT Set up jumper pins of LRCK clock JP17 BCLK_SEL JP12 BCLK EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT 64fs 32fs 16fs 2005/04 ASAHI KASEI [AKD5701-A] (3) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: BCLK or LRCK pin) Connect PORT4 (DSP2) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI EXBCLK EXLRCK EXSDTI VD GND GND NC NC SDTO a) Set up jumper pins of MCKI clock JP16 XTI JP19 MCLK_SEL 5701MCKO EXTCLK /BCLK 4114MCKO MCKI EXTCLK /BCLK b) Set up jumper pins of BCLK clock When an external clock is supplied through a RCA connector J3 (EXT/BCLK), J4 (EXT/LRCK), JP14 (EXT1) and R20, JP15 (EXT2) and R21 should be properly selected in order to much the output impedance of the clock generator. JP17 BCLK_SEL JP12 BCLK EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT 64fs 32fs 16fs c) Set up jumper pins of LRCK clock JP18 LRCK_SEL JP13 LRCK EXT EXT EXTLRCK/ LRCK/ DIT 2fs 1fs LRCK DIT 2005/04 ASAHI KASEI [AKD5701-A] (4) Evaluation of EXT, Slave Mode Connect PORT4 (DSP2) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI EXBCLK EXLRCK EXSDTI VD GND GND NC NC SDTO a) Set up jumper pins of MCKI clock PORT4 (DSP2) is used. JP19 (MCKI_SEL) should be open. b) Set up jumper pins of BCLK clock JP17 BCLK_SEL JP12 BCLK EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT 64fs 32fs 16fs c) Set up jumper pins of LRCK clock JP18 LRCK_SEL JP13 LRCK EXT EXT EXTLRCK/ LRCK/ DIT 2fs 1fs LRCK DIT d) Set up jumper pins of DATA JP18 LRCK_SEL JP17 BCLK_SEL EXT EXT EXTLRCK/ LRCK/ DIT EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT LRCK DIT 2005/04 ASAHI KASEI [AKD5701-A] (5) Slave & Bypass Mode Connect PORT4 (DSP2) and PORT2 (DSP1) with DSP. Figure below shows PORT4 and PORT2 pin assign. PORT4 MCKI EXBCLK EXLRCK EXSDTI VD GND GND NC NC SDTO MCKO BCLK LRCK SDTO VD PORT2 GND GND NC NC NC a) Set up jumper pins of MCKI clock PORT4 (DSP2) is used. JP19 (MCKI_SEL) should be open. b) Set up jumper pins of BCLK clock JP17 BCLK_SEL JP12 BCLK EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT 64fs 32fs 16fs c) Set up jumper pins of LRCK clock JP18 LRCK_SEL JP13 LRCK EXT EXT EXTLRCK/ LRCK/ DIT 2fs 1fs LRCK DIT d) Set up jumper pins of DATA JP18 LRCK_SEL JP17 BCLK_SEL EXT EXT EXTLRCK/ LRCK/ DIT EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT LRCK DIT 2005/04 ASAHI KASEI [AKD5701-A] (6) Bypass Mode Figure below shows PORT4 and PORT2 pin assign. PORT4 MCKI EXBCLK EXLRCK EXSDTI VD GND GND NC NC SDTO MCKO BCLK LRCK SDTO VD PORT2 GND GND NC NC NC a) Set up jumper pins of MCKI clock PORT4 (DSP2) is used. JP19 (MCKI_SEL) should be open. b) Set up jumper pins of BCLK clock JP17 BCLK_SEL JP12 BCLK EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT 64fs 32fs 16fs c) Set up jumper pins of LRCK clock JP18 LRCK_SEL JP13 LRCK EXT EXT EXTLRCK/ LRCK/ DIT 2fs 1fs LRCK DIT d) Set up jumper pins of DATA JP18 LRCK_SEL JP17 BCLK_SEL EXT EXT EXTLRCK/ LRCK/ DIT EXT BCLK EXT EXTBCLK/ BCLK/ DIT DIT LRCK DIT 2005/04 ASAHI KASEI [AKD5701-A] DIP Switch set up [SW2] (MODE): Mode Setting of AK4114 ON is "H", OFF is "L". No. 1 2 3 4 Name DIF0 DIF1 OCKS0 OCKS1 ON ("H") OFF ("L") AK4114 Audio Format Setting See Table 2 Master Clock Frequency Select See Table 3 Table 1. Mode Setting Resistor for AK5701 Set up for AK4114 SW3 M/S 0 0 1 1 DIF1 DIF0 DIF1 DIF0 DAUX 1 0 0 0 24bit, Left justified Master 2 1 1 0 1 24bit, I S Master 1 0 1 0 24bit, Left justified Slave 1 1 1 1 24bit, I2S Slave Table 2. Setting for AK5701 and AK4114 Audio Interface Format Default No. 0 2 OCKS1 0 1 OCKS0 0 0 MCKO1 256fs 512fs X'tal 256fs 512fs Default Table 3. Master Clock Frequency Select for AK4114 (Stereo mode) Other jumper pins set up ASAHI KASEI [AKD5701-A] 1. JP1 (GND) OPEN SHORT : Analog ground and Digital ground : Separated. : Common. (The connector "DGND" should be open.) 2. JP2 (AVDD_SEL) : AVDD of the AK5701 OPEN : AVDD is supplied from the regulator ("AVDD" jack should be open). < Default > SHORT : AVDD is supplied from "AVDD " jack. 3. JP3 (DVDD_SEL) : DVDD of the AK5701 AVDD : DVDD is supplied from "AVDD". < Default > DVDD : DVDD is supplied from "DVDD " jack. 4. JP4 (CSP) H L : CSP signal Select (Hi or Low) : CSP= "Hi" : CSP= "Low"< Default > 5. JP5, JP6 (MPWR) : Connect to MPWR OPEN : No connect< Default > SHORT : Connect 6. JP7 (LVC_SEL) DVDD VD 7. JP20 (SDTO) OPEN SHORT 8. JP8 (CCLK) OPEN SHORT : Supply line selection of Logic block of LVC. : Logic block of LVC is supplied from "DVDD". < Default > : Logic block of LVC is supplied from "VD " jack. : Select #4 pin of the PORT4 (DSP) : Input data for EXSDTI 2005/04 ASAHI KASEI [AKD5701-A] The function of the toggle SW [SW1] (DIT): Power control of AK4114. Keep "H" during normal operation. Keep "L" when AK4114 is not used. [SW3] (PDN): Power control of AK5701. Keep "H" during normal operation. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114. Serial Control The AK5701 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (CTRL) with PC by 10-wire flat cable packed with the AKD5701-A Connect PC CSN CCLK CDTI AKD5701-A 10 Wire Flat Cable 10pin Connector 10pin Header Figure 2. Connect of 10 wire flat cable 2005/04 ASAHI KASEI [AKD5701-A] Analog Input / Output Circuits (1) Input Circuits a) LIN, RIN, MIC Input Circuit R38 (Open) J1 LIN JP9 LIN LIN1 2 3 1 LIN1 LIN2 MR-552LS J5 LIN2 4 6 3 MIC J2 RIN JP10 RIN RIN1 2 3 1 RIN1 RIN2 MR-552LS R39 (Open) RIN2 Figure 3. LIN, RIN, MIC Input Circuit (a-1) LIN1, RIN1 input JP9 LIN JP10 RIN LIN1 LIN2 RIN1 RIN2 (a-2) LIN2, RIN2 input JP9 LIN JP10 RIN LIN1 LIN2 RIN1 RIN2 AKM assumes no responsibility for the trouble when using the above circuit examples. 2005/04 ASAHI KASEI [AKD5701-A] 2. Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD5701-A according to previous term. 2. Connect IBM-AT compatible PC with AKD5701-A by 10-line type flat cable (packed with AKD5701-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AK5701 Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD5701-A.exe" to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button Explanation of each buttons 1. [Port Reset] : 2. [Write default] : 3. [All Write] : 4. [Function1] : 5. [Function2] : 6. [Function3] : 7. [Function4] : 8. [Function5]: 9. [SAVE] : 10. [OPEN] : 11. [Write] : Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK5701-A. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet. 2005/04 ASAHI KASEI [AKD5701-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK5701, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK5701, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate IVOL There are dialogs corresponding to register of 18h and 19h. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK5701 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK5701, click [OK] button. If not, click [Cancel] button. 2005/04 ASAHI KASEI [AKD5701-A] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is "akr". 2005/04 ASAHI KASEI [AKD5701-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. The following is displayed. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is "aks". Figure 1. Window of [F3] 2005/04 ASAHI KASEI [AKD5701-A] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 2 opens. Figure 2. [F4] window 2005/04 ASAHI KASEI [AKD5701-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is "DAC_Stereo_ON.aks") Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is "*.ak4". [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. 2005/04 ASAHI KASEI [AKD5701-A] 7. [Function5 Dialog] The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens. Figure 4. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is "DAC_Output.akr") (2) Click [WRITE] button, then the register setting is executed. 2005/04 ASAHI KASEI [AKD5701-A] Figure 5. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is "*.ak5". [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. 2005/04 ASAHI KASEI [AKD5701-A] MEASUREMENT RESULTS 1.AK5701 Mode: EXT mode (Slave) [Measurement condition] * Measurement unit: AP2 (Audio Precision, System two, Cascade) * MCKI: 256fs * BCLK: 64fs * Bit: 16bit * Sampling Frequency: 44.1kHz * Measurement Frequency: 20 20kHz * Power Supply: AVDD=DVDD=VD=3.0V * Temperature: Room * Input Frequency: 1kHz [Measurement Results] 1.ADC characteristics (MIC Gain = 0dB, IVOL=0dB, ALC = OFF, LIN/RIN Result MGAIN=0dB LIN RIN 79.0dB 79.0dB 89.8dB 89.8dB 89.9dB 89.8dB ADC) S/(N+D) (-0.5dBFS) D-Range (-60dBFS) S/N MGAIN=+15dB LIN RIN 78.3dB 78.4dB 87.7dB 87.7dB 87.7dB 87.7dB 2.AK5701 Mode: PLL MASTER mode [Measurement condition] * Measurement unit: AP2 (Audio Precision, System two, Cascade) * MCKI: 12MHz * BCLK: 64fs * Bit: 16bit * Sampling Frequency: 44.0995kHz * Measurement Frequency: 20 20kHz * Power Supply: AVDD=DVDD=VD=3.0V * Temperature: Room * Input Frequency: 1kHz [Measurement Results] ADC characteristics Result MGAIN=0dB LIN RIN 78.7dB 78.3dB 89.3dB 89.3dB 89.3dB 89.3dB S/(N+D) (-0.5dBFS) D-Range (-60dBFS) S/N MGAIN=+15dB LIN RIN 77.9dB 77.5dB 87.4dB 87.3dB 87.4dB 87.3dB 2005/04 ASAHI KASEI [AKD5701-A] 3.Plot data AKM -60 AK5701 THD+N vs Input Level (fin=1kHz, GAIN=0dB) -64 -68 -72 -76 d B F S -80 -84 -88 -92 -96 -100 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 Figure 1. THD+N vs. Input Level AKM -60 AK5701 THD+N vs Frequency (fin=1kHz, GAIN=0dB) -64 -68 -72 -76 d B F S -80 -84 -88 -92 -96 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 2. THD+N vs. Input Frequency ASAHI KASEI [AKD5701-A] AKM +0 AK5701 Linearity (fin=1kHz, GAIN=0dB) -12 -24 -36 -48 d B F S -60 -72 -84 -96 -108 -120 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 +0 Figure 3. Linearity AKM +0 AK5701 Freqency Responce (fin=1kHz, GAIN=0dB) -0.2 -0.4 -0.6 -0.8 d B F S -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 4. Frequency Response 2005/04 ASAHI KASEI [AKD5701-A] AKM -60 AK5701 Crosstalk (fin=1kHz, GAIN=0dB) -68 -76 -84 -92 d B -100 -108 -116 -124 -132 -140 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 5. Crosstalk AKM -0 AK5701 FFT S/(N+D) -0.5dBFS (fin=1kHz, GAIN=0dB) -16 -32 -48 -64 d B F S -80 -96 -112 -128 -144 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 6. FFT Plot 2005/04 ASAHI KASEI [AKD5701-A] AKM -0 AK5701 FFT DR (fin=1kHz, GAIN=0dB) -16 -32 -48 -64 d B F S -80 -96 -112 -128 -144 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 7. FFT Plot AKM +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 AK5701 FFT S/N MGAIN=0dB 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 8. FFT Plot 2005/04 ASAHI KASEI [AKD5701-A] AKM -60 AK5701 THD+N vs Input Level MGAIN=+15dB -64 -68 -72 -76 d B F S -80 -84 -88 -92 -96 -100 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 Figure 9. THD+N vs. Input Level AKM -60 AK5701 THD+N vs Freqency (fin=1kHz, GAIN=+15dB) -64 -68 -72 -76 d B F S -80 -84 -88 -92 -96 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 10. THD+N vs. Input Frequency 2005/04 ASAHI KASEI [AKD5701-A] AKM +0 AK5701 Lineearity (fin=1kHz, GAIN=+15dB) -12 -24 -36 -48 d B F S -60 -72 -84 -96 -108 -120 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 +0 Figure 11. Linearity AKM +0 AK5701 Freqency Responce (fin=1kHz, GAIN=+15dB) -0.2 -0.4 -0.6 -0.8 d B F S -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 12.Freqency Response 2005/04 ASAHI KASEI [AKD5701-A] AKM -60 AK5701 Crosstalk (fin=1kHz, GAIN=+15dB) -68 -76 -84 -92 d B -100 -108 -116 -124 -132 -140 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 13.Crosstalk AKM +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 AK5701 FFT S/(N+D) -0.5dBFS MGAIN=+15dB 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 14. FFT Plot 2005/04 ASAHI KASEI [AKD5701-A] AKM +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 AK5701 FFT DR MGAIN=+15dB 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 15. FFT Plot AKM +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 AK5701 FFT S/N MGAIN=+15dB 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 16. FFT Plot 2005/04 ASAHI KASEI [AKD5701-A] Revision History Date 05/04/25 Manual Revision KM076903 Board Revision 0 Reason First Edition Contents IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. 2005/04 A B C D E JP1 GND REG_IN T1 TA48033F DVDD BCLK AVDD IN GND OUT 1 C1 0.1u E C2 0.1u C3 + 47u REG AVDD1 L1 1 1 2 JP2 AVDD_SEL E 2 C4 47u + 2 (short) AVDD CN1 24pin_1 6 5 4 3 2 1 REG1 T45_R 1 AVDD1 T45_O 1 DVDD1 T45_O 1 VD1 T45_O 1 AGND1 DGND1 T45_BK T45_BK 1 1 REG_IN C5 2 D AVDD1 DVDD1 VD1 C6 1 1 C7 2 2 1 D + AVDD R1 5.1 L2 1 1 2 R2 51 JP3 AVDD DVDD_SEL DVDD DVDD CN2 LRCK H JP4 CSP SDTO 7 8 9 9 CSP 5 6 U1 10u C8 0.1u 3 4 + + 10u C9 0.1u 2 2.2u C10 0.1u DVDD1 DVSS AVSS BCLK C12 47u + 2 (short) R3 51 7 LRCK VCOM DVDD AVDD 1 C11 (open) R4 VCOC 24 8 SDTO LIN1 23 1 + R7 51 10k C13 4.7n C14 2 CN4 24 23 22 21 20 19 1u 22 1 + R5 51 RIN1 C15 2 LIN1 RIN1 LIN2 RIN2 C MCKO 5701_EXSDTI 5701_EXLRCK 10 MCKO LIN2 21 1 + L 10 11 12 R6 51 AK5701 EXSDTI RIN2 1u C16 2 C 1u 20 1 + R8 51 11 C17 2 1u 19 EXBCLK 24pin_2 R9 51 12 EXLRCK MPWR CCLK MCKI CDTI PDN CSN JP5 MPWR R10 2.2k R11 2.2k R17 (open) R18 (open) JP6 MPWR 24pin_4 13 14 15 16 17 JP7 DVDD LVC_SEL LVC VD B R40 51 R12 51 R13 51 R14 51 R15 51 18 R16 51 B VD1 1 13 14 15 16 17 2 VD 24pin_3 C18 47u 1 + 2 5701_EXBCLK 5701_MCKI CDTI JP8 CCLK A A CSN PDN 18 L3 (short) CN3 CCLK Title Size Document Number AKD5701-A AK5701 Sheet E Rev A3 Date: A B C D 0 1 of Tuesday, December 14, 2004 5 A B C D E R38 (Open) E E J1 LIN 2 3 1 JP9 LIN LIN1 LIN1 LIN2 MR-552LS J5 MIC 6 4 3 LIN2 D J2 RIN 2 3 1 JP10 RIN RIN1 RIN1 RIN2 D MR-552LS R39 (Open) RIN2 C C B B A A Title Size Document Number AKD5701-A Input Sheet E Rev A3 Date: A B C D 0 2 of Tuesday, December 14, 2004 5 A B C D E for 74AC74,74VHC4040,74HC14 VD 1 for 74LVC07ANS LVC E C19 0.1u C20 0.1u C21 0.1u + C23 47u C22 0.1u E D 2 D EXT_MCLK VD VD JP11 MKFS U2 10 11 CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 U3A Q 5 12 11 D CLK U3B Q 9 R19 short MCKI PR D CLK 3 PR 2 256fs 512fs 1024fs MCKO 10 4 64fs 32fs 16fs JP12 EXT_BCLK BLCK_SEL C CL Q 6 CL Q 8 C 13 74AC74 74AC74 1 2fs 1fs JP13 EXT_LRCK LRCK_SEL 74VHC4040 MCKO J3 EXT/BCLK 2 3 1 EXTCLK/BCLK R20 51 JP14 EXT1 MR-552LS AVSS B B J4 EXT/LRCK 2 3 1 EXTCLK/LRCK R21 51 JP15 EXT2 Title Size Document Number A MR-552LS A AKD5701-A CLOCK Sheet E Rev A3 Date: A B C D 0 3 of Friday, January 28, 2005 5 A B C D E VD E R22 10k U4A 2 1 4 K C24 10u 2 1 U4B 3 VD 74HC14 74HC14 3 C25 0.1u C26 0.1u 2 1 L A D1 HSU119 E H SW1 DIT + VD C27 0.47u R23 18k 41 48 46 45 44 42 39 47 D DIF0 DIF1 OCKS0 OCKS1 1 2 3 4 8 7 6 5 1 43 AVSS VCOM 40 38 TEST1 AVDD INT1 RX3 RX2 RX1 RX0 NC NC R 37 SW2 U5 D U4C INT0 36 5 6 R24 1k K LED1 ERF A MODE2 2 IPS0 VD 74HC14 NC OCKS0 35 OCKS0 RP1 5 4 3 2 1 3 DIF0 OCKS1 34 OCKS1 OCKS0 OCKS1 4 TEST2 CM1 33 47k 5 DIF1 C 6 NC AK4114 CM0 32 VD JP16 XTI EXTCLK/BCLK 5701_MCKO C PDN 31 1 7 DIF2 XTI 30 C28(open) X1 11.2896MHz C29 (open) IPS1 XTO 9 P/SN DAUX 28 2 8 29 DAUX 10 XTL0 MCKO2 27 11 B XTL1 BICK 26 4114_BICK B 12 VIN MCKO1 COUT UOUT DVDD BOUT VOUT TVDD DVSS DVSS LRCK TX0 TX1 SDTO 25 13 14 15 16 17 18 19 20 21 22 23 C30 0.1u + C31 0.1u + 1 2 1 2 C32 10u VD PORT1 A C33 10u VD 4114_MCKO 4114_LRCK A IN VCC GND 3 2 1 VD C34 0.1u TOTX141 24 Title Size Document Number AKD5701-A DIT Sheet E Rev A3 Date: A B C D 0 4 of Thursday, December 02, 2004 5 A B C D E VD U6 E R25 R26 R27 R28 330 330 330 330 5701_EXBCLK 11 Y8 A8 9 E 5701_EXLRCK 12 Y7 A7 8 U7A MCKO 1 2 5701_MCKO 5701_MCKI 13 Y6 A6 7 74LVC07ANS U7B BCLK 3 4 5701_EXSDTI 14 Y5 A5 6 EXSDTI LRCK 5 74LVC07ANS U7C 6 PDN 15 Y4 A4 5 74LVC07ANS U7D SDTO 9 8 MCKI BCLK LRCK SDTO VD PORT2 1 2 3 4 5 10 9 8 7 6 CDTI D 16 Y3 A3 4 74LVC07ANS R29 DSP1 D CCLK 17 Y2 A2 3 VD 10k BCLK-DIT EXBCLK-DIT EXT EXTBCLK JP17 4114_BICK EXT_BCLK EXTCLK/BCLK CSN 18 Y1 A1 2 10 GND G2 19 BCLK_SEL JP18 C35 0.1u 20 VCC G1 1 74LVC541 LRCK-DIT EXLRCK-DIT EXTLRCLK EXT LRCK_SEL 4114_LRCK EXTCLK/LRCK EXT_LRCK C C LVC + C36 47u DAUX VD R30 R31 R33 10k 10k 10k R32 R35 R34 2 1 470 470 470 EXT_MCLK 4114_MCKO MCKI EXTCLK/BCLK JP19 MCKI EXBCLK EXLRCK EXSDTI VD 1 2 3 4 5 PORT4 10 9 8 7 6 PORT3 1 2 3 4 5 10 9 8 7 6 CSN CCLK CDTI MCKI_SEL DSP2 R36 SDTO B B CTRL 10k VD K VD JP20 EXSDTI D2 HSU119 R37 10k U4D 9 8 11 SDTO U4E 10 A L 3 1 H SW3 PDN 2 74HC14 74HC14 A C37 0.1u U4F 13 12 U7E 11 10 A 74LVC07ANS U7F 13 12 Title Size Document Number 74HC14 74LVC07ANS AKD5701-A LOGIC Sheet E Rev A3 Date: A B C D 0 5 of Friday, December 17, 2004 5 |
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