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ASAHI KASEI [AKD4115-A] AKD4115-A AK4115 Evaluation Board Rev.3 GENERAL DESCRIPTION AKD4115 is the evaluation board for AK4115, 192kHz digital audio transceiver. This board has optical, cannon connector (XLR), and BNC connectors to interface with other digital audio equipment. Ordering guide AKD4115-A --Evaluation board for AK4115 (A cable for connecting the printer port (parallel port) of IBM-AT compatible PC and control software are packed with this document. Please note that the control software does not operate on Windows NT) FUNCTION Digital interface -S/PDIF : 8 channel input (optical, BNC or XLR) 2 channel output (optical, BNC or XLR) - Serial audio data I/F : 1 input (for DIT data input. 10-pin port) 1 output (for DIR data output. 10-pin port) -B,C,U,V bit : 1 input/output port (10-pin port) -Serial control data I/F 1 input/output port (10-pin port) 5V Opt RX0 REG 3.3V GND Control RX1 RX7 Opt TX0 AK4115 TX1 B,C,U,V Serial Data in (To DIT) Serial Data out (From DIR Figure 1. AKD4115-A Block Diagram *Circuit diagram and PCB layout are attached at the end of this manual. 2006/08 ASAHI KASEI [AKD4115-A] Evaluation Board Manual Operating sequence (1) Set up the power supply lines. [+ 5V] (Red) = 5V [GND] (Black) = 0V Each supply line should be distributed from the power supply unit. (2) Set up the evaluation mode and jumper pins. (Refer to the following item.) (3) Connect cables. (Refer to the following item.) (4) Power on. The AK4115 should be reset once bringing PDN (SW2) "L" upon power-up. Evaluation modes (1) Evaluation for DIR MCLK BICK LRCK SDTI S/PDIF Optical, XLR or BNC connector AK4115 (DIR) PORT2 (10pin Header) MCLK BICK LRCK SDTI DAC AKD4115-A The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical connector(PORT1: TORX176), BNC connector or cannon connector(XLR). The AKD4115 can be connected with the AKM's DAC evaluation board via 10-pin cable. a. Set-up of Bi-phase Input RXP0/RXN0 and RX1-7 should not select BNC at the same time. a-1. RXP0/RXN0 Connector Optical (PORT1) XLR (J1) BNC (J2) JP2(RXP0) JP3(RXN0) OPT BNC XLR XLR BNC BNC Table 1. Set-up of RXP0/RXN0 a-2. RX1, 2, 3, 4, 5, 6, and 7 can be inputted from a BNC (J2) connector only. Only RX1, RX2 and RX 3 can be used in parallel mode. The jumper which selects the Rx channel should be Short. Input JP RX1 JP4 Short RX3 RX4 RX5 RX2 JP6 JP7 JP8 JP5 Short RX4 RX5 Short Table 2. Set-up of RX1, 2, 3, 4, 5, 6 and 7 RX6 JP9 RX6 RX7 JP10 RX7 2006/08 ASAHI KASEI [AKD4115-A] a-3. Set-up of AK4115 input path In Parallel Mode you will need to use SW1_1 & SW1_5. In Serial Mode you will need to use IPS2-0 bits. IPS1 pin IPS0 pin (SW1_5) (SW1_1) INPUT Data IPS2 bit IPS1 bit IPS0 bit 0 0 0 RX0 0 0 1 RX1 0 1 0 RX2 0 1 1 RX3 1 0 0 RX4 1 0 1 RX5 1 1 0 RX6 1 1 1 RX7 (In parallel mode, IPS2 is fixed to "0") Table 3. Recovery Data Select b. Set-up of clock input and output The signal level outputted/inputted from PORT2 is 3.3V. MCLK SDTO LRCK BICK PORT2 DIR 1 Default 5 GND GND GND Figure 2. PORT2 pin layout b-1. MCKO1/MCKO2 The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2 is selected by OCKS 1-0. Output JP12 signal Default MCKO1 MCKO1 MCKO2 MCKO2 Table 4. MCKO1/MCKO2 set-up OCKS1 pin (SW3_2) OCKS1 bit 0 0 1 1 OCKS0 pin (SW3_3) OCKS0 bit 0 1 0 1 (X'tal) MCKO1 NC 10 GND 6 MCKO2 fs (max) 96 kHz 96 kHz 48 kHz 192 kHz Default 256fs 256fs 256fs 256fs 256fs 128fs 512fs 512fs 256fs 128fs 128fs 64fs Table 5. Master Clock Frequency Select 2006/08 ASAHI KASEI [AKD4115-A] b-2. Set-up of BICK and LRCK input and output Please select SW 3_7 (DIR_I/O) according to the setup of audio format of AK4115 (Refer to Table 7). Audio format SW3_7 (DIR_I/O) Slave mode 0 Master mode 1 Table 6. DIR_I/O set-up c. Set-up of Audio format It sets up by SW 1_2 and SW 1_3 in parallel mode. Please set up DIF2-0 bit and AES3 bit in serial mode. Mode AES3 bit 0 0 0 0 0 0 0 0 1 DIF2 bit 0 0 0 0 1 1 1 1 x DIF1 pin (SW1_3) DIF1 bit 0 0 1 1 0 0 1 1 x DIF0 pin (SW1_2) DIF0 bit 0 1 0 1 0 1 0 1 x 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S H/L H/L H/L H/L H/L L/H H/L L/H H/L LRCK DAUX SDTO I/O O O O O O O I I O 64fs 64fs 64fs 64fs 64fs 64fs 64-128f s 64-128f s 64fs I/O O O O O O O I I O Default BICK Default 0 1 2 3 4 5 6 7 8 24bit, Left AES3 Mode justified Table 7. Audio format 2006/08 ASAHI KASEI [AKD4115-A] d. Set-up of CM1 and CM0 The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_4, SW3_1 and JP18. In serial mode, it can be selected by PSEL bit and CM1-0 bits. PSEL pin (SW3_4) PSEL bit 0 0 0 0 1 1 1 CM1 pin (SW3_1) CM1 bit 0 0 1 1 0 0 1 CM0 pin (JP18) CM0 bit 0 1 0 1 0 1 0 SDTO source RX DAUX RX DAUX DAUX DAUX DAUX DAUX Default (UNLOCK) 0 1 0 PLL ON OFF ON ON ON ON OFF ON X'tal ON(Note) ON ON ON ON ON(Note) ON ON Clock source PLL(RX) X'tal PLL(RX) X'tal X'tal PLL(ELRCK) X'tal PLL(ELRCK) 1 ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-Down) Note: When the X'tal is not used as clock comparison for fs detection (XTL0, 1= "1,1"), the X'tal is OFF. Table 8. Clock Operation Mode Select 2006/08 ASAHI KASEI [AKD4115-A] (2) Evaluation for DIT 1. Synchronous mode MCLK BICK LRCK DAUX ADC PORT2 (10pin Header) PORT5 (10pin Header) MCLK BICK LRCK DAUX AK4115 (DIT) Optical, XLR or BNC connector S/PDIF AKD4115-A 2. Asynchronous mode EMCK EBICK ELRCK DAUX ADC PORT2 (10pin Header) EMCK EBICK ELRCK DAUX AK4115 (DIT) Optical, XLR or BNC connector S/PDIF AKD4115-A MCLK, BICK, LRCK and DAUX are input the via 10pin header (PORT5: DIT). The AKD4115-A can be connected with the AKM's ADC evaluation board via 10-pin cable. a. Set-up of a Bi-phase output signal TX0 and TXP0/TXN0 should not select an optical connector or a BNC connector at the same time. a-1. The data outputted from TXP1/TXN1 can be selected by OPS12-10 bit. Connector JP19 (TXP1) JP14 (TXN1) Optical (PORT4) OPT BNC XLR (J3) XLR XLR BNC (J4) BNC BNC Table 9. Set-up of TXP1/TXN1 a-2. As for TX0, only the loop back mode of RX corresponds. This mode is fixed to RX0 in parallel mode. In serial mode, it can be selected by OPS02-00 bits. Connector Optical (PORT4) BNC (J4) JP13 (TX0) JP19 (TXP1) OPT Open BNC Open Table 10. Set-up of TX0 JP14 (TXN1) BNC BNC 2006/08 ASAHI KASEI [AKD4115-A] b. Set-up of clock input and output b-1. In the case of synchronous mode (ASYNC bit="0" or Parallel mode) The used signals are MCKO1, MCKO2, LRCK, BICK, ELRCK and DAUX. The signal level outputted and inputted from PORT2 and PORT5 is 3.3V. Clock PORT MCLK PORT2 BICK PORT2 LRCK PORT2 DAUX PORT5 ELRCK PORT5(LRCK) Table 11. Clock input and output b-1-1. MCKO1/MCKO2 The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2 sets up by OCKS 1-0. Output JP12 JP15 JP11 signal MCKO1 MCKO1 MCKO MCKO1 MCKO2 MCKO2 MCKO MCKO2 Table 12. Selection of MCKO1/MCKO2 OCKS1 pin (SW3_2) OCKS1 bit 0 0 1 1 OCKS0 pin (SW3_3) OCKS0 bit 0 1 0 1 Default (X'tal) MCKO1 MCKO2 fs (max) 96 kHz 96 kHz 48 kHz 192 kHz Default 256fs 256fs 256fs 256fs 256fs 128fs 512fs 512fs 256fs 128fs 128fs 64fs Table 13. Master Clock Frequency Select b-1-2. Set-up of BICK and LRCK input and output Please select SW 3_7 (DIR_I/O) according the setup of audio format of AK4115 (Refer to Table 7). Audio format SW3_7 (DIR_I/O) Slave mode 0 Master mode 1 Table 14. Set-up DIR_I/O b-1-3. A set up of ELRCK As a reference clock of PLL, when using ELRCK clock, it inputs from PORT5 (LRCK). JP16 When inputting by AC coupling AC When inputting by CMOS level DC Table 15. Set-up of ELRCK input JP17 AC DC Default Default 2006/08 ASAHI KASEI [AKD4115-A] b-2. In the case of the asynchronous mode (ASYNC bit= "1" , This mode is supported in serial mode.) The used signals are EMCK, X'tal, EBICK, ELRCK, and DAUX. These signal levels outputted / inputted from PORT5 is 3.3V. Clock PORT MCLK PORT5 BICK PORT5 LRCK PORT5 DAUX PORT5 ELRCK PORT5 Table 16. Clock input and output b-2-1. Set-up of Master clock When EMCK is used MSEL bit Output signal JP15 1 EMCK EMCK Table 17. Selection of EMCK When X'tal is used as master clock Output signal MCKO1 MCKO2 JP12 JP15 JP11 MCKO1 MCKO MCKO1 MCKO2 MCKO MCKO2 Table 18. Selection of MCKO1/MCKO2 b-2-2. Setup of BICK and LRCK input and output Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4115 (Refer to Table 20). JP16 and 17 are fixed to the "DC" side. Audio format SW3_8 (DIT_I/O) Slave mode 0 Master mode 1 Table 19. DIT_I/O set-up c. Set-up of audio data format c-1. In case of synchronous mode. Please refer to Table 7. c-2. In case of asynchronous mode Mode 4 5 6 7 EDIF1 bit 0 0 1 1 ELRCK EBICK I/O I/O 0 24bit, Left justified H/L O 64fs O 1 24bit, I2S L/H O 64fs O 0 24bit, Left justified H/L I 64-128fs I 1 24bit, I2S L/H I 64-128fs I Table 20. Audio data format in asynchronous mode EDIF0 bit DAUX Default Default 2006/08 ASAHI KASEI [AKD4115-A] d. Set-up of PSEL, CM1 and CM0 d-1. In case of synchronous mode. Please refer to Table 8. d-2. In case of asynchronous mode CM1 bit CM0 bit (UNLOCK) PLL X'tal Clock source PLL (RX) X'tal PLL (RX) X'tal X'tal RX Clock I/O Note 3 Note 3 Note 3 Note 3 Note 3 SDTO Clock source X'tal or EMCK (Note 5) X'tal or EMCK X'tal or EMCK X'tal or EMCK X'tal or EMCK Clock I/O Note 4 Note 4 Note 4 Note 4 Note 4 Default 0 0 0 1 0 ON OFF ON ON ON ON(Note 2) ON ON ON ON RX "L" RX "L" "L" 1 0 1 1 1 - ON: Oscillation (Power-up), OFF: STOP (Power-Down) Note 2: When the X'tal is not used as clock comparison for sampling frequency detection (i.e. XTL1, 0 = "1, 1"), the X'tal is OFF. Note 3: MCKO1/2, BICK, LRCK Note 4: EMCK OR X'tal, EBICK, ELRCK, DAUX Note 5: When X'tal is OFF, the clock source supports EMCK only. Table 21. Clock Operation Mode Select 2006/08 ASAHI KASEI [AKD4115-A] B, C, U, V Inputs and output B(block start), C(channel status), U(user data) and V(validity) are inputted via 10pin header (PORT3: BCUV). When BCU_IO bit is set to "1", they are input signals. And when BCU_IO bit is set to "0", they are output signals. In parallel mode, they are fixed to output signals. Pin arrangement of PORT3 has become like Figure 3. VOUT VIN GND PORT3 BCUV 10 C U B 6 GND GND GND 1 Figure 3. PORT3 pin layout Serial control The AK4115 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect the included 10pin cable to PORT6 (uP-I/F) of the AKD4115-A. Take care of the direction of connector. There is a mark at pin#1. And the pin layout of PORT6 is as Figure 4 shows. Mode 4 wire Serial IIC SW1_5 L H GND 5 JP18 CDTO/CM0="H" (Short) SDA (Short) CM0="L" (Short) (Note) Note: In IIC mode, the chip address is fixed to "01". Table 22. Set-up of Parallel mode and Serial mode GND GND GND GND GND PORT6 uP I/F 2 10 1 Figure 4. PORT6 pin layout The evaluation board also includes control software and a software operation procedure is included in the evaluation board manual. CDTO CCLK CSN NC CDTI 9 2006/08 ASAHI KASEI [AKD4115-A] Toggle switch set-up SW2 PDN Reset switch for AK4115. Set to "H" during normal operation. Bring to "L" once after the power is supplied. LED indication LE1 INT0 LE2 INT1 Bright when INT0 pin goes to "H". Bright when INT1 pin goes to "H". DIP switch (SW1) set-up: -off- means "L" No. Switch Name Function 1 IPS0 Set-up of IPS0 pin. (in parallel mode) 2 DIF0 Set-up of DIF0 pin. (in parallel mode) 3 DIF1 Set-up of DIF1 pin. (in parallel mode) 4 XSEL Set-up of XSEL pin. (in parallel mode) "L": X'tal 1, "H": X'tal 2 Set-up of IPS1 pin. (in parallel mode) 5 IPS1/IIC Set-up of IIC pin. (in serial mode) "L": 4 wire Serial, "H": IIC 6 7 P/SN TEST Set-up of P/SN pin. "L": Serial mode, "H": parallel mode Set-up of TEST pin. (always "OFF") Set-up of ACKS pin. (in parallel mode) 8 ACKS "L": Manual Setting, "H": Auto Setting Table 23 DIP switch (SW3) set-up: -off- means "L" No. Switch Name Function 1 CM1 Set-up of CM1 pin. (in parallel mode) 2 OCKS1 Set-up of OCKS1 pin. (in parallel mode) 3 OCKS0 Set-up of OCKS0 pin. (in parallel mode) Set-up of PSEL pin. (in parallel mode) 4 PSEL "L": S/PDIF Input, "H": ELRCK Input Clock 5 XTL0 Set-up of XTL0 pin. 6 XTL1 Set-up of XTL1 pin. Set-up of the transmission direction of 74AC245 DIR_I/O 7 "L": When inputting from PORT2, "H": When outputting from PORT2 Set-up of the transmission direction of 74AC245 8 DIT_I/O "L": When inputting from PORT5, "H": When outputting from PORT5. Table 24 Set-up of XSEL, XTL1 and XTL0 SW1_4 XSEL 0 1 Status X'tal #1 X'tal #2 Power-Up Power-Down Power-Down Power-Up Table 25. Setting of X'tal oscillator X'tal Frequency X'tal #1 11.2896MHz 12.288MHz 24.576MHz (Use channel status) Table 26. Reference X'tal frequency X'tal #2 12.288MHz 11.2896MHz 22.5792MHz Default OFF OFF OFF OFF OFF OFF OFF OFF Default OFF OFF OFF OFF OFF OFF ON OFF SW3_6 XTL1 0 0 1 1 SW3_5 XTL0 0 1 0 1 Default 2006/08 ASAHI KASEI [AKD4115-A] Jumper set up. No. Jumper Name 1 D3V/VD 2 RXP0 3 4,5,6 7,8,9,10 RXN0 RX1-3 RX4-7 DIR MCLK , DIT MCLK TX0 11,12 13 14 TXN1 15 MCLK 16,17 ELRCK 18 SDA/CDTO 19 TXP1 Function Set-up of Power supply source for 74AC245. D3V : D3V (default) VD : VD Set-up of RXP0 input circuit. OPT : Optical (default) XLR : XLR BNC : BNC Set-up of RXP0 input circuit. OPT : Optical (default) BNC : BNC Set-up of RX1-3 input circuit. RX4-7 set-up depending serial/parallel mode RX4-7 : Serial mode (default) DIF2-0,IPS0 : Parallel mode MCKO set-up for PORT5(DIT) and PORT2(DIR) MCKO1 : MCKO1 of AK4115 (default) MCKO2 : MCKO2 of AK4115 Set-up of TX0 output circuit. OPT : Optical BNC : BNC (default) Set-up of TXN1 output circuit. XLR : XLR BNC : BNC (default) MCLK input output selection of PORT5(DIT). MCKO : MCKO (default) EMCK : EMCK Set-up of ELRCK input signal. AC : AC DC : DC (default) Set-up of SDA/CDTO pin. 4 wire Serial : CDTO/CM0="H" (default) IIC : SDA Set-up of TXP1 input circuit. OPT : Optical (default) XLR : XLR BNC : BNC 2006/08 ASAHI KASEI [AKD4115-A] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4115-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4115-A by 10-line type flat cable (packed with AKD4115-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4115-A Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4115-A.exe" to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button Explanation of each buttons [Port Reset] : [Write default] : [All Write] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5]: [SAVE] : [OPEN] : [Write] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4115. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". 2006/08 ASAHI KASEI [AKD4115-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to the AK4115, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog]: Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to the AK4115, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate volume Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to the AK4115 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to the AK4115, click [OK] button. If not, click [Cancel] button. 2006/08 ASAHI KASEI [AKD4115-A] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is "akr". 2006/08 ASAHI KASEI [AKD4115-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is "aks". Figure 5. Window of [F3] 2006/08 ASAHI KASEI [AKD4115-A] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 10 opens. Figure 6. [F4] window 2006/08 ASAHI KASEI [AKD4115-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 11. ( In case that the selected sequence file name is "DAC_Stereo_ON.aks") Figure 7. [F4] window(2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The extension of the file is "*.ak4". [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. 2006/08 ASAHI KASEI [AKD4115-A] 7. [Function5 Dialog] The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 12 opens. Figure 8. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 13. (In case that the selected file name is "DAC_Output.akr") (2) Click [WRITE] button, then the register setting is executed. 2006/08 ASAHI KASEI [AKD4115-A] Figure 9. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is "*.ak5". [OPEN] : The file extension assignment of the register setting file(*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. 2006/08 ASAHI KASEI [AKD4115-A] Revision History Date (YY/MM/DD) 04/12/08 06/02/15 06/06/15 Manual Board Revision Revision KM076400 0 KM076401 1 KM076402 2 Reason First edition Modification Contents 06/08/10 KM076403 3 * Circuit diagram was changed (page 1/3). * The R61 changed from 15k to 10k. Add the explanation P13 "Instruction for use" was added. Change control software Control software was updated: 1.0 3.0 Control software manual was changed: P13-14 P14-21 Error Correct P10 * SW_6 SW_5 * CDTO/CM0="H" CDTO/CM0="H" (Short) * SDA and CM0="L" SDA (Short) CM0="L" (Short) Change device Revision AK4115: Rev. C Rev. D Delete the explanation P13 "Instruction for use" was deleted. Change control software Control software was updated: 3.0 4.0 IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. 2006/08 5 4 3 2 1 CN5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 RX3 RX2 AVDD AVDD RX1 RXP0 RXN0 ACKS P/SN IPS0/RX4 AVDD + C19 10u C22 C20 0.1u C21 0.1u + 0.1u D D C23 4.7u 61 57 62 60 64 58 54 63 59 53 52 56 U7 CN6 AVSS AVSS 55 51 50 ACKS IPS0/RX4 VCOM RXN0 AVDD AVDD AVDD AVSS RX3 RX2 RX1 RXP0 P/SN R 49 R61 10k 49 1 DIF0/RX5 C24 100p R62 24k C25 0.01u CN7 1 DIF0/RX5 FILT 48 48 XTL1 2 TEST 2 TEST XTL1 47 47 3 DIF1/RX6 3 DIF1/RX6 XTL0 46 XTL0 46 4 PDN 4 PDN PSEL 45 PSEL 45 C 5 XSEL/RX7 5 XSEL/RX7 IPS1/IIC 44 IPS1/IIC 44 C 6 DVDD + VIN C26 10u C27 0.1u 6 DVDD BVSS 43 43 7 7 VIN DVSS 42 + 10u OCKS0/CSN/CAD0 Title Size A3 Date: Document Number C28 C29 0.1u 42 DVDD 8 DAUX 8 DAUX DVDD 41 41 9 MCKO1 9 DVSS AK4115 OCKS0/CSN/CAD0 40 40 10 10 MCKO1 OCKS1/CCLK/SCL 39 OCKS1/CCLK/SCL 39 11 MCKO2 11 MCKO2 CM1/CDTI/SDA 38 CM1/CDTI/SDA 38 12 B 12 + C30 10u C31 0.1u OVDD CM0/CDTO/CAD1 37 CM0/CDTO/CAD1 37 B 13 BICK 13 OVSS INT1 36 INT1 36 14 14 BICK INT0 35 INT0 35 15 SDTO 15 SDTO ELRCK 34 ELRCK 34 16 LRCK 16 LRCK EBICK OVDD EMCK 33 EMCK 33 VOUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OVSS TVDD XTO1 XTO2 TVSS TXN1 TXP1 XTI1 XTI2 TX0 C U B C32 0.1u C34 10u + X1 2 12.288MHz 1 C35 5p X2 2 11.2896MHz 1 C37 5p C38 5p + C33 0.1u C39 10u A C36 5p 32 A VOUT TVDD TXP1 TXN1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 OVDD 31 32 EBICK TX0 B C U AKD4115 Rev CN8 Sockt Thursday, August 10, 2006 Sheet 1 3 1 of 3 5 4 3 2 5 4 3 2 1 CN4 For U6 VD D3V For U1, U2, U5 D3V VD JP1 1 D3V 2 3 VD PORT1 For U3, U4 D3V/VD 6 5 6 5 GND VCC GND OUT 4 3 2 1 L1 10u 2 VD 49 50 R1 JP2 1 C7 1 2 C8 + TORX176 C1 C2 C3 C4 C5 C6 0.1u 10u 51 OPT XLR BNC 0.1u D 0.1u0.1u0.1u 0.1u 0.1u 470 T1 1 3 5 2 4 6 AVDD P/SN/ANS ACKS AVDD P/SN/ANS ACKS RXN0 RXP0 52 D DA02-F 4 T2 LP2950A R3 +5V L2 R2 C9 53 54 55 56 57 8 0.1u C10 10u 2 R4 VD TVDD/VDD 2 AVDD OUT GND 1 1 IN 3 1 2 1 4 3 3 1 1:1 5 110 0.1u short + JP3 1 XLR 2 3 BNC 2 C11 47u 2 1 4 J1 XLIN C13 C12 0.1u RX1 short T3 TA48M033F R6 DVDD J2 RX0 2 3 4 5 1 R5 58 59 60 61 75 0.1u 1 1 JP4 JP5 JP6 2 2 2 JP7 1 RX4 2 3 IPS0 OUT GND 2 1 IN 1 1 + C15 47u AVDD AVDD RX2 short R7 OVDD + 2 2 C14 47u 3 1 IPS0 DIF0 DIF1 DIF2/XSEL IPS1/IIC P/SN/ANS TEST ACKS RP1 short C SW1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 D3V RX3 AVDD IPS0/RX4 R8 D3V 62 63 64 C short AVDD 9 8 7 6 5 4 3 2 1 47k JP8 1 RX5 2 3 DIF0 IPS1/IIC P/SN/ANS TEST ACKS DIF0/RX5 JP9 1 RX6 2 3 DIF1 JP10 1 RX7 2 3 DIF2/XSEL R9 D3V TEST DIF1/RX6 PDN DIF2/XSEL/RX7 DVDD VIN DAUX CN1 1 2 3 4 5 6 B TEST D3V 16 EMCK1 DAUX1 1A 1B 2A 2B 3A 3B 4A 4B G A/B D3V B 7 4Y GND 7 2 3 5 6 11 10 14 13 15 1 1Y 2Y 3Y 4 7 D1 1S1588 A K U1 10k D3V DVDD 14 14 9 12 100 100 R11 R12 1 U2A 74HC14 2 3 U2B 74HC14 4 VIN 7 8 9 R10 DAUX2 EMCK2 DAUX2 SW2 1 3 H L 100 C16 PDN 0.1u 2 JP11 1 3 MCKO1 2 MCKO2 MCKO1 MCKO MCKO2 OVDD 10 11 12 13 8 74LVC157 DIT_MCLK DIR_MCLK D3V/VD PORT2 10 9 8 7 6 JP12 MCKO1 1 2 3 MCKO2 100 100 100 R13 R14 R17 R19 R21 OVDD GND GND GND GND NC 1 2 3 4 5 DIR A R22 R23 100k 100k 47k 47k 47k 47k 47k 47k R70 R71 R72 R73 R74 R75 B0 B1 B2 B3 B4 B5 B6 B7 D3V/VD MCLK BICK LRCK SDTO 100 100 100 100 R15 R16 R18 R20 U3 20 18 17 16 15 14 13 12 11 A0 A1 A2 A3 A4 A5 A6 A7 DIR OE 2 3 4 5 6 7 8 9 1 19 BICK SDTO LRCK 14 15 16 A 47k 47k 47k 47k 47k 47k R76 R77 R78 R79 R80 R81 100 100 10 74AC245 GND DIR_I/O Title Size A3 Date: Document Number AKD4115-A Rev MAIN1 Thursday, August 10, 2006 Sheet 1 3 2 of 3 5 4 3 2 5 4 3 2 1 PORT3 GND T45_BK +5V JP19 T45_BK OPT XLR BNC TXP1 2 4 6 CN2 1 3 5 1 2 3 4 5 10 9 8 7 6 B C U VOUT VIN R24 R25 R26 R27 R28 100 100 100 100 100 B C VIN U VOUT TVDD TX0 17 18 19 20 D 1 1 BCUV +5V R29 R30 R31 R32 JP13 D 47k 47k 47k 47k TVDD/VDD PORT4 5 6 5 6 IN VCC IF GND 4 3 2 1 VD TX0 1 3 21 22 23 24 25 OPT 2 T4 BNC TOTX176 R33 1k C17 DA02-F 4 8 R34 TXP1 0.1u 2 R36 75 2 4 1 3 3 J3 J4 TX0 2 3 4 5 1 DA02-F 4 8 R37 BNC 430 XLOUT TXN1 4 1 1 1:1 5 150 GND GND GND GND NC C PORT5 10 9 8 7 6 1 2 3 4 5 DC 2 DAUX1 R42 AC JP16 1 3 R40 R41 DIT ELRCK 100k 100k 100k R84 R85 R86 R87 R88 R89 47k 47k 47k 47k 47k 47k B0 B1 B2 B3 B4 B5 B6 B7 D3V/VD MCLK BICK LRCK DAUX U4 R82 R83 20 GND 10 14 U2C LE1 R45 A K 6 5 74HC14 INT0 1k 7 14 U2D LE2 D3V R47 A K 8 9 74HC14 R48 VD U5 16 INT1 1k 7 14 R51 R54 B U2E 10k 10k R52 R55 470 470 11 74HC14 10 10 8 6 4 2 12 U2F 9 7 5 3 1 P/SN/ANS G A/B GND CSN R56 SCL/CCLK SDA/CDTI 51 SDA(ACK)/CDTO 4Y 12 1 U6A 14 PORT6 1A 1B 2A 2B 3A 3B 4A 4B D3V 10k 14 7 uP-I/F 7 74HC14 R58 D3V CM1/FS1 OCKS1/FS2 OCKS0/FS0 PSEL XTL0/CKS1 XTL1/TRANS DIR_I/O DIT_I/O RP2 JP18 D3V R57 8 7 13 SW3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 D3V D3V/VD A 9 8 7 6 5 4 3 2 1 47k DIR_I/O DIT_I/O 7 7 7 7 7 5 4 1 1 MCKO 2 EMCK T5 1:1 2 1 5 3 XLR JP14 JP15 TXN1 MCLK 1 3 R38 D3V/VD MCKO EMCK1 26 27 28 100k 100 100 18 17 16 15 14 13 12 11 A0 A1 A2 A3 A4 A5 A6 A7 DIR OE 2 3 4 5 6 7 8 9 1 19 R96 R97 R90 R91 R92 R93 R94 R95 47k 47k 47k 47k 47k 47k 100 100 OVDD OVDD 29 30 31 EBICK C DIT_I/O 32 74AC245 C18 CN3 JP17 0 R44 R46 0.1u ELRCK 1 3 EMCK2 EMCK ELRCK INT0 INT1 CM0/CDTO/CAD1 33 34 35 36 37 38 B 75 DC 2 AC D3V R49 470 2 3 5 6 11 10 14 13 15 1 1Y 2Y 3Y 4 7 9 R50 R53 VD 100 100 CM1/CDTI/SDA OCKS1/CCLK/SCL OCKS0/CSN/CAD0 39 40 41 42 2 74LS07 DVDD DVDD 74LVC157 10k R60 R59 10k 1 SDA 3 CDTO/CM0=H 5 2 4 6 100 IPS1/IIC IPS1/IIC PSEL XTL0 XTL1 43 44 45 46 47 48 12 74LS07 A CM0=L SDA/CDTO 100 3 U6B 4 74LS07 9 U6D 8 74LS07 U6F 13 5 U6C 6 74LS07 11 U6E 10 74LS07 Title Size A3 Date: 2 AKD4115-A Document Number Rev MAIN2 Thursday, August 10, 2006 Sheet 1 3 3 of 3 3 |
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