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M-NARA
(AED30A)
ULTRA LOW POWER MPEG LAYER3 AUDIO ENC/DECODER
PRELIMINARY DATA SHEET VER1.2(2003.2.26)
MOBILE DOCTOR Co.
- INDEX 1. GENERAL DESCRIPTION 2. FEATURES 3. FUNCTIONAL DESCRIPTIONS 4. EXTERNAL INTERFACE DESCRIPTIONS 5. FLOWCHART FOR SOFTWARE APPLICATIONS 6. PIN CONNECTIONS 7. APPLICATION NOTE 8. PACKAGE DIMENTION
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1. GENERAL DESCRIPTION
M-NARA(AED30A) is a ultra low power digital audio encoder/decoder, capable of encoding/decoding ISO/IEC 11172-3 Layer III audio format. Fully hardwired design skill provides lower power consumption and cost than any other chip using DSP. Thus, M-NARA is ideally suited for portable electronics. For user convenience, various interfaces are supported. Host data reading/writing is executed with the serial I2C I/F. With the serial I2S or 8bit PIO I/F, bit streams for encoding or decoding are transferred. The external AD/DA are interfaced with the I2S format. Easily accessible host interface has various functions and controls, such as software reset, digital volume control, test mode, mute, interrupt, encoder/decoder status check, power down mode, .... M-NARA has the capability of voice recoding/decoding with MPEG2 LAYER III algorithm(16kHz sampling freq. 8~32kbps mono). At that time, the external MCU doesn't execute any operation. The voice signal from ADC is compressed and transmitted to external memory through I2S or parallel PIO interface. For minimum power consumption, the external MCU can power down the encoder/decoder. In typical application, M-NARA is suitable for low power application in consumer digital audio system, multimedia and digital system.
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2. FEATURES
MPEG 1/2 Audio layer 3 encoder/decoder single chip Fully hardwired design for ultra low power and cost Various user interface (I2C, I2S, PIO) Host read/write access with I2C interface 16bits PCM data input/MP3 data output for encoder with I2C/I2S/PIO interface MP3 data input for decoder with I2C/I2S/PIO interface Internal PLL 12.288MHz single clock Need not program download Power down mode for reducing power consumption Power consumption - normal mode (encoder : 8mA, decoder : 6mA ) 3.3/2.5V power supply 64 pin TQFP
2.1 Encoder Features
Flexible encoding bit rate (MPEG1 : 32 ~ 320kbps, MPEG2 : 8 ~ 160kbps) Various audio source input (music, voice, radio, audio line-in, 16bit PCM data) Voice record/playback (16kHz sampling freq. 8~32kbps mono) function MPEG1 layer3 format 32, 44.1, 48kHz 16-bit stereo ADC sampled data/16bits PCM data input Flexible compression ratio(32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256, 320kbps) stereo/joint-stereo/mono encoded data serial/parallel output For music application MPEG2 layer3 format 16, 22.05, 24kHz 16-bit stereo ADC sampled data/wave file data input Flexible compression ratio(8, 16, 24, 32, 40, 48, 56, 64, 80, 96, 112, 128, 144, 160kbps) stereo/joint-stereo/mono encoded data serial/parallel output In case of 8Kbps case, only 16kHz mono encoding is possible. For voice application(16kHz 8~32kbps mono encoding)
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2.2 Decoder Features
MPEG1/2 Layer3 bit stream decoder 8 steps tempo control Digital volume control Digital bass control Digital treble control Mute control Ancillary data support
2.3 Typical Applications
Portable music player Voice recorder CD R/W recorder VoIP Sound card Digital audio/video recorder Mobile phone PDA Internet broadcasting system Notebook PC
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3. FUNCTIONAL DESCRIPTION 3.1 Overview
M-NARA makes a low power operation on encoding/decoding with MP3 bitstream data. It has compactlymade hardwired core that can operate at low frequency. Due to that, power consumption is less than any other DSP encoder/decoder. With this architecture, there is no process to download the MP3 program.
3.2 Architecture
M-NARA
BI2S I/F PIO I/F AI2S I/F
ETC. Pins
EXTERNAL MEMORY
MP3 ENCODER CONTROL/ STATUS REGISER
EXTERNAL ADC
MCU
I2C I/F
OSC. CRY.
PLL I/F
PLL
MP3 DECODER
INTERNAL SRAM
AI2S I/F
EXTERNAL DAC
3.3 Internal PLL
The internal PLL is a low voltage, low cost, multi-clock generator. This can generate system clock and variou s tempo clocks such as 5%, 10%, 15%, and 20% offset against system clock. The input system clock is 12.288MHz.
3.4 External Audio Codec(ADC, DAC)
There is a I2S interface for the external AD/DA.
3.5 MPEG Codec/Arithmetic Logic/RAM
The MPEG codec is the MPEG1/2 layer3 encoder/decoder. The features of encoder/decoder are described at "2. FEATURES".
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3.6 DAC Mute
Host processor can control mute function.
3.7 Register Description
A standard I2C slave interface is implemented to control chip operation. With I2C I/F, it's possible to read from status registers, write to control registers, write 16bits PCM to encoder, write MP3 data to decoder and read MP3 output from encoder. With I2S/PIO interface, it's also possible to read/write PCM/MP3 data from/to encoder/decoder. All registers are composed of 8bit. The control registers are read/write and the status registers are read only.
3.7.1 Control Registers for ENC/DECODER 3.7.1.1 address 0x00 : interrupt masking, default 0xFF bit[7:5]: reserved bit[4] bit[3] bit[2] bit[1] bit[0] : decoder frame sync. : encoder output buffer full, input buffer full : encoder mute frame end : encoder mute frame start : encoder frame sync.
3.7.1.2 address 0x01 : interrupt enable MAX counter, default 0x01 bit[7:0] : MAX counter
3.7.1.3 address 0x02 : software reset, default 0x00 bit[7:5] : reserved bit[4] : enc/decoder core/register reset, auto cleared
bit[3:2] : reserved bit[1] bit[0] : encoder core reset, auto cleared : decoder core reset, auto cleared
3.7.1.4 address 0x03 : External ADC control, default 0x10 bit[7:5] : reserved bit[4] : external ADC output bypass to external DAC input enable
bit[3:1] : reserved bit[0] : ADC input selection, 0=reserved, 1=external ADC input
3.7.1.5 address 0x04 : reserved
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3.7.1.6 address 0x05 : External AD/DA control, default 0x10 bit[7:6] : reserved bit[5] bit[4] : external AD/DA channel polarity invert : external AD/DA MSB justified
bit[3:1] : reserved bit[0] : external AD/DA master clock enable
3.7.1.7 address 0x06 : reserved
3.7.1.8 address 0x07 : Internal PLL control (digital tempo control for decoder), default 0x0F bit[7:4] : reserved bit[3:0] : decoder fast/slow selection
Bit[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1XXX
Decoder DAC Speed(%) -20 -15 -10 -5 +5 +10 +15 +20 0
3.7.1.9 address 0x08 : reserved
3.7.1.10 address 0x09 : reserved
3.7.1.11 address 0x0A : encoder control, default 0x00 bit[7] : encoder power down
bit[6:5] : reserved bit[4] : encoder enable, 1=start, 0=stop
bit[3:0] : reserved
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3.7.1.12 address 0x0B : decoder control, default 0x00 bit[7] : decoder power down
bit[6:5] : reserved bit[4] : decoder enable, 1=start, 0=stop
bit[3:2] : reserved bit[1] bit[0] : decoder pause : decoder mute
3.7.1.13 address 0x0C : I2S bit stream IN/OUT control, default 0x00 bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] : LSB first for output bit stream : LSB first for input bit stream : falling clock edge detection for output bit stream : falling clock edge detection for input bit stream : I2S encoder MP3 bit stream output enable : I2S encoder 16bits PCM bit stream input enable : reserved : I2S decoder MP3 bit stream input enable
At 16bits PCM encoding mode(bit[2] = `1'), each bit[0] of register 0x04 and 0x05 must be set to `0'.
3.7.1.14 address 0x0D : PIO bit stream IN/OUT control, default 0x00 bit[7:4] : reserved bit[3] bit[2] bit[1] bit[0] : PIO encoder MP3 data output enable : PIO encoder 16BITS PCM data input enable : reserved : PIO decoder MP3 data input enable
At 16bits PCM encoding mode(bit[2] = `1'), each bit[0] of register 0x04 and 0x05 must be set to `0'.
3.7.1.15 address 0x0E : reserved
3.7.2 Control Registers for ENCODER 3.7.2.1 address 0x10 : MPEG1/2 selection, default 0x01 bit[7:1] : reserved bit[0] : MPEG1/2 selection, 1 = MPEG1 LAYER3, 0 = MPEG2 LAYER3
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3.7.2.2 address 0x11 : MPEG2 mode, default 0xB2 bit[7:6] : sampling frequency bit[5:4] : mode selection bit[3:0] : bit rate
At 8kbps case, only 16kHz mono encoding is possible.
Bit[7:6] 00 01 10 11
Sample freq.(kHz) 22.05 24 16 reserved
Bit[5:4] 00 01 10 11
mode stereo joint-stereo reserved mono
Bit[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Bit rate(kbps) reserved 8 16 24 32 40 48 56 64 80 96 112 128 144 160 reserved
3.7.2.3 address 0x12 : MPEG1 mode, default 0x19 bit[7:6] : sampling frequency bit[5:4] : mode selection bit[3:0] : bit rate
Bit[7:6] 00 01 10
Sample freq.(kHz) 44.1 48 32
Bit[5:4] 00 01 10
mode stereo joint-stereo reserved
Bit[3:0] 0000 0001 0010
Bit rate(kbps) reserved 32 40
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11
reserved
11
mono
0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
48 56 64 80 96 112 128 160 192 224 256 320 reserved
3.7.2.4 address {0x14, 0x13} : low pass filter threshold data, default {0x02, 0x40} bit[7:2] : reserved @0x14 bit[1:0] : high threshold data @0x14 bit[7:0] : low threshold data @0x13
3.7.2.5 address {0x16, 0x15} : high pass filter threshold data, default {0x00, 0x00} bit[7:2] : reserved @0x16 bit[1:0] : high threshold data @0x16 bit[7:0] : low threshold data @0x15
3.7.2.6 address {0x19, 0x18, 0x17} : reserved
3.7.2.7 address 0x1A : PCM data input burst data number, default 0x20 bit[7] : reserved
bit[6:0] : burst data number
3.7.2.8 address 0x1B : MP3 data output burst data number, default 0x08 bit[7:4] : reserved bit[3:0] : burst data number
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3.7.2.9 address {0x1D, 0x1C} : PCM data write, default {0x00, 0x00} bit[7:0] : high data @0x1D bit[7:0] : low data @0x1C
3.7.2.10 address {0x1F, 0x1E} : reserved
3.7.3 Control Registers for DECODER 3.7.3.1 address 0x20 : MP3 data write, default 0x00 bit[7:0] : MP3 data
3.7.3.2 address 0x21 : MP3 input burst data number, default 0x20 bit[7:0] : MP3 input burst data number
3.7.3.8 address {0x25, 0x24, 0x23, 0x22} : digital volume, default {0x10, 0x7F, 0x7F, 0x10} bit[7:0] : digital volume RR @0x25 bit[7:0] : digital volume RL @0x24 bit[7:0] : digital volume LR @0x23 bit[7:0] : digital volume LL @0x22
Bit[7] 0 1
sign normal Inverting
Bit[6:0] 00 ... 10 ... 7F
Volume index(dB) 16 ... 0 ... -111
Y = -X + 16, X=bit[6:0], Y= dB
3.7.3.4 address 0x26 : digital bass tone, default 0x00 bit[7:5] : reserved bit[4:0] : digital bass tone index, Y = X - 16, X=bit[4:0], Y= dB
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Bit[4:0] 00 01 ... 10 ... 1F
Tone index(dB) disable -15 ... 0 ... 15
3.7.3.5 address 0x27 : digital treble tone, default 0x00 bit[7:5] : reserved bit[4:0] : digital treble tone index, Y = X - 16, X=bit[4:0], Y= dB
Bit[4:0] 00 01 ... 10 ... 1F
Tone index(dB) disable -15 ... 0 ... 15
3.7.3.6 address 0x28 : Pre scale control for bass/treble, default 0x00 bit[7] : 0=auto, 1=manual
bit[6:4] : reserved bit[3:0] : pre scale factor, Y = -X, X=bit[3:0], Y= dB
Bit[3:0] 0 1 ... F
pre scale factor (dB) 0 -1 ... -15
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3.7.4 Status Registers for ENC/DECODER 3.7.4.1 address 0x30 : interrupt status, default 0x00 bit[7:5] : reserved bit[4] bit[3] bit[2] bit[1] bit[0] : decoder frame sync., auto cleared : encoder output buffer full, auto cleared : encoder mute frame end, auto cleared : encoder mute frame start, auto cleared : encoder frame sync., auto cleared
3.7.4.2 address 0x31 : I2C I/F data input/output request, default 0xXX bit[7] : encoder MP3 data output request
bit[6:5] : reserved bit[4] : encoder 16BITS PCM data input request
bit[3:1] : reserved bit[0] : decoder MP3 data input request
3.7.4.3 address 0x32 : PIO I/F data input/output request, default 0xXX bit[7] : encoder MP3 data output request
bit[6:5] : reserved bit[4] : encoder 16BITS PCM data input request
bit[3:1] : reserved bit[0] : decoder MP3 data input request
3.7.5 Status Registers for ENCODER 3.7.5.1 address 0x40 : reserved, default 0xXX bit[7:0] : reserved
3.7.5.2 address 0x41 : Encoded MP3 data, default 0xXX bit[7:0] : MP3 data
3.7.5.3 address 0x42 : reserved, default 0xXX bit[7:0] : reserved
3.7.5.4 address {0x44, 0x43} : Mute frame counter, default {0xXX, 0xXX} bit[7:0] : high counter @0x44 bit[7:0] : low counter @0x43
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3.7.5.5 address {0x46, 0x45} : Frame counter, default {0xXX, 0xXX} bit[7:0] : high counter @0x46 bit[7:0] : low counter @0x45
3.7.6 Status Registers for DECODER 3.7.6.1 address 0x50 : header information 1, default 0xXX bit[7] bit[6] : reserved : mpeg1/2, 0 = mpeg2, 1 = mpeg1
bit[5:4] : layer, 0 = reserved, 1 = layer3, 2 = layer2, 3 = layer1 bit[3] bit[2] bit[1] bit[0] : protection : sync. Error : CRC error : decoder error
3.7.6.2 address 0x51 : header information 2, default 0xXX bit[7:4] : bit rate index bit[3:2] : sampling freq bit[1] bit[0] Bit[7:4] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 : padding : private bit rate index(kbps) free format 32(MPEG1), 40(MPEG1), 48(MPEG1), 56(MPEG1), 64(MPEG1), 80(MPEG1), 96(MPEG1), 112(MPEG1), 128(MPEG1), 160(MPEG1), 8(MPEG2) 16(MPEG2) 24(MPEG2) 32(MPEG2) 40(MPEG2) 48(MPEG2) 56(MPEG2) 64(MPEG2) 80(MPEG2) 96(MPEG2) Bit[3:2] 00 01 10 11 sampling freq(kHz) 44.1(MPEG1), 22.05(MPEG2) 48.0(MPEG1), 24.00(MPEG2) 32.0(MPEG1), 16.00(MPEG2) reserved
192(MPEG1), 112(MPEG2) 224(MPEG1), 128(MPEG2) 256(MPEG1), 144(MPEG2) 320(MPEG1), 160(MPEG2) reserved 15
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3.7.6.3 address 0x52 : header information 3, default 0xXX bit[7:6] : mode bit[5:4] : mode ext. : joint-stereo{intensity stereo on/off, m/s stereo on/off} bit[3] bit[2] : copy : original
bit[1:0] : emphasis
Bit[7:6] 00 01 10 11
Mode Stereo Joint-stereo dual channel single channel
Bit[5:4] 00 01 10 11
mode ext. off, off on, off off, on on, on
Bit[1:0] 00 01 10 11
emphasis none 50/15uS reserved CCITT J.17
3.7.6.4 address 0x53 : bit stream buffer counter, default 0xXX bit[7:0] : bit stream buffer counter
3.7.6.5 address {0x55, 0x54} : frame counter, default {0xXX, 0xXX} bit[7:0] : high counter @0x55 bit[7:0] : low counter @0x54
3.7.6.6 address {0x57, 0x56} : CRC error counter, default {0xXX, 0xXX} bit[7:0] : high counter @0x57 bit[7:0] : low counter @0x56
3.7.6.7 address {0x59, 0x58} : ancillary data counter, default {0xXX, 0xXX} bit[7:0] : high counter @0x59 bit[7:0] : low counter @0x58
3.7.6.8 address 0x5A : ancillary data, default 0xXX bit[7:0] : ancillary data
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4. EXTERNAL INTERFACE DESCRIPTION 4.1 Host Interface (I2C I/F)
Configuration setting and status information reading is done by standard I2C interface. With device address writing, this chip is selected. Next issue is command sequences. Consecutive data reading/writing can be done. Because I2C slave mode is used only, the clock port(I2CC) is used as input port. I/F ports(I2CC/I2CD) must be pull-up on external board.
4.1.1 Device Address Selection Two input pins(I2CA2, I2CA1) are used to select I2C device address. Connect those pins either to VDD or to VSS. Bit[0] is for device read/write selection.'0' means writing and `1' means reading. See the following table for the proper device address selection.
I2C DEVICE ADDRESS A7 0 A6 I2CA2 A5 0 A4 I2CA1 A3 0 A2 0 A1 0 W/R 0/1
4.1.2 Read/Write Access write access S DEV_W A REG_ADD A DATA < bytes + ack.> A P
read access S DEV_W A REG_ADD A S DEV_R A DATA1 A DATA2 N P
< bytes + ack.>
bus protocol 1
I2CD(I/O)
S
I2CC(I)
0
P
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S : START condition, P : STOP condition A : acknowledge(I2CD LOW) N : not acknowledge(I2CD HIGH) DEV_W : device address with bit[0]='0' DEV_R : device address with bit[0]='1' REG_ADD : register address to read/write DATA : data which master write to register DATA1, DATA2 : data which master read from register Black region : from master to slave White region : from slave to master In write access, data transfer number(bytes + ack.) >= 1 In read access, data transfer number(bytes + ack.) >= 0
4.1.3 Control/Status Register Access Register read/write is done with I2C read/write access process. Most of all register need one register read/write processing. If multi read processing is required like decoding ancillary data(register 0x5A), it is possible with data transfer number increasing in read access. With I2C processing, following data transfer is possible, MP3 data writing(register 0x20) to decode, MP3 data reading(register 0x41) from encoder, 16bits PCM data writing(register {0x1D, 0x1C}) to encoder
4.2 1bit Serial Interface (BI2S I/F)
With I2S interface, 1bit serial bit stream(8bits encoder output/decoder input, 16bits encoder input) can be done. When internal buffer is empty at encoding/decoding, demand signal(SBREQ, SIBREQ) is asserted to `1'. Then data to encode/decode(SBD, SIBD) will be input/output with clock signal(SBC, SIBC). The serial data is accepted at rising clock edge(options). It is strongly recommended to hold the clock signal `0', if there is no input/output serial data. Three pins(SBC, SBD, SBREQ) are used at encoder output and decoder input mode, and 8bits MP3 data are used in this modes. Other pins(SIBC, SIBD, SIBREQ) are used at encoder input mode, this mode needs 16bits PCM input data.
4.2.1 Control Register Options The serial I/F options are controlled by the I2S bit stream IN/OUT control register(0x0C). The bit[7] is for MSB/LSB first option of encoder output data, bit[6] for encoder/decoder input data. The bit[5] is for rising/falling clock edge option of encoder output data, bit[4] for encoder/decoder input data. The other bits(bit[3:0]) is for I2S interface selection.
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4.2.2 Read/Write Access Encoder MP3 output(SBD output) / Decoder MP3 input(SBD input)
SBREQ(O)
SBC(I)
data valid latch at rising edge of clock
SBD(I/O)
MSB LSB MSB
Encoder 16bits PCM input
SIBREQ(o)
SIBC(I)
......
data valid latch at rising edge of clock
SIBD(I)
MSB
......
LSB
MSB
4.3 8bits Parallel Interface (PIO I/F)
With PIO interface, 8bits parallel data transfer(8bits encoder output/decoder input, 16bits encoder input) can be done. This I/F consist of 8bits data pins(PD7, ..., PD0) and the control pins(PCSn, PREADY, PEODn, PREADn, PWRITEn). When PEODn is `1', then it notices that available data output is ready or input buffer is empty. After verifying PEODn signal, the external MCPU sets PREADY signal to `1' when it is ready status of read/write. After that, PREADn/PWRITEn goes to `0' with data write/read. PREADY goes to `0' and PREADn/PWRITEn to `1'. The above procedure will be repeated until the data number register(0x1A, 0x1B, 0x21). After n byte read/write procedure, PEODn signal goes to `0'.
4.3.1 Control Register Options PIO I/F is controlled by the PIO bit stream IN/OUT control register(0x0D).
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4.3.2 Read/Write Access Encoder 16bits PCM input
PCSn(I )
PEODn(O)
PREADY(I)
PREADn(O) BYTE 1 HIGH BYTE 1 LOW BYTE n HIGH BYTE n LOW BYTE 1 HIGH BYTE 1 LOW
PD[7:0](I)
Encoder MP3 output
PCSn(I )
PEODn(O)
PREADY(I)
PWRITEn(O
PD[7 :0](O )
BYTE 1
BYTE n
BYTE 1
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Decoder MP3 input
PCSn(I)
PEODn(O)
PREADY(I)
PREADn(O)
PD[7:0](I)
BYTE 1
BYTE n
BYTE 1
4.4 External Audio Codec Interface (AI2S I/F)
The data is 16-bit, MSB/LSB-first, 2's complement. The AD/DA master clock is controlled by the external AD/DA control register(address 0x05 bit[0]), the MSB/LSB justified mode by bit[4] and the channel polarity by bit[5]. The MCLK clock is 256fs and the SCLK clock is 32fs. *fs is sampling frequency. The LRCK and SCLK are synchronized with MCLK The five pins(MCLK, SCLK, LRCK, SDTO, SDTI) are used for interface and there is no AD/DA power down interface pins..
4.4.1 Timing Characteristics Parameter Master Clock 256fs LRCK Frequency fs Serial Interface Timing SCLK Period SCLK Pulse Width Low Pulse Width High LRCK Edge to SCLK "rising" SCLK "rising" to LRCK Edge LRCK Edge to SDTO(MSB) SCLK "falling" to SDTO SDTI Hold Time SDTI Setup Time tSCK tSCKL tSCKH tLRS tSLR tDLR tDSS tSDH tSDS 8fs 4fs 4fs 4fs 4fs 1fs 1fs 1fs 1fs 256fs 256fs 256fs 256fs 256fs 256fs 256fs 256fs 256fs Symbol fCLK fs Min. 3.2768 12.8 Typ. 11.2896 44.1 Max. 14.7456 57.6 Units MHz kHz
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4.4.2 Timing Diagram
LRCK(O)
tSLR
SCLK(O)
t
LRS
t
SCKH
t SCKL
tSC K SDTOO(0) tSDH tSDS
SDTI(I)
tDLR
tDSS
4.4.3 Interface format The following format is MSB justified one. If bit numbers(15-14,~,4-3-2-1-0) are changed to "0-15,~,5-4-3-21", it is LSB justified format.
Left Channel
Right Channel
LRCK
15 1 4 4 3 2 1 0 15 1 4 4 3 2 1 0
SCLK (32fs)
MSB LSB
SDTO
15 14
1 0 15 14
1 0 15 14
ADC : 16 - b it, MSB- Firs t, Le ft- Justified
MSB LSB
SDTI
15 14
10
15 14
10
DAC : 16 - bit, MSB- Firs t, Rig ht ustified -J
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4.5 PLL Interface
The CLKI input pin is for the crystal/osc. system clock. The inverted clock feeds back from CLKO output pin for crystal usage. With EXTCLK(PLLBYPASS) input pin to `1', it is possible to use direct external input clock through CLKI pin. The IREF analog input pin is for bias current input and it is set with BSEL input pin. For charge pump output, LF output pin is used. External capacitor should be connected between this pin and analog ground.
4.6 Interrupt Interface
The output pin(IRQn) is used for a interrupt request. This pin is active `0' and the duration of `0' state is controlled by interrupt MAX counter register(address 0x01). The counter number is the system clock number. See the interrupt status register(address 0x30). The interrupt request can be masked by the interrupt masking register(address 0x00).
4.7 Power Down/Reset Interface
There are 5 powers down mode. The PLL clock disable mode : This mode can be made when PWDNn pin is `0' and then all logic doesn't operate. MP3 en/decoder power down mode : with setting bit7 of register 0x0a/0x0b to high, it is power on mode(low) at power up initial. For normal mode, PWDNn signal must be inactive(`1'). The RSTn input pin is for chip power reset. If it is `0', all logic of chip goes to initial state.
4.8 Power/Ground
VDD0~3 VSS0~3 VDDD0 VSSD0 VDDA0~1 VSSA0~1 VDDX0~2 VSSX0~2 : core power, 2.5V : core ground : PLL digital power, 2.5V : PLL digital ground : PLL analog power, 2.5V : PLL analog ground : External I/O PAD power, 3.3V : External I/O PAD ground
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5. FLOWCHART FOR SOFTWARE APPLICATIONS 5.1 Power Up Initial
START
// p o wer sw itch o n
RSTn = 1 N Y PWDNn = 1
// p o wer reset rel e ase check
: R STn(p in 56) = hig (R)
h
/ / chip powe r down r e lease : PWDNn(pin 6 4) = (R) high
IDLE_PROCESS
// id le p ro c essing fo r P LL stabilization : about 1mS
REG_WR(h0A, 0x 80) (R) REG_WR(h0B, 0x 80) (R)
/ / e ncode r cor e powe r down, de fa ult powe r on / / de code r cor e powe r down, de fa ult powe r on
END
/ / go to ne xt r o utine : e ncoding, de coding, | .
5.2 Interrupt Routine
START
// interrup t ro utine start
IREQn = 0 N Y REG_RD((R) h3 0) REG_DATA[7 :0]
// interrup t check : IR Qn(p in 53) = lo w (R)
// interrup t status read
// R EG_DATA(0x10) : d e co d e r fram e sy nc. ro ut ine // R EG_DATA(0x08) : enco d e r o utp ut b uffer ful l ro ut ine // R EG_DATA(0x04) : enco d e r m ute fram e end ro ut ine // R EG_DATA(0x02) : enco d e r m ute fram e st art ro ut ine // R EG_DATA(0x01) : enco d e r fram e sy nc. ro ut ine // int e rrup t ro ut ine end
INT_ROUTINE
END
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5.3 MP3 Encoding With External Audio ADC Input
5.3.1 MP3 Encoding With External Audio ADC Input : with BI2S I/F
START
// I2S enco de r routine st art
REG_ WR(h02, 0x 02) (R) REG_ WR(h1B, 0x 0C) (R) REG_ WR(h03, 0x 11) (R) REG_ WR(h05, 0x 01) (R) REG_ WR(h0C, 0x 08) (R) REG_ WR(h10, 0x 01) (R) REG_ WR(h12, 0x 19) (R) REG_ WR(h0A, 0x 10) (R)
// enco de r reset / / MP3 output burst data numbe r se tting // ADC t o DAC b ypass, ex te rnal ADC sel e ct // ex te rnal AD/DA Mast er cl o c k enab le // I2S enco de r MP3 o utput enab le // MP EG1 sel e ct // 44.1k Hz /jo int-st e reo / 128k bps select // enco de r enab le
SBREQ = 1 N Y I2S DATA_RD
// enco de r output req uest check
: SBR EQ p in = hig (R)
h
// I2S data read : SBC,SBD pin
CNT > R EG N Y
/ / output burst data counte
r : counte r > REG((R)h1
B)
END ? N Y REG_ WR(h02, 0x 10) (R) REG_ WR(h0A, 0x 80) (R) (R) REG_ WR(h0B , 0x 80 )
// enco de r end k e y check
// reg ist er, en/d eco de r co re reset / / e ncode r powe r down / / de code r powe r down
END
// I2S enco de r routine end
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5.3.2 MP3 Encoding With External Audio ADC Input : with PIO I/F
START
// P IO enco de r routine st art
REG_ WR(h02, 0x 02) (R) REG_ WR(h1B, 0x 0C) (R) REG_ WR(h03, 0x 10) (R) REG_ WR(h05, 0x 01) (R) REG_ WR(h0D, 0x 08) (R) REG_ WR(h10, 0x 01) (R) REG_ WR(h12, 0x 19) (R) REG_ WR(h0A, 0x 10) (R)
// enco de r reset / / MP3 output burst data numbe r se tting // ADC t o DAC b ypass, int e rnal ADC sel e ct // ex te rnal AD/DA Mast er cl o c k enab le // P IO enco de r MP3 o utput enab le // MP EG1 sel e ct // 44.1k Hz /jo int-st e reo / 128k bps select // enco de r enab le
PCSn = lo (R)
w
// P IO chip sel e ct enab le
PEODn = 1 N Y PIO DATA_RD
// enco de r output req uest check
: P EODn p in = hig (R)
h
/ / PIO data re ad : PREADY, PWRIT En, PD[7 :0]
CNT > R EG N Y PCSn = hig (R) h
/ / output burst data counte
r : counte r > REG((R)h1
B)
// P IO chip sel e ct d isab le
END ? N Y REG_ WR(h02, 0x 10) (R) REG_ WR(h0A, 0x 80) (R) (R) REG_ WR(h0B , 0x 80 )
// enco de r end k e y check
// reg ist er, en/d eco de r co re reset / / e ncode r powe r down / / de code r powe r down
END
// P IO enco de r routine end
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5.4 MP3 Decoding With External Audio DAC Output
5.4.1 MP3 Decoding With External Audio DAC Output : with BI2S I/F
START
/ / I2S de coding r o utine star t
REG_ WR(h02, 0x 01) (R) REG_ WR(h21, 0x 20) (R) REG_ WR(h05, 0x 01) (R) REG_ WR(h0C, 0x 01) (R) REG_ WR(h07, 0x 0F) (R) REG_ WR(h0B, 0x 10) (R)
/ / de code r re se t / / MP3 input burst data numbe r se tting // ex te rnal AD/DA Mast er cl o c k enab le / / I2S de code r MP3 input e nable // t e mpo / sp eed co ntrol fo r DAC / / de code r e nable
SBREQ = 1 N Y I2S DATA_WR
/ / de code r input re que s t che c k : SBREQ pin = (R)
high
// I2S d ata w rite : SBC,SBD p in
CNT > R EG N Y END ? N Y REG_ WR(h02, 0x 10) (R) REG_ WR(h0A, 0x 80) (R) REG_ WR(h0B, 0x 80) (R)
/ / input burst data counte r : counte r > REG((R)h2
1)
// MP 3 inp ut file end check
// reg ist er, en/d eco de r co re reset / / e ncode r cor e powe r down / / de code r cor e powe r down
END
// I2S d e co de r routine end
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5.4.2 MP3 Decoding With External Audio DAC Output : with PIO I/F
START
/ / PIO de code r ro utine star t
REG_ WR(h02, 0x 01) (R) REG_ WR(h21, 0x 20) (R) REG_ WR(h05, 0x 01) (R) REG_ WR(h0D, 0x 01) (R) REG_ WR(h07, 0x 0F) (R) REG_ WR(h0B, 0x 10) (R)
/ / de code r re se t / / MP3 input burst data numbe r se tting // ex te rnal AD/DA Mast er cl o c k enab le / / PIO de code r MP3 input e nable // t e mpo / sp eed co ntrol fo r DAC / / de code r e nable
PCSn = lo (R)
w
// P IO chip sel e ct enab le
PEODn = 1 N Y PIO DATA_WR
// decoder input request check : PEODn pin = (R)high
/ / PIO data write : PREADY, PREADn, PD[7 :0]
CNT > R EG N Y PCSn = hig (R) h
/ / input burst data counte r : counte r > REG((R)h2
1)
// P IO chip sel e ct d isab le
END ? N Y REG_ WR(h02, 0x 10) (R) REG_ WR(h0A, 0x 80) (R) REG_ WR(h0B, 0x 80) (R)
// MP 3 inp ut file end check
// reg ist er, en/d eco de r co re reset / / e ncode r cor e powe r down / / de code r cor e powe r down
END
// P IO d e co de r routine end
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6. PIN CONNECTIONS
6.1 Pin Configurations(Top View)
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6.2 Pin Description
The pin names with small letter `n' means active low signal(like as pin64 PWDNn).
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN NAME EXTCLK BSEL LF IREF VSSA0 VDDA0 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C SDTI SDTO LRCK SCLK MCLK NANDEN VSS0 VDD0 VSSX0 VDDX0 I2CC I2CD VSS1 VDD1 I2CA1 I2CA2 I/O I I O I I O I/O I/O I/O I I I/O I I External clock select PLL IREF input enable PLL charge pump output(ANALOG PAD) PLL bias current input(ANALOG PAD) PLL analog VSS(2.5V) PLL analog VDD(2.5V) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved External ADC serial data input External DAC serial data output External AD/DA channel clock output External AD/DA sampling clock output External AD/DA master clock output Short to GND Digital core VSS(2.5V) Digital core VDD(2.5V) Digital pad VSS(3.3V) Digital pad VDD(3.3V) I2C clock(needs a external PULL-UP) I2C data(needs a external PULL-UP) Digital core VSS(2.5V) Digital core VDD(2.5V) I2C device address selection 1 input(address bit4) I2C device address selection 2 input(address bit6) FUNCTION
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33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SBD SBC SBREQ PEODn PD0 PD1 PD2 VSSX1 VDDX1 PD3 VSS2 VDD2 PD4 PD5 PD6 PD7 PWRITEn PREADn / SIBREQ
I/O I O O I/O I/O I/O I/O I/O I/O I/O I/O O O
I2S bit stream data in/output(encoding output, decoding input) I2S bit stream clock input(encoding output, decoding input) I2S bit stream request output(encoding output, decoding input) PIO data end of DMA output PIO data bit 0 in/output PIO data bit 1 in/output PIO data bit 2 in/output Digital pad VSS(3.3V) Digital pad VDD(3.3V) PIO data bit 3 in/output Digital core VSS(2.5V) Digital core VDD(2.5V) PIO data bit 4 in/output PIO data bit 5 in/output PIO data bit 6 in/output PIO data bit 7 in/output PIO data write enable output PIO data read enable output I2S bit stream request output(encoding input)
51
PREADY / SIBD
I
PIO ready to send/receive input I2S bit stream data input(encoding input)
52
PCSn / SIBC
I
PIO chip select input I2S bit stream clock input(encoding input)
53 54 55 56 57 58 59 60 61 62 63 64
IRQn VSSX2 VDDX2 RSTn TESTEN VSS3 VDD3 CLKO CLKI VSSD0 VDDD0 PWDNn
O I I O I I
Chip interrupt output Digital pad VSS(3.3V) Digital pad VDD(3.3V) Power reset Short to GND Digital core VSS(2.5V) Digital core VDD(2.5V) Crystal clock output Crystal clock input, osc. Clock input PLL digital VSS PLL digital VDD(2.5V) Chip power down select
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7. APPLICATION NOTE
7.1 Indirect bit stream feeding
Host processor
M-NARA AED30A
DAC
Earphone
Bit stream data memory
ADC
7.2 Direct bit stream feeding
Host processor
M-NARA AED30A ADC
DAC
Ear p hone
Bit stream data memory
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7.3 Radio Antenna
Tuner
Various audio Resource (Audio Line In)
Pre-AMP
ADC
Microphone
BATTERY(1EA) M-NARA AED30A DAC Jack Earphone
DC/DC Converter
2.5V
MICOM
MEMORY
KEY
LCD
FLASH/ SMC/MMC
USB
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7.4 Power Connection Circuit
There are two power supplies(2.5V, 3.3V). VDD*(digital core), VDDD0(PLL digital) are supplied by VDD2.5V and the VDDX3.3V supplies to VDDX*(I/O pin power). The VDD2.5V is filtered by inductors and supplies to analog powers such as VDDA0(PLL analog). Also, the GND is filtered. VDDX3.3V can be replaced with VDD2.5V.
VDD2.5V VDDA 10uF 0.1uF 1m H 10uF 0.1uF 10uF 0.1uF VDDX3.3V
1m H GNDA GND GND
10K
TESTEN
PWDNn
VDDD0
VDDX2
VSSD0
VSS3
CLKI
64
63
62
61
60
59
58
57
56
55
54
53
52
IRQn
GND
VSSX2
10uF
51
50
Digital gr ound plane (Move right side ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
49
PWRITEn PD7 PD6 PD5 PD4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PD3 PD2 PD1 PD0 SBC SBD I2CA2
SW CLKO VDD3 RSTn
EXTCLK BSEL LF IREF VSSA0 VDDA0 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VDDX1
M-NARA
PEODn SBREQ
MCLK
NANDEN
VDDX0
LRCK
VDD0
VSSX0
VDD1
SCLK
SDTI
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I2CA1
SDTO
VSS0
I2CD
VSS1
I2CC
32
PREADn / SIBREQ
PREADY / SIBD
PCSn / SIBC
VDD2 VSS2
VSSX1
7.5 Application Circuit (Encoing/Decoding mode)
The uC/External Memory/External AD/DA are powered by VDDX*. Connect power/ground shown at "7.4 power connection circuit".
10p F
1M 1K 350nF 330 3.5nF
12.288MHz
GND
10p F
GNDA
uC
PREADn / SIBREQ 49
PREADY / SIBD 50
PCSn / SIBC
GND 64
63
62
61
60
59
58
57
56
55
54
53
52
51
PWRITEn PD7 PD6 PD5 PD4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 uC PARALLEL EXTERNAL MEMORY PD3 PD2 PD1 PD0 SBC SBD I2C addr e ss Selection I2CA2
TESTEN
PWDNn
VDDD0
VDDX2
VSSD0
VSSX2
CLKO
VDD3
RSTn
VSS3
CLKI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
EXTCLK BSEL LF IREF VSSA0 VDDA0 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C 17 18 19 20 21 22 23 24 25 26 27 28 29 30 4.7K 31
IRQn
VDD2 VSS2 VDDX1
M-NARA
VSSX1
PEODn SBREQ
MCLK
NANDEN
VDDX0
LRCK
VDD0
VSSX0
VDD1
SCLK
SDTI
CD DSP
GND
4.7K
EXTERNAL AD/DA
uC
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I2CA1
SDTO
VSS0
I2CD
VSS1
I2CC
32 (VDDX*, GND)

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