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CERAMIC SMD CRYSTAL CLOCK OSCILLATOR WITH VOLTAGE CONTROL
ABVFM SERIES
: PRELIMINARY
5.0 x 7.0 x 1.8mm
FEATURES: * Based on a proprietary analog multiplier * 2.5V to 3.3V +/- 10% operation * Tri-State Output * Ceramic SMD, low profile package * Ultra low Phase Jitter * 155.52MHz, 311.04MHz, 622.08MHz applications
APPLICATIONS: * xDSL, Cable Modems * Customer Premise Equipment (CPE) * ATM, SONET, SDH, STB * LAN / WAN Data Communications Equip.
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STANDARD SPECIFICATIONS:
PARAMETERS Frequency Range Operating Temperature Storage Temperature Overall Frequency Stability Supply Voltage (Vdd) Jitter (12KHz - 20MHz) Low Phase Noise 60 MHz to 320 MHz 0C to + 70C (see options) - 55C to + 125C 100 ppm max. (see options) 2.5V - 3.3 Vdc 10% RMS phase jitter < 0.6pS period jitter < 20pS peak to peak -130 dBc/Hz @ 1kHz Offset from 212.5MHz -140 dBc/Hz @ 10kHz Offset from 212.5MHz -145 dBc/Hz @ 100kHz Offset from 212.5MHz TBD Per Crystal +/- 50ppm 58mA min, 65mA typical, 75mA max. 45% min, 50% typical, 55% max. VOH = VDD-2V (VDD-1.025V min) VOL = VDD-2V (VDD-1.620V max) 0.7ns max, 0.4ns typical 0.7ns max, 0.4ns typical 1.6ns max, 1.2ns typical 45% min, 50% typical, 55% max 60mA max, 55mA typical. 45% min, 50% typical, 55% max 247mV min, 355mV typical, 454mV max -50mV min, 50mV max VOH = 1.6V max, 1.4V typical VOL = 0.9V min, 1.1V typical VOS = 1.125V min, 1.1V typical, 1.375V max VOS = 0mV min, 3mV typical, 25mV max 10A max, 1A typical 0.2ns min, 0.5ns typical, 0.7ns max 0.2ns min, 0.5ns typical, 0.7ns max
Aging (PPM/year) Pullability PECL Supply Current (IDD)[Fout = 212.50MHz] Output Clock Duty Cycle @ VDD-1.3V Output High Voltage Output Low Voltage Clock Rise time (tr) @ 20/80% Clock Fall time (tf) @ 80/20% CMOS Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load] Output Clock Duty Cycle [Measured @ 50% VDD] LVDS Supply Current (IDD) [Fout = 212.50MHz] Output Clock Duty Cycle @ 1.25V Output Differential Voltage (VOD) VDD Magnitude Change (VOD) Output High Voltage Output Low Voltage Offset Voltage [RL = 100] Offset Magnitude Voltage[RL = 100] Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V] Differential Clock Rise Time (tr) [RL=100, CL=10pF] Differential Clock Fall Time (tf) [RL=100, CL=10pF]
ABRACON IS ISO 9001 / QS 9000 CERTIFIED
rev1.1-5/05
30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR WITH VOLTAGE CONTROL
ABVFM SERIES
NAME VCON Tri-state GND Q Q VDD
: PRELIMINARY
5.0 x 7.0 x 1.8mm
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PIN ASSIGNMENTS:
PIN # 1 2 3 4 5 6 DESCRIPTION VCON Tri-state Ground PECL, LVDS, or CMOS Output Complimentary PECL,LVDS, or NC VDD Connection
TRI-STATE PIN OPERATION:
OUTPUT TYPE PECL LVDS & CMOS PIN 2 LOGIC LEVEL* 0 (Default) 1 0 1(Default) OUTPUT STATE Enabled Tri-state Tri-state Enabled
*Connect to VDD from logic level "1", connect to ground for logic level "0".
MARKING:
- TUH - ABFM ZY (Frequency: T=First ""10" digit of frequency, U=First "unit" of frequency, H=First "tenth" of frequency, Ex: 100 for 10.0MHz) (Z: Month, A to L; Y: Year, 5 for 2005
OUTLINE DRAWING:
OPTIONS AND PART IDENTIFICATION (Left blank if standard):
ABFM - Frequency - Temperature - Frequency Stability - Output - Packaging Temperature: D for -10C to +60C E for -20C to +70C F for -30C to +70C N for -30C to +85C L for -40C to +85C Stability options: R for 25 ppm C for 50 ppm Output options: P = PECL L = LVDS C = CMOS
Dimensions: inch (mm)
Packaging option: T for Tape and Reel (1,000pcs/reel)
Availability limited to application specific application frequencies. Please contact factory for available frequencies.
ABRACON IS ISO 9001 / QS 9000 CERTIFIED
rev1.1-5/05
30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com

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