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74VHCT573A Octal D-Type Latch with 3-STATE Outputs
January 1998 Revised April 2005
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
General Description
The VHCT573A is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a Latch Enable input (LE) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Note 1: Outputs in OFF-State.
Features
s High speed: tPD
7.7 ns (typ) at TA 2.0V, VIL
25qC 0.8V
s High Noise Immunity: VIH
s Power Down Protection is provided on all inputs and outputs s Low Noise: VOLP
1.6V (max) 25qC
s Low Power Dissipation:
ICC
4 PA (max) @ TA
s Pin and function compatible with 74HCT573
Ordering Code:
Order Number 74VHCT573AM 74VHCT573ASJ 74VHCT573AMTC 74VHCT573AN Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
(c) 2005 Fairchild Semiconductor Corporation
DS500028
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74VHCT573A
Pin Descriptions
Pin Names D0-D7 LE OE O0-O7 Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Outputs
Truth Table
Inputs OE L L L H
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
Outputs D H L X X On H L O0 Z
LE H H L X
Functional Description
The VHCT573A contains eight D-type latches with 3STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs, a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode, but, this does not interfere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHCT573A
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) (Note 3) (Note 4) Input Diode Current (IIK) Output Diode Current (IOK) (Note 5) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260qC
0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 0.5V to 7.0V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC
Recommended Operating Conditions (Note 6)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) (Note 3) (Note 4) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC 5.0V r 0.5V 0 ns/V a 20 ns/V
Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 4: When outputs are in OFF-State or when VCC Note 5: VOUT GND, V OUT ! VCC (Outputs Active). Note 6: Unused inputs must be held HIGH or LOW. They may not float. OV.
4.5V to 5.5V 0V to 5.5V 0V to VCC 0V to 5.5V
40qC to 85qC
DC Electrical Characteristics
Symbol VIH VIL VOH VOL IOZ IIN ICC ICCT IOFF Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current Maximum ICC/Input Output Leakage Current (Power Down State) VCC (V) 4.5 5.5 4.5 5.5 4.5 4.5 4.5 4.5 5.5 0 5.5 5.5 5.5 0.0 4.40 3.94 0.0 0.1 0.36 4.50 TA Min 2.0 2.0 0.8 0.8 4.40 3.80 0.1 0.44 25qC Typ Max TA
40qC to 85qC
Max 2.0 2.0 0.8 0.8
Min
Units V V V V V V VIN VIN VOUT VIN VIN VIN VOUT VIN
Conditions
VIH VIH
IOH IOL
50 PA 8 mA
50 PA 8 mA
or VIL IOH or VIL IOL VIH or VIL
r0.25 r0.1
4.0 1.35 0.5
r2.5 r1.0
40.0 1.50 5.0
PA PA PA
mA
VCC or GND 5.5V or GND VCC or GND 3.4V VCC or GND 5.5V
Other Inputs
PA
Noise Characteristics
Symbol VOLP (Note 7) VOLV (Note 7) VIHD (Note 7) VILD (Note 7)
Note 7: Parameter guaranteed by design.
Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage
VCC (V) 5.0 5.0 5.0 5.0
TA Typ 1.2
25qC Limits 1.6
Units V V V V CL CL CL CL
Conditions 50 pF 50 pF 50 pF 50 pF
1.2
1.6
2.0 0.8
3
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74VHCT573A
AC Electrical Characteristics
Symbol tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ tOSLH tOSHL CIN COUT CPD Parameter Propagation Delay Time (LE to On) Propagation Delay Time (D to On) 3-STATE Output Enable Time 3-STATE Output Disable Time Output to Output Skew Input Capacitance Output Capacitance Power Dissipation Capacitance
Note 8: Parameter guaranteed by design. tOSLH |tPLH max t PLH min|; tOSHL |tPHL max tPHL min| Note 9: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN ICC/8 (per F/F). The total CPD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) 14 13n.
VCC (V) 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5
TA Min
25qC Typ 7.7 8.5 5.1 5.9 6.3 7.1 8.8 Max 12.3 13.3 8.5 9.5 10.9 11.9 11.2 1.0 4 6 25 10
TA
40qC to 85qC
Max 13.5 14.5 9.5 10.5 12.5 13.5 12.0 1.0 10 1.0 1.0 1.0 1.0 1.0 1.0 1.0
Min
Units ns ns ns ns ns pF pF pF RL RL
Conditions CL CL CL CL 1 k: CL CL 1 k: CL 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 50 pF
(Note 8) VCC VCC Open 5.0V
(Note 9)
AC Operating Requirements
Symbol tW(H) tS tH Parameter Minimum Pulse Width (LE) Minimum Setup Time Minimum Hold Time VCC (V) 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 TA Min 6.5 1.5 3.5 25qC Typ Max TA
40qC to 85qC
Max
Min 8.5 1.5 3.5
Units ns ns ns
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74VHCT573A
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
5
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74VHCT573A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74VHCT573A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74VHCT573A Octal D-Type Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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