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| 74VHC14 Hex Schmitt Inverter June 1993 Revised February 2005 74VHC14 Hex Schmitt Inverter General Description The VHC14 is an advanced high speed CMOS Hex Schmitt Inverter fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the VHC04 but the inputs have hysteresis between the positive-going and negative-going input thresholds, which are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals, thus providing greater noise margin than conventional inverters. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features s High Speed: tPD 5.5 ns (typ) at VCC VNIL 5V 25qC s Low power dissipation: ICC s High noise immunity: VNIH s Low noise: VOLP 2 PA (Max) at TA 28% VCC (Min) s Power down protection is provided on all inputs 0.8V (Max) s Pin and function compatible with 74HC14 Ordering Code: Order Number 74VHC14M (Note 1) 74VHC14MX_NL (Note 2) 74VHC14SJ (Note 1) 74VHC14MTC (Note 1) 74VHC14MTC_NL (Note 3) 74VHC14MTCX_NL (Note 2) 74VHC14N Package Number M14A M14A M14D MTC14 MTC14 MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pb-Free package per JEDEC J-STD-020B. Note 1: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Note 2: "_NL" indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only. Note 3: "_NL" indicates Pb-Free product (per JEDEC J-STD-020B). (c) 2005 Fairchild Semiconductor Corporation DS011617 www.fairchildsemi.com 74VHC14 Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions Pin Names An On Description Inputs Outputs Truth Table A L H O H L www.fairchildsemi.com 2 74VHC14 Absolute Maximum Ratings(Note 4) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) Lead Temperature (TL) Soldering (10 seconds) 260qC 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC Recommended Operating Conditions (Note 5) Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) 2.0V to 5.5V 0V to 5.5V 0V to VCC 40qC to 85qC Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The data book specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 5: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VP Parameter Positive Threshold Voltage VCC 3.0 4.5 5.5 VN Negative Threshold Voltage 3.0 4.5 5.5 VH Hysteresis Voltage 3.0 4.5 5.5 VOH HIGH Level Output Voltage 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 0-5.5 5.5 0.90 1.35 1.65 0.30 0.40 0.50 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 2.0 3.0 4.5 1.20 1.40 1.60 TA Min 25qC Typ Max 2.20 3.15 3.85 0.90 1.35 1.65 0.30 0.40 0.50 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 V IOL IOL VIN VIN 4 mA 8 mA V V VIN VIH IOL 50 PA IOH IOH V 1.20 1.40 1.60 VIN VIL IOH V V TA 40qC to 85qC Max 2.20 3.15 3.85 Units Conditions Min V 50 PA 4 mA 8 mA r0.1 2.0 r1.0 20.0 PA PA 5.5V or GND VCC or GND Noise Characteristics Symbol VOLP (Note 6) VOLV (Note 6) VIHD (Note 6) VILD (Note 6) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC 5.0 5.0 5.0 5.0 TA Typ 0.4 25qC Limits 0.8 V V V V CL CL CL CL 50 pF 50 pF 50 pF 50 pF Units Conditions 0.4 0.8 3.5 1.5 Note 6: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC14 AC Electrical Characteristics Symbol tPLH tPHL Parameter Propagation Delay Time 5.0 r 0.5 CIN CPD Input Capacitance Power Dissipation Capacitance VCC 3.3 r 0.3 TA Min 25qC Typ 8.3 10.8 5.5 7.0 4 21 Max 12.8 16.3 8.6 10.6 10 TA 40qC to 85qC Max 15.0 18.5 10.0 12.0 10 1.0 1.0 1.0 1.0 Min Units ns ns pF pF CL CL CL CL Conditions 15 pF 50 pF 15 pF 50 pF Open VCC (Note 7) Note 7: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr) C PD * VCC * fIN ICC/6 (per Gate) www.fairchildsemi.com 4 74VHC14 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74VHC14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74VHC14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 74VHC14 Hex Schmitt Inverter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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