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CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
The CX74001 Application-Specific Integrated Circuit (ASIC) is a triple-mode, dualband receiver (Rx) intended for use in Code Division Multiple Access (CDMA) portable phones in both cellular and Personal Communications System (PCS) bands, as well as Advanced Mobile Phone System (AMPS) mode. The device is a highly integrated super-heterodyne receiver. It incorporates all the components required to implement the receiver chain, from the low-noise amplifier (LNA) to the In-Phase and Quadrature (I/Q) demodulator stages, except for the external Surface Acoustic Wave (SAW) filters and matching components. There are two internal Low Noise Amplifiers (LNAs). The Cellular LNA has three-step gain stages, and the PCS LNA gain has a bypass feature. After RF signal amplification and filtering, the received signal is mixed down from RF to the Intermediate Frequency (IF). There are separate mixers for AMPS, CDMA, and PCS bands. The CDMA cellular and PCS mixers have balanced outputs for the IF SAW filters, while the AMPS differential output can be combined externally to mate to a single-ended SAW filter. After IF filtering, the IF signal is amplified by a Variable Gain Amplifier (VGA) and fed to an I/Q demodulator resulting in baseband I/Q signals at the output. The VGA has a minimum dynamic range of 90 dB with a control voltage range from 0.5 to 2.5 Volts, and it is common to all modes. There are two VHF oscillators which operates with external tank circuits to provide Local Oscillator (LO) frequencies for the I/Q demodulator in the cellular and PCS bands. The noise figure, gain, and third order Input Intercept Point (IIP3) of each stage in the receiver chip are optimized to meet the system requirements for AMPS and CDMA modes as per TIA/EIA-98-C. Employing BiCMOS technology, the ASIC is designed for low cost, high performance, and a high level of integration. The device package and pinout are shown in Figure 1. A system block diagram of the CX74001 is shown in Figure 2.
Distinguishing Features
* Supports single and dual-band, and tri-mode handsets * Battery cell operation (2.7 V < Vcc < 3.3 V) * Dual Low Noise Amplifiers (800 MHz / 1900 MHz) * PCS LNA With Bypass Feature * Three-Step Cellular LNA Gain * I/Q Interface * Dual 200-600 MHz VHF Oscillators * VCO On/Off control For Standby Current Optimization * CDMA Single IF Feature * 48-pin, 7 x 7 mm RF Land Grid Array (RFLGATM) package with down-set paddle.
Applications
* * * * * * * * Cellular and PCS band phones CDMA and AMPS modes in the cellular band AMPS CDMA-US CDMA-Japan CDMA mode in the PCS band PCS-US PCS-Korea
PCS_LNA_BIAS_RES CELL_LNA_ OUT NC PCS_LNA_OUT CELL_LNA_BIAS_RES RF_BIAS_RES CELL_MIX_IN PCS_MIX_IN PCSMIX_BYPASS CELL_LO PCS_LO 48 47 46 45 44 43 42 41 40 39
LNA_CTRL1 PCS_LNAIN LNA_CTRL0 CELL_LNA_IN VCC_RF_BIAS CELL_LNA_EMIT CELL/PCS FM/CDMA VCO_VCC VCO_ON CELL_TANKCELL_TANK+ PCS_TANK1 2 3 4 5 6 7 8 9 10 11 12 13
38
37 36 35 34 33 32 31 30 29 28 27 26 25
VCC_MIX PCS_MIXER_OUT+ PCS_MIXER_OUTAMPS_MIX_OUT+ AMPS_MIX_OUTCDMA_MIX_OUT+ CDMA_MIX_OUTPCS_VGA_IN+ PCS_VGA_INAMPS_VGA_IN CDMA_VGA_IN+ CDMA_VGA_INVCC_IF
14 15 16 PLL- 17 SIF 18 I- 19 I+ 20 Q+ 21 Q- 22 SLEEP 23 VGA_CONTROL 24 PCS_TANK+ LOD PLL+
CNXT061
Figure 1. CX74001 Rx ASIC Pin-Out (Top View)
Data Sheet
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Doc. No. 101134A March 5, 2002
CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
AMPS IF SAW CELL_LO RF SAW (CELL) VCO_ON
CDMA IF SAW
PLL
LNA_CTRL1 LNA_CTRL0
BYPASS
CELL_LNA_IN
LNA1 LNA2
I+ I-
FM CELL/PCS SLEEP PCS LNA IN
BIAS CONTROL
/2
Q+ Q-
BYPASS
LOD SIF BIAS RESISTORS (3)
3
PCS_LO
RF SAW (PCS)
PCS IF SAW
Figure 2. CX74001 Rx ASIC Block Diagram
Technical Description
Low Noise Amplifiers (LNAs) _________________________ The cellular band LNA is designed with a low noise figure and high linearity to achieve receiver sensitivity and single-tone requirements. The cellular LNA is a three-step gain LNA designed to meet the inter-modulation distortion specifications in CDMA per TIA/EIA 98-C. The PCS band LNA is also designed to provide a low noise figure and high linearity to achieve receiver sensitivity and single-tone requirements. At high signal strength, it is preferable to bypass the LNA completely, and the PCS LNA supports this feature. Mixers ____________________________________________ The CX74001 Rx ASIC has three independent mixers, one for the PCS band and two for the cellular band (AMPS and CDMA). The mixers are designed to operate with LO powers of -10 dBm, typical. The cellular and PCS band mixers have a high gain and IIP3, and a low noise figure that allow them to meet the system
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requirements with margin. The cellular CDMA and PCS mixers have balanced output to drive the IF SAW filters. The differential outputs of the AMPS mixer are combined externally to mate to a single-ended input IF SAW filter. Variable Gain Amplifier (VGA) _________________________ The high dynamic range required by CDMA handsets is achieved by the VGA, which is common to all modes. It has three different inputs and the appropriate signal path is switched inside the chip. The VGA has a dynamic range of 90 dB with a control voltage of 0.5 to 2.5 volts. It has a low noise figure at maximum gain, which allows it to meet the system noise figure requirements. The balanced output is common for all the modes and is fed directly to the I/Q Demodulator. I/Q Demodulator_____________________________________ The VGA stage is internally AC coupled to the I/Q demodulator. The LO signals are derived from one of the on-chip VCOs, then fed to a divider block that divides the VCO frequency by two. The differential I and Q outputs are designed specifically with a low DC output offset and a low phase and amplitude imbalance when cascaded with the baseband processor.
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VGA_CONTROL
Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
Voltage Controlled Oscillators (VCOs)__________________ The active cores of the two VCOs are present on the CX74001, requiring only differential external LC tanks and a PLL synthesizer. The VCO core current is automatically adjusted to give a constant VCO output swing, regardless of the external tank Q. Mode Control ______________________________________ The operation of the chip is controlled by signals CELL/PCS, FM, and SLEEP. The Single IF (SIF) is added to use a common IF frequency for CDMA mode in cellular and PCS band. This allows the use of one IF SAW filter for the PCS and CDMA modes to reduce system implementation cost. The logic blocks are powered off of the Vcc_IF, so it must be present to obtain chip functionality.
provided in Table 4. Tables 5, 6, 7, and 8 provide logic and mode control information for the CX74001. Figures 3 through 46 provide typical performance characteristics. A schematic diagram of the CX74001 is provided in Figure 47 and the package dimensions of the 48-pin RFLGA are shown in Figure 48.
ESD Sensitivity
The CX74001 is a JEDEC Class 1 device. The following extreme Electrostatic Discharge (ESD) precautions are required according to the Human Body Model (HBM): * * * * Protective outer garments. Handle device in ESD safeguarded work area. Transport device in ESD shielded containers. Monitor and test all ESD protection equipment.
Electrical and Mechanical Specifications.
Signal pin assignments and functional pin descriptions are described in Table 1. The absolute maximum ratings of the CX74001 are provided in Table 2. The recommended operating conditions are specified in Table 3. Electrical specifications are
The HBM ESD withstand threshold value, with respect to ground, is 1.5 kV. The HBM ESD withstand threshold value, with respect to VDD (the positive power supply terminal) is also 1.5 kV.
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CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
Table 1. CX74001 Pin Assignments and Signal Descriptions (1 of 4) Pin #
1
Name
LNA_CTRL1
Description
Digital signal used in conjunction with pin 3 to control LNA gain step. DO NOT ALLOW TO FLOAT OR LEAVE UNCONNECTED
Equivalent Circuit
Vcc
2
PCS_LNAIN
PCS LNA input pin. High-Q matching network should be used to minimize noise figure, and a DC blocking capacitor is required.
3
LNA_CTRL0
Digital signal used in conjunction with pin 1 to control LNA gain step. DO NOT ALLOW TO FLOAT OR LEAVE UNCONNECTED
Vcc
4
CELL_LNA_IN
Cellular LNA input pin. High-Q matching network should be used to minimize noise figure, and a DC blocking capacitor is required.
5 6
VCC_RF_BIAS CELL_LNA_EMIT
Supply voltage to the RF bias (needed by all LNA/Mixer blocks) . An RF bypass capacitor should be connected from the pin to ground with minimal trace length. Ground directly to ground with minimum trace length.
7 8 9 10 11 12 13 14 15
CELL/PCS FM/CDMA VCO_VCC VCO_ON CELL_TANK- CELL_TANK+ PCS_TANK- PCS_TANK+ LOD
Digital signal used for band selection: 0 = cellular (800 MHz), 1 = PCS (1900 MHz). Digital signal used in cellular band for mode selection: 0 = AMPS, 1 = CDMA. Voltage supply to the VCO buffers. A bypass capacitor should be placed close to the device from pin 9 to ground with minimal trace length. VCO control signal to turn VCO and PLL buffer ON/OFF during slotted paging modes, thereby increasing standby time. Differential tank cellular band VCO pin. Care should be taken during the layout of the external tank circuit to prevent parasitic oscillations. Differential tank cellular band VCO pin. Care should be taken during the layout of the external tank circuit to prevent parasitic oscillations. Differential tank PCS band VCO pin. Care should be taken during the layout of the external tank circuit to prevent parasitic oscillations. Differential tank PCS band VCO pin. Care should be taken during the layout of the external tank circuit to prevent parasitic oscillations. Linearity On Demand. It provides the bias control for the mixers, thereby reducing the chip current consumption at the expense of input IP3.
- +
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101134A March 5, 2002
Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
Table 1. CX74001 Pin Assignments and Signal Descriptions (2 of 4) Pin #
16 PLL+
Name
Differential buffered VCO output.
Description
- +
Equivalent Circuit
Vcc Vcc
17 18 19 20 21 22 23 24
PLL- SIF I- I+ Q+ Q- SLEEP VGA_CONTROL
Differential buffered VCO output. Digital control signal for SIF selection: 1 = SIF, 0 = Normal. I channel differential output. I channel differential output. Q channel differential output. Q channel differential output. Digital signal used to activate the receiver ASIC: 0 = sleep, 1= enable. Analog gain control of the VGA. Typical 0.5 to 2.5 V to control VGA dynamic range of greater than 90dB.
25 26
VCC_IF CDMA_VGA_IN-
Voltage supply to VGA from I/Q demodulator stages and logic blocks. Supply should be bypassed to prevent signal modulation to the supply line. CDMA differential VGA input
+ -
27
CDMA_VGA_IN+
CDMA differential VGA input
28
AMPS_VGA_IN
AMPS VGA input
29
PCS_VGA_IN-
PCS differential VGA input
+ -
30
PCS_VGA_IN+
PCS differential VGA input
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CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
Table 1. CX74001 Pin Assignments and Signal Descriptions (3 of 4) Pin #
31 32 33 34 35 36 37 38 39 40
Name
CDMA_MIX_OUT- CDMA_MIX_OUT+ AMPS_MIX_OUT- AMPS_MIX_OUT+ PCS_MIXER_OUT- PCS_MIXER_OUT+ VCC_MIX PCS_LO CELL_LO PCSMIX_BYPASS
Description
CDMA differential cellular mixer open collector output. VCC pull up inductor is required, and the output impedance is set by an external matching network. CDMA differential cellular mixer open collector output. VCC pull up inductor is required, and the output impedance is set by an external matching network. AMPS differential mixer open collector output. VCC pull up inductor is required, and the output impedance is set by an external matching network. AMPS differential mixer open collector output. VCC pull up inductor is required, and the output impedance is set by an external matching network. PCS differential mixer open collector output. VCC pull up inductor is required, and the output impedance is set by an external matching network. PCS differential mixer open collector output. VCC pull up inductor is required, and the output impedance is set by an external matching network. Voltage supply for the mixers. RF bypass capacitor should be close to pin with minimal trace length. The local oscillator input for the PCS band mixer. The local oscillator input for the cellular band mixer. Low frequency bypass for the PCS mixer. Typically, a 47 nF is connected from pin to ground.
Equivalent Circuit
+ -
41
PCS_MIX_IN
PCS mixer input. Requires AC coupling capacitor
42
CELL_MIX_IN
Cellular mixer input
43
RF_BIAS_RES
This sets the RF bias current. Typically, a 15 k resistor is connected from the pin to ground.
44
CELL_LNA_BIAS_RES
This sets the cellular LNA bias current. Typically, 27 k is connected to ground.
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101134A March 5, 2002
Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
Table 1. CX74001 Pin Assignments and Signal Descriptions (4 of 4) Pin #
45
Name
PCS_LNA_OUT
Description
PCS LNA open collector output. VCC inductor pull up and external matching network are required.
Equivalent Circuit
46 47
NC CELL_LNA_OUT
No Connection. Cellular LNA open collector output. VCC inductor pull up and external matching network are required.
48
PCS_LNA_BIAS_RES
This set the PCS LNA bias current. Typically, a 220 resistor is connected from the pin to ground.
Table 2. Absolute Maximum Ratings Parameter
Supply voltage (VCC) Input voltage range LNA input power Power dissipation Ambient operating temperature Storage temperature -30 -40
Minimum
-0.3 -0.3
Maximum
+5.5 VCC +5 600 +80 +125
Units
V V dBm mW C C
Table 3. Recommended Operating Conditions Parameter
Supply voltage (VCC) Operating temperature Impedance of logic inputs VIL Logic Low Input Voltage VIH Logic High Input Voltage 0.0 VCC - 0.5
Minimum
2.7 -30
Typical
3.0 +25 50
Maximum
3.3 +80 0.5 VCC
Units
V C k V V
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CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
Table 4. CX74001 Rx ASIC Electrical Specifications (1 of 3)
(TA = 25 C, VCC = 3.0 V)
Parameter
High Gain Medium Gain Low Gain Noise Figure @ High Gain Noise Figure @ Medium Gain Noise Figure @ Low Gain Input IP3 @ High Gain Input IP3 @ Medium Gain Input IP3 @ Low Gain Reverse isolation Input return loss (869-894 MHz) Output return loss (869-894 MHz) Total supply current (adjustable)
Symbol
Test Condition
Minimum
15.5 6 -3
Typical
16 6.4 -5 1.6 2.8 5
Maximum
16.5 7 -6 1.8 4 6.4
Units
dB dB dB dB dB dB dBm dBm dBm dB dB dB
800 MHz LNA CDMA
5 10 20 18 -10 -10 800 MHz LNA AMPS
6 15 22 20 -15 -12 8 8.5 16 1.6
mA dB dB dBm dB dB dB
Gain @ 881 MHz Noise Figure Input IP3 Reverse Isolation Input return loss Output return loss Total supply current 1900 MHz LNA Gain 1 (High) Gain 2 (LNA Bypass) Noise Figure 1 (High) Noise Figure 2 (LNA Bypass) Input IP3 1 (High Gain) Input IP3 (LNA Bypass) Reverse Isolation Input return loss (1930-1990 MHz) Output return loss (1930-1990 MHz) Total supply current (Adjustable)
15 -2 19 -10 -10
15.5 1.4 0 20 -15 -15 4.5
5 16 -3 2 5
mA dB dB dB dB dBm dBm dB dB dB
15 -5
15.5 -4 1.8 4
2 20 19 -8 -10
3 21 20 -12 -12 7.5 10
mA
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Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
Table 4. CX74001 Rx ASIC Electrical Specifications (2 of 3)
(TA = 25 C, VCC = 3.0 V)
Parameter
Conversion Gain (Power): CDMA Mode AMPS Mode Single-Sideband Noise Figure: CDMA Mode AMPS Mode P1dB @ Input: CDMA Mode AMPS Mode IP3 @ Input: CDMA Mode AMPS Mode Mixer RF Input Return Loss (869-894 MHz) (RF Port 1) IF output Resistance: CDMA (differential) AMPS (differential) LO Input Power Level LO Input Return Loss IF Frequency Range LO/RF Isolation Total supply current (Mixer and LO Buffer) CDMA AMPS
Symbol
Test Condition
Minimum
Typical
Maximum
Units
800 MHz Mixer 10 11 10.5 11.5 8.1 8.2 -9.5 -14 6 5 -10 -8 -13 7.5 6 -14 2000 1700 -10 -10 50 18 20 18 12 1900 MHz Mixer (1930-1990 MHz) Conversion Gain (Power) Single-Sideband Noise Figure P1dB @ Input IP3 @ Input RF Input Return Loss (1930-1990 MHz) LO Input Power Level LO Input Return Loss (1600-2300 MHz) IF output resistance (differential) IF Frequency Range Total Supply Current (Mixer and LO Buffer) 50 18 -10 -10 -10 -12 10 11 8 -10 6 -15 -5 -11 1000 300 20 0 7 11.5 9.5 dB dB dBm dBm dB dBm dB MHz mA 22 16 -5 -12 300 0 11 12 8.6 8.6 dB dB dB dB dBm dBm dBm dBm dB dBm dB MHz dB mA mA
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CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
Table 4. CX74001 Rx ASIC Electrical Specifications (3 of 3)
(TA = 25 C, VCC = 3.0 V)
Parameter
Input Frequency Range (-2 dB) Input impedance: CDMA (differential) AMPS(single-ended) PCS (differential) Cascaded Noise Figure: @ Max Gain @ Min Gain VGA control range Gain: Minimum (AMPS) Minimum (CDMA) Minimum (PCS) Maximum (AMPS) Maximum (CDMA) Maximum (PCS) Gain Slope Gain variation over Signal Bandwidth: CDMA and PCS (1 kHz-630 kHz) AMPS (100 Hz-15 kHz) Gain variation over temperature and supply Input 1 db compression at minimum gain OIP3 @ greater than 30 dB gain Output (1dB compression) Output Common Mode Voltage Variation Over Supply I-Ib and Q-Qb DC Offset I-Q Gain Mismatch I-Q Phase Mismatch I-Q DC Offset Total supply current (VGA, IQ, dividers) CDMA / PCS AMPS
Symbol
Test Condition
Minimum
50
Typical
Maximum
300
Units
MHz
VGA and IQ Cascaded Performance
1000 1000 1000 5 50 0.5 -35 -43 -47.5 59 51 48 30 -30 -38 -42.5 63 55 52 45 0.2 0.2 2 -10 4 1.25 0.9 2 0.2 2 8 9 12 Oscillator 100 -115 -25 Buffered VCO Output -117 -30 6 100 120 -30 150 300 -40 3 4 8 600 1.8 6 0.3 4 30 10.5 14 600 -8 5.5 7 2.5 -25 -33 -37.5 66 59 56 70 0.55 0.55
dB dB V dB dB dB dB dB dB dB/V dB dB dB dBm dBm Vppd V mV dB degrees mV mA mA MHz dBc/Hz dBc mA MHz mV dB mA
Frequency range Phase Noise (fc = 200 MHz, unloaded Q = 20) @ 100 kHz offset Second harmonic distortion (application dependent) Total Supply Current Frequency range Output Level (peak differential) Output impedance (differential) Reverse isolation Total supply current
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Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
Table 5. Mode Control Select Signal Switching SLEEP
0 1 1 1 Key: 0 = Low, OFF 1 = High, ON X = Do not care Note 1: All blocks except VCO, which is independently controlled by VCO_ON in this state.
CELL/ PCS
X 0 0 1
FM
X 0 1 X
AMPS CHAIN
OFF (Note 1) ON
CELL CDMA CHAIN
OFF (Note 1) ON
PCS CDMA CHAIN
OFF (Note 1)
ON
Table 6. VCO_ON Control (SIF = 0) VCO_ON
1 1 X X Key: 0 = Low, OFF 1 = High, ON X = Do not care
SLEEP
X X 1 1
CELL/ PCS
0 1 0 1
CELLULAR VCO
ON
PCS VCO
ON ON ON
Table 7. SIF Control - Single IF (SLEEP = 1) SIF
0 0 0 1 1 1 Key: 0 = Low, OFF 1 = High, ON X = Do not care
CELL/ PCS
0 0 1 0 0 1
FM AMPS
0 1 X 0 1 X ON ON
VGA INPUT CDMA
ON ON
PCS
VCO1 CELL
ON ON
VCO2 PCS
ON ON ON ON
ON ON
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CX74001 Table 8. Logic Control for LNA Gain Step LNA_CTRL0
0 1 0 1 Key: 0 = Low, OFF 1 = High, ON X = Do not care Note 1: These modes are available but not used to meet the IS-98 Specifications.
Rx ASIC for CDMA, AMPS, and PCS Applications
LNA_CTRL1
0 0 1 1
AMPS
HIGH MEDIUM (Note 1) BYPASS (Note 1) BYPASS (Note 1)
CELL CDMA
HIGH MEDIUM BYPASS BYPASS
PCS CDMA
HIGH BYPASS HIGH BYPASS
18 17 16 15 Gain (dB) 14 13 12 11 10 9 8 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
3 2.5 Noise Figure (dB) 2 1.5 1 0.5 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5
-30 deg C 25 deg C 85 deg C
-30 deg C 25 deg C 85 deg C
Vcc (V)
Figure 3. PCS LNA Gain at 1960 MHz
Figure 4. PCS LNA NF at 1960 MHz
5 4.5 4 3.5 IIP3 (dBm) Gain (dB) 3 2.5 2 1.5 1 0.5 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5 25 deg C 85 deg C -30 deg C
-30 deg C 25 deg C 85 deg C
Figure 5. PCS LNA IIP3 at 1960 MHz
Figure 6. PCS LNA Gain at 1960 MHz(Bypass Mode)
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Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
25 10 9 8 7 6 5 4 3 2 1 0 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 -30 deg C 25 deg C 85 deg C 24 23 22 21 20 19 18 17 16 15 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 Vcc (V) Vcc (V) 25 deg C 85 deg C -30 deg C
Figure 7. PCS LNA NF (Bypass Mode)
Figure 8. PCS LNA IIP3 (Bypass Mode)
20 19 18
2.5
2
Gain (dB)
16 15 14 13 12 11 10 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5 -30 deg C 25 deg C 85 deg C
Noise Figure (dB)
17
1.5 -30 deg C 25 deg C 0.5 85 deg C 0 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
1
Vcc (V)
Figure 9. Cell CDMA LNA GAIN at 881 MHz
Figure 10. Cell CDMA LNA NF at 881 MHz
10 9 8 7
10 9 8 7
IIP3 (dBm)
Gain (dB)
6 5 4 3 2 1 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5 85 deg C -30 deg C 25 deg C
6 5 4 3 2 1 0 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 Vcc (V) -30 deg C 25 deg C 85 deg C
Figure 11. Cell CDMA LNA IIP3 (High Gain) at 881 MHz
Figure 12. Cell CDMA LNA Gain (Mid Gain) at 881 MHz
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CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
4.5 4 3.5
14 12 10 IIP3 (dBm) 8 6 4 2 0
2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
Noise Figure (dB)
3 2.5 2 1.5 1 0.5 0 Vcc (V) 85 deg C -30 deg C 25 deg C
-30 deg C 25 deg C 85 deg C
2.5
2.6
2.7
2.8
2.9 3 Vcc (V)
3.1
3.2
3.3
3.4
3.5
Figure 13. Cell CDMA LNA Noise Figure (Mid Gain) at 881 MHz
Figure 14. Cell CDMA LNA IIP3 (Mid Gain) at 881 MHz
-2
7 6 5
-3
Noise Figure (dB)
-4 Gain (dB)
4 3 2 1 0
-5
-30 deg C 25 deg C 85 deg C
-6
-30 deg C 25 deg C 85 deg C
-7
-8 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 Vcc (V)
2.5
2.6
2.7
2.8
2.9
3 Vcc (V)
3.1
3.2
3.3
3.4
3.5
Figure 15. Cell CDMA LNA Gain (Bypass Mode) at 881 MHz
Figure 16. Cell CDMA LNA Noise Figure (Bypass Mode) at 881 MHz
25 24 23 22 IIP3 (dBm) 21 20 19 18 17 16 15
2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
20 19 18 17
Gain (dB)
16 15 14 13 12 11 10 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 Vcc (V)
-30 deg C 25 deg C 85 deg C
-30 deg C 25 deg C 85 deg C
Vcc (V)
Figure 17 Cell CDMA LNA IIP3 (Bypass Mode) at 881 MHz
Figure 18. AMPS LNA Gain at 881 MHz
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Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
2 1.8 1.6
5 4 3 2 IIP3 (dBm) 1 0 -1 -2 -3 -4
2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5
Noise Figure (dB)
1.4 1.2 1 0.8 0.6 0.4 0.2 0 85 deg C -30 deg C 25 deg C
-30 deg C 25 deg C 85 deg C 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
-5
Vcc (V)
Figure 19. AMPS LNA Noise Figure at 881 MHz
Figure 20. AMPS LNA IIP3 at 881 MHz
14 12 10 8 Gain (dB) 6 4 2 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5 Noise Figure (dB)
12 10 8 6
-30 deg C
4
-30 deg C 25 deg C 85 deg C
25 deg C
2
85 deg C
0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5
Figure 21. PCS Mixer Gain at 1960 MHz
Figure 22. PCS Mixer Noise Figure at 1960 MHz
8 7 6 5
14 12 10 8
IIP3 (dBm)
3 2 1 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2
-30 deg C 25 deg C 85 deg C
Gain (dB)
4
6 4 2 0 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2
-30 deg C 25 deg C 85 deg C
3.3
3.4
3.5
3.3
3.4
3.5
Vcc (V)
Figure 23. PCS Mixer IIP3 at 1960 MHz
Figure 24. CELL CDMA Mixer Gain at 881 MHz
101134A March 5, 2002
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Proprietary Information and Specifications are Subject to Change
15
CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
10 9 8 7 Noise Figure (dB)
IIP3 (dBm)
10 8 6 4 2 0
6 5 4 3 2 1 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5 25 deg C -30 deg C
-30 deg C 25 deg C 85 deg C
-2
85 deg C
-4 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2
3.3
3.4
3.5
Figure 25. Cell CDMA Mixer Noise Figure at 881 MHz
Figure 26. Cell CDMA Mixer IIP3 at 881 MHz
14 12 10 Gain (dB)
NF (dB)
10 9 8 7 6
8 6 4 2 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5
5 4 3
-30 deg C 25 deg C 85 deg C
-30 deg C 25 deg C 85 deg C
2 1 0 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
Vcc (V)
Figure 27. AMPS Mixer Gain at 881 MHz
Figure 28. AMPS Mixer Noise Figure at 881 MHz
7 6 5 4 3 2 1 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5 -30 deg C 25 deg C 85 deg C
Gain (dB)
60 58 56 54
IIP3(dBm)
52 50 48 46 44 42 40 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
-30 deg C 25 deg C 85 deg C
Vcc (V)
Figure 29. AMPS Mixer IIP3 at 881 MHz
Figure 30. PCS VGA+IQ Gain (VCC = 2.5 V) at 210.38 MHz
16
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Proprietary Information and Specifications are Subject to Change
101134A March 5, 2002
Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
-35 -36 -37
Noise Figure (dB)
7 6 5 4 3 -30 deg C 2 25 deg C 1 85 deg C 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5
-38
Gain (dB)
-39 -40 -41 -42 -43 -44 -45 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 -30 deg C 25 deg C 85 deg C
Vcc (V)
Figure 31. PCS VGA+IQ Gain (VCC = 0.5 V) at 210.38 MHz
Figure 32. PCS VGA+I/Q Noise Figure (VCC = 2.5 V) at 210.38 MHz
-40 -41 -42 Noise Figure (dB) -43 -44 -45 -46 -47 -48 -49 -50 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5
Gain (dB)
-30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
-30 deg C 25 deg C 85 deg C
-30 deg C 25 deg C 85 deg C
Vcc (V)
Figure 33. PCS VGA+I/Q IIP3 (VCC = 2.5 V) at 210.38 MHz
Figure 34. Cell CDMA VGA+IQ Gain (VCC = 0.5 V) at 85.38 MHz
60 58 56 54 Gain (dB) 52 50 48 46 44 42 40 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
9 8 7
Noise Figure (dB)
6 5 4 3 2 1 0 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5 -30 deg C 25 deg C 85 deg C
-30 deg C 25 deg C 85 deg C
Vcc (V)
Figure 35. Cell CDMA VGA+IQ Gain (VCC = 2.5 V) at 85.38 MHz
Figure 36. CDMA VGA+I/Q Noise Figure (VCC = 2.5 V) at 85.38 MHz
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Proprietary Information and Specifications are Subject to Change
17
CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
-43 -45 Noise Figure (dB) -47 -49
-20 -22 -24 -26
Gain (dB)
-28 -30 -32 -34 -36 -38 -40
-30 deg C
-51
-30 deg C 25 deg C 85 deg C
2.5 2.6 2.7 2.8 2.9 Vcc (V) 3 3.1 3.2 3.3 3.4 3.5
25 deg C
-53 -55 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5
85 deg C
Figure 37. CDMA VGA+I/Q IIP3 (Vc = 2.5 V) at 85.38 MHz
70 68 66 64
Noise Figure (dB)
Figure 38. AMPS VGA+IQ Gain (Vc = 0.5 V) at 85.38 MHz
10 9 8 7 6 5 4 3 2 1 0
Gain (dB)
62 60 58 56 54 52 50 2.5 2.6 2.7 2.8 2.9 Vcc (V) 3 3.1 3.2 3.3 3.4 3.5 85 deg C -30 deg C 25 deg C
-30 deg C 25 deg C 85 deg C
2.5
2.6
2.7
2.8
2.9
3 Vcc (V)
3.1
3.2
3.3
3.4
3.5
Figure 39. AMPS VGA+IQ Gain (Vc = 2.5 V) at 85.38 MHz
-48 -50 -52
Figure 40. AMPS VGA+I/Q Noise Figure (Vc = 2.5 V) at 85.38 MHz
70 60 50
Current (mA)
IIP3 (dBm)
40 30 20 10 -30 deg C 25 deg C 85 deg C 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
-54 -56 -58 -60 2.5 2.6 2.7 2.8 2.9 3 Vcc (V) 3.1 3.2 3.3 3.4 3.5
-30 deg C 25 deg C 85 deg C
0
Vcc (V)
Figure 41. AMPS VGA+I/Q IIP3 (Vc = 2.5 V) at 85.38 MHz
Figure 42. Supply Current in PCS Mode (LNA Bypassed)
18
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Proprietary Information and Specifications are Subject to Change
101134A March 5, 2002
Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
70 60 50 40 30 20 10 0 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5
70 60 50
Current (mA)
Current (mA)
40 30 20 10 0 2.5 2.7 2.9 Vcc (V) 3.1 3.3 3.5 -30 deg C 25 deg C 85 deg C
-30 deg C 25 deg C 85 deg C
Vcc (V)
Figure 43. Supply Current in PCS Mode ( LNA ON)
70 60 50
Figure 44. Supply Current in Cell CDMA Mode (LNA ON)
70 60 50
Current (mA)
40 30 20 10 0 2.5 2.7 2.9 Vcc (V) 3.1 3.3 3.5 -30 deg C 25 deg C 85 deg C
Current (mA)
40 30 -30 deg C 20 10 0 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 25 deg C 85 deg C
Vcc (V)
Figure 45. Supply Current in CELL CDMA Mode (LNA Bypassed)
Figure 46. Supply Current in AMPS Mode
101134A March 5, 2002
Skyworks
Proprietary Information and Specifications are Subject to Change
19
CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
8.2 nH VCC_1900_LNA 1 nF 10 8.2 pF FROM PCS RF SAW FILTER OUTPUT 10 nH 33 pF FROM CDMA RF SAW FILTER OUTPUT
TO PCS RF SAW FILTER INPUT
50 ohms
50 ohms
800LO
4.7pF 6.8 nH VCC_LNA 1 nF 10 8.2 pF 8.2 pF 3.3 pF 50 ohms
1900LO
1.5 nH VCC_MIX 4.7 F 33 pF 18 nH
TO CDMA RF SAW FILTER INPUT
50 ohms
1K LNA_CTRL 10 nF
DNI DNI
1 nF
33 pF
8.2 pF PCS LNA INPUT DNI
1.2 nH 18 nH
TO PCS IF SAW FILTER INPUT
VCC_MIX DNI DNI 1 nF 33 PF
1K LNA_CTRL 8.2 pF 8.2 pF
15 K
8.2 pF 27 K 390 nH
33 pF CELL LNA INPUT 10 nH
15 pF 220 DNI 33 pF Vcc CELL_LNA_BIAS_RES PCS_LNA_BIAS_RES 750 nH DNI 0 8.2pF CELL_LO PCS_LO 4.7 nF 4.7 nF 33 pF
VCC_MIX
PCSMIX_BYPASS
PCS_LNA_OUT
CELL_MIX_IN
1000 pF
CELL_LNA_OUT
47 nF
RFBIAS_SET
PCS_MIX_IN
TO IF AMPS SAW FILTER INPUT VCC_MIX
Vcc CELL/PCS FM/PCS VCO_ON 50 ohms
47 nH
NC
48
47
46
45
44
43
42
41
40
39
38
2.2 K 37 36 35 34 33 VCC_MIX PCS_MIXER_OUT+ PCS_MIXER_OUT- AMPS_MIXOUT+ AMPS_MIXOUT- CDMA_MIXOUT+ CDMA_MIXOUT- PCS_VGA_IN+ PCS_VGA_IN- AMPS_VGA_IN CDMA_VGA_IN+ CDMA_VGA_IN- VCC_IF 1 nF 1 nF 4.7 nF 12 pF 4.7 nF 4.7 nF 2.2 K DNI 47 nH DNI
4.7 nF
33 pF
LNA_CTRL1 PCS_LNAIN LNA_CTRL0 CELL_LNA_IN VCC_RF_BIAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TO CDMA IF SAW FILTER INPUT
VCC_TANK 1 F 5.1 1 nF 220 pF
CELL_LNA_EMIT CELL/PCS FM/CDMA VCO_VCC VCO_ON 0 5.1 5.1 CELL_TANK- CELL_TANK+ PCS_TANK- 82 nH 1 nF 1 nF 82 nH 0
CX74001
32 31 30 29 28 27 26 25
4.7 nF
33 pF
VGA_PCS_IN+ VGA_PCS_IN- VGA_AMPS_IN VGA_CDMA_IN+ VGA_CDMA_IN-
LOD
PLL+
I+
Q+
PCS_TANK+
SLEEP
PLL-
SIF
Q-
I-
18 pF
5.1 K
5.1 K
18 pF
VGA_CONTROL
A1 Anode 1
A2 Anode 2
VCC_IF 4.7 nF 10 VGA_CTRL 0.1 F 1000 pF
VCC_TANK 2.2 F 5.1 1 nF 220 pF
Cathode 1
Cathode 2
TUNE 2K
SLEEP 0 0
C 5.1 5.1
RXQ-
0 RXQ+ 12 nH 0 0 RXI+ 0 RXI-
12 nH
1 nF
1 nF
22 pF
5.1 K
5.1 K
22 pF STM
A2 Anode 2
A1 Anode 1
100 pF PLL+ 100 pF LOD 5.1 K PLL+
Cathode 2
NOTES: 1. COMPONENT VALUES MAY CHANGE 2. DNI = DO NOT INSTALL
2K
C
Cathode 1
TUNE
Figure 47. CX74001 Schematic Diagram
20
Skyworks
Proprietary Information and Specifications are Subject to Change
101134A March 5, 2002
Rx ASIC for CDMA, AMPS, and PCS Applications
CX74001
B E
F
PIN #1 MARK PIN #1
B
DIM. A B C D E MILLIMETERS MIN. MAX. 1.30 7.10 0.35 INCHES MIN. 0.043 0.272 0.010 MAX. 0.051 0.280 0.014
C
TOP VIEW BOTTOM VIEW
D
1.10 6.90 0.25
0.50 REF 0.31 0.41
0.020 REF 0.012 0.016
A
SIDE VIEW
F
R 2.225 REF
R 0.089 REF
CNXT017
Figure 48. Package Dimensions - 48-pin RFLGA Package
101134A March 5, 2002
Skyworks
Proprietary Information and Specifications are Subject to Change
21
CX74001
Rx ASIC for CDMA, AMPS, and PCS Applications
Ordering Information
Model Name
Dual-band, tri-mode Rx ASIC
Manufacturing Part Number
CX74001-12
Product Revision
(c) 2002, Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. ("Skyworks") products. These materials are provided by Skyworks as a service to its customers and may be used for informational purposes only. Skyworks assumes no responsibility for errors or omissions in these materials. Skyworks may make changes to its products, specifications and product descriptions at any time, without notice. Skyworks makes no commitment to update the information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from future changes to its products and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as may be provided in Skyworks' Terms and Conditions of Sale for such products, Skyworks assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF SKYWORKSTM PRODUCTS INCLUDING WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. SKYWORKS FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THESE MATERIALS. SkyworksTM products are not intended for use in medical, lifesaving or life-sustaining applications. Skyworks' customers using or selling SkyworksTM products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale. RFLGA is a trademark of Conexant Systems, Inc. The following are trademarks of Skyworks Solutions, Inc.: SkyworksTM, the Skyworks symbol, and "Breakthrough Simplicity"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. Additional information, posted at www.skyworksinc.com, is incorporated by reference.
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Skyworks
Proprietary Information and Specifications are Subject to Change
101134A March 5, 2002
General Information: Skyworks Solutions, Inc. 4311 Jamboree Rd. Newport Beach, CA 92660-3007 www.skyworksinc.com

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