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| W942516CH 4M x 4 BANKS x 16 BIT DDR SDRAM Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 KEY PARAMETERS ................................................................................................................... 4 PIN CONFIGURATION ............................................................................................................... 5 PIN DESCRIPTION..................................................................................................................... 6 BLOCK DIAGRAM ...................................................................................................................... 7 ELECRICAL CHARACTERISTICS ............................................................................................. 8 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Absolute Maximum Ratings ................................................................................................. 8 Recommended DC Operating Conditions............................................................................ 8 Capacitance ......................................................................................................................... 9 Leakage and Output Buffer Characteristics ......................................................................... 9 DC Characteristics ............................................................................................................. 10 AC Characteristics and Operating Condition ..................................................................... 11 AC Test Conditions ............................................................................................................ 13 Simplified Truth Table ........................................................................................................ 15 Function Truth Table .......................................................................................................... 16 Function Truth Table for CKE ............................................................................................ 19 Simplified Stated Diagram.................................................................................................. 20 Power Up Sequence .......................................................................................................... 21 Command Function............................................................................................................ 21 Read Operation.................................................................................................................. 24 Write Operation .................................................................................................................. 24 Precharge........................................................................................................................... 24 Burst Termination............................................................................................................... 25 Refresh Operation.............................................................................................................. 25 Power Down Mode............................................................................................................. 25 Mode Register Operation ................................................................................................... 25 Command Input Timing...................................................................................................... 29 Timing of the CLK Signals.................................................................................................. 29 8. OPERATION MODE ................................................................................................................. 15 8.1 8.2 8.3 8.4 9. FUNCTIONAL DESCRIPTION.................................................................................................. 21 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10. TIMING WAVEFORMS ............................................................................................................. 29 10.1 10.2 -1- Publication Release Date: May 20, 2003 Revision A2 W942516CH 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.19 10.20 10.21 10.22 10.23 10.24 10.25 10.26 Read Timing (Burst Length = 4) ......................................................................................... 30 Write Timing (Burst Length = 4) ......................................................................................... 31 DM, Data Mask (W942508CH /W942504CH).................................................................... 32 DM, Data Mask (W942516CH) .......................................................................................... 32 Mode Register Set (MRS) Timing ...................................................................................... 33 Extend Mode Register Set (EMRS) Timing........................................................................ 34 Auto Precharge Timing (Read Cycle, CL = 2).................................................................... 35 Auto Precharge Timing (Write Cycle)................................................................................. 37 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ............................................................... 38 Burst Read Stop (BL = 8) ................................................................................................... 38 Read Interrupted by Write & BST (BL = 8)......................................................................... 39 Read Interrupted by Precharge (BL = 8) ............................................................................ 39 Write Interrupted by Write (BL = 2, 4, 8) ............................................................................ 40 Write Interrupted by Read (CL = 2, BL = 8) ....................................................................... 40 Write Interrupted by Read (CL = 2.5, BL = 4) .................................................................... 41 Write Interrupted by Precharge (BL = 8) ............................................................................ 41 2 Bank Interleave Read Operation (CL = 2, BL = 2) .......................................................... 42 2 Bank Interleave Read Operation (CL = 2, BL = 4) .......................................................... 42 4 Bank Interleave Read Operation (CL = 2, BL = 2) .......................................................... 43 4 Bank Interleave Read Operation (CL = 2, BL = 4) .......................................................... 43 Auto Refresh Cycle ............................................................................................................ 44 Active Power Down Mode Entry and Exit Timing............................................................... 44 Precharged Power Down Mode Entry and Exit Timing ...................................................... 44 Self Refresh Entry and Exit Timing .................................................................................... 45 11. 12. PACKAGE DIMENSION ........................................................................................................... 46 REVISION HISTORY ................................................................................................................ 47 -2- W942516CH 1. GENERAL DESCRIPTION W942516CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words x 4 banks x 16 bits. Using pipelined architecture and 0.13 m process technology, W942516CH delivers a data bandwidth of up to 400M words per second (-5). To fully comply with the personal computer industrial standard, W942516CH is sorted into four speed grades: -5, -6, -7, -75 The -5 is compliant to the 200 MHz/CL2.5 & CL3 specification, The -6 is compliant to the 166 MHz/CL2.5 specification, the -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -75 is compliant to the DDR266/CL2.5 specification. All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W942516CH is ideal for main memory in high performance applications. 2. FEATURES * * * * * * * * * * * * * * * * 2.5V 0.2V Power Supply for DDR266 2.5V 0.2V Power Supply for DDR333 2.6V 0.1V Power Supply for DDR400 Up to 200 MHz Clock Frequency Double Data Rate architecture; two data transfers per clock cycle Differential clock inputs (CLK and CLK ) DQS is edge-aligned with data for Read; center-aligned with data for Write CAS Latency: 2, 2.5 and 3 Burst Length: 2, 4 and 8 Auto Refresh and Self Refresh Precharged Power Down and Active Power Down Write Data Mask Write Latency = 1 8K Refresh Cycles / 64 mS Interface: SSTL-2 Packaged in TSOP II 66-pin, 400 x 875 mil, 0.65 mm pin pitch -3- Publication Release Date: May 20, 2003 Revision A2 W942516CH 3. KEY PARAMETERS SYMBOL tCK tRAS tRC IDD1 IDD4 IDD6 DESCRIPTION Clock Cycle Time CL = 2 CL = 2.5 Active to Precharge Command Period Active to Ref/Active Command Period Operation Current (Single bank) Burst Operation Current Self-Refresh Current MIN./MAX. Min. Min. Min. Min. Max. Max. Max. -7 7.5 nS 7 nS 45 nS 65 nS 120 mA 165 mA 3 mA -75 8 nS 7.5 nS 45 nS 65 nS 120 mA 155 mA 3 mA SYMBOL tCK tRAS tRC IDD1 IDD4 IDD6 DESCRIPTION Clock Cycle Time CL = 2.5 CL = 3 MIN./MAX. Min. Min. Min. Min. Max. Max. Max. -5 5 nS 5 nS 40 nS 55 nS 120 mA 165 mA 3 mA -6 6 nS 6 nS 42 nS 60 nS 120 mA 165 mA 3 mA Active to Precharge Command Period Active to Ref/Active Command Period Operation Current (Single bank) Burst Operation Current Self-Refresh Current -4- W942516CH 4. PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC1 VDDQ LDQS NC1 VDD NC1 LDM WE CAS RAS CS NC1 BS0 BS1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC1 VSSQ UDQS NC1 VREF VSS UDM CLK CLK CKE NC1 A12 A11 A9 A8 A7 A6 A5 A4 VSS -5- Publication Release Date: May 20, 2003 Revision A2 W942516CH 5. PIN DESCRIPTION PIN NUMBER 28 - 32, 35 - 42 26, 27 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 16,51 PIN NAME A0 - A12 FUNCTION Address DESCRIPTION Multiplexed pins for row and column address. Row address: A0 - A12. Column address: A0 - A8. (A10 is used for Auto Precharge) BS0, BS1 DQ0 - DQ15 LDQS, UDQS Bank Select Data Input/ Output Select bank to activate during row address latch time, or bank to read/write during column address latch time. The DQ0 - DQ7 input and output data are synchronized with both edges of DQS. DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command inputs (along with CS ) define the command being entered. When DM is asserted "high" in burst write, the input data is masked. DM is synchronized with both edges of DQS. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK . CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for logic circuit inside DDR SDRAM. Ground for logic circuit inside DDR SDRAM. Data Strobe 24 CS RAS , CAS , WE Chip Select 23, 22, 21 20, 47 Command Inputs Write Mask Differential Clock Inputs LDM, UDM CLK, CLK 45, 46 44 49 1, 18, 33 34, 48, 66 3, 9, 15, 55, 61 6, 12, 52, 58, 64 14, 17, 19, 25, 43, 50, 53 CKE VREF VDD VSS VDDQ VSSQ NC1 Clock Enable Reference Voltage VREF is reference voltage for inputs. Power (+2.5V) Ground Power (+2.5V) for Separated power from VDD, used for output buffer, to improve noise. I/O Buffer Ground for I/O Buffer No Connection Separated ground from VSS, used for output buffer, to improve noise. No connection -6- W942516CH 6. BLOCK DIAGRAM CLK CLK DLL CLOCK BUFFER CKE CS RAS CAS DECODER CONTROL SIGNAL GENERATOR COMMAND WE COLUMN DECODER COLUMN DECODER ROW DECODER A10 CELL ARRAY BANK #0 ROW DECODER CELL ARRAY BANK #1 A0 A9 A11 A12 BA1 BA0 ADDRESS BUFFER MODE REGISTER SENSE AMPLIFIER SENSE AMPLIFIER PREFETCH REGISTER DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER DQ BUFFER DQ0 DQ15 LDQS UDQS LDM UDM COLUMN DECODER COLUMN DECODER ROW DECODER CELL ARRAY BANK #2 ROW DECODER CELL ARRAY BANK #3 SENSE AMPLIFIER SENSE AMPLIFIER NOTE: The cell array configuration is 8912 * 512 * 16 -7- Publication Release Date: May 20, 2003 Revision A2 W942516CH 7. ELECRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT Input/Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER PD IOUT -0.3 - VDDQ +0.3 -0.3 - 3.6 0 - 70 -55 - 150 260 1 50 V V C C C W mA Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 7.2 Recommended DC Operating Conditions PARAMETER Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input reference Voltage Termination Voltage (System) Input High Voltage (DC) Input Low Voltage (DC) Differential Clock DC Input Voltage Input Differential Voltage. CLK and CLK inputs (DC) Input High Voltage (AC) Input Low Voltage (AC) Input Differential Voltage. CLK and CLK inputs (AC) Differential AC input Cross Point Voltage Differential Clock AC Middle Point (TA = 0 to 70C) SYMBOL VDD VDDQ VREF VTT VIH (DC) VIL (DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC) MIN. 2.3 2.3 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 VREF + 0.31 0.7 VDDQ/2 - 0.2 VDDQ/2 - 0.2 TYP. 2.5 2.5 0.50 x VDDQ VREF - MAX. 2.7 VDD 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 VREF - 0.31 VDDQ + 0.6 VDDQ/2 + 0.2 VDDQ/2 + 0.2 UNIT V V V V V V V V V V V V V NOTES 2 2 2, 3 2, 8 2 2 15 13, 15 2 2 13, 15 12, 15 14, 15 Notes: Undershoot Limit: VIL (min) = -0.9V with a pulse width < 5 nS Overshoot Limit: VIH (max) = VDDQ +0.9V with a pulse width < 5 nS VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state. -8- W942516CH 7.3 Capacitance PARAMETER Input Capacitance (except for CLK pins) Input Capacitance (CLK pins) DQ, DQS, DM Capacitance NC1 Pin Capacitance NC2 Pin Capacitance MIN. 2.0 2.0 4.0 4.0 MAX. 3.0 3.0 5.0 1.5 5.0 DELTA (MAX.) 0.5 0.25 0.5 UNIT pF pF pF pF pF (VDD = VDDQ = 2.5V 0.2V, f = 1 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V) SYMBOL CIN CCLK CI/O CNC1 CNC2 Notes: These parameters are periodically sampled and not 100% tested. The NC2 pins have additional capacitance for adjustment of the adjacent pin capacitance. The NC2 pins have Power and Ground clamp. 7.4 Leakage and Output Buffer Characteristics PARAMETER Input Leakage Current (0V < VIN < VDDQ, All other pins not under test = 0V) Output Leakage Current (Output disabled, 0V < VOUT < VDDQ) Output High Voltage (under AC test load condition) Output Low Voltage (under AC test load condition) Output Minimum Source DC Current Output Minimum Sink DC Current Output Minimum Source DC Current Output Minimum Sink DC Current Half Strength MIN. -2 -5 VTT +0.76 Full Strength -15.2 15.2 -10.4 10.4 MAX. 2 5 VTT -0.76 UNITS A A V V mA mA mA mA 4, 6 4, 6 5 5 NOTES SYMBOL II (L) IO (L) VOH VOL IOH (DC) IOL (DC) IOH (DC) IOL (DC) -9- Publication Release Date: May 20, 2003 Revision A2 W942516CH 7.5 SYM. DC Characteristics PARAMETER MAX. -5 -6 -7 -75 UNIT NOTES IDD0 IDD1 IDD2P IDD2F OPERATING CURRENT: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL = 2.5; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle. PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM IDLE FLOATING STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DQS and DM IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM IDLE QUIET STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=2.5; tCK = tCK min; IOUT = 0mA OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT: tRC = tRFC min SELF REFRESH CURRENT: CKE < 0.2V RANDOM READ CURRENT: 4 Banks Active Read with activate every 20ns, Auto-Precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle tCK = 10ns tRC CK CK 110 110 110 110 7 120 2 120 2 120 2 120 2 7, 9 45 45 45 40 7 IDD2N 45 45 45 40 7 IDD2Q IDD3P IDD3N 40 20 40 20 40 20 35 20 mA 7 70 70 70 65 7 IDD4R IDD4 W 165 165 165 155 7, 9 165 190 3 270 165 190 3 270 165 190 3 270 155 190 3 270 7 7 IDD5 IDD6 IDD7 tRCD COMMAND ADDRESS DQS DQ Qa Qa Qb Qb Qb Qb Qc Qc Qc Qc Qd Qd (IDD7) Qd Qd Qe Qe ACT Bank 0 Row d READ AP Bank 3 Rowc Col c ACT Bank 1 Row e READ AP Bank 0 Rowd Col d ACT Bank 2 Row f READ AP Bank 1 Rowe Col e ACT Bank 3 Row q READ AP Bank 2 Col f ACT Bank 0 Row h RANDOM READ CURRENT Timing - 10 - W942516CH 7.6 AC Characteristics and Operating Condition PARAMETER -7 MIN. 65 75 45 20 15 1 20 15 15 30 7.5 7 MAX. MIN. 65 75 45 20 15 1 20 15 15 30 8 7.5 -75 MAX. UNITS NOTES (Notes: 10, 12) SYMBOL tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK tAC tDQSCK tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREF tMRD Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto Precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto Precharge Write Recovery + Precharge Time CL = 2 CLK Cycle Time CL = 2.5 Data Access Time from CLK, CLK DQS Output Access Time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width 100000 100000 nS tCK 15 15 0.75 0.75 0.5 0.55 0.55 15 15 0.75 0.75 0.5 0.55 0.55 nS 16 -0.75 -0.75 -0.75 -0.75 0.45 0.45 Min. (tCL,tCH) THP -0.75 0.9 0.4 0.5 0.5 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.9 0.9 2.2 -0.75 -0.75 0.5 1 75 10 15 0.45 0.45 Min. CLK Half Period (minimum of actual tCH, tCL) (tCL,tCH) THP DQ Output Data Hold Time from DQS -0.75 DQS Read Preamble Time 0.9 DQS Read Postamble Time 0.4 DQ and DM Setup Time 0.5 DQ and DM Hold Time 0.5 DQ and DM Input Pulse Width (for each input) 1.75 DQS Input High Pulse Width 0.35 DQS Input Low Pulse Width 0.35 DQS Falling Edge to CLK Setup Time 0.2 DQS Falling Edge Hold Time from CLK 0.2 Clock to DQS Write Preamble Set-up Time 0 DQS Write Preamble Time 0.25 DQS Write Postamble Time 0.4 Write Command to First DQS Latching Transition 0.75 UDQS - LDQS Skew (x 16) -0.25 Input Setup Time 0.9 Input Hold Time 0.9 Control & Address Input Pulse Width (for each input) 2.2 -0.75 -0.75 0.5 1 75 10 15 tCK 11 nS 1.1 0.6 1.1 0.6 tCK nS 11 tCK nS tCK 11 11 1.25 0.25 1.25 0.25 Data-out High-impedance Time from CLK, CLK Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Time (8k) Mode Register Set Cycle Time 0.75 0.75 1.5 0.75 0.75 1.5 nS 64 64 tCK ns tCK mS nS - 11 - Publication Release Date: May 20, 2003 Revision A2 W942516CH SYM. tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK tAC tDQSCK tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREF tMRD PARAMETER Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto Precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto Precharge Write Recovery + Precharge Time 2.5 CLK Cycle Time 3 Data Access Time from CLK, CLK DQS Output Access Time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual tCH, tCL) DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition UDQS - LDQS Skew (x 16) Input Setup Time Input Hold Time Control & Address Input Pulse Width (for each input) Data-out High-impedance Time from CLK, CLK Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Time (8k) Mode Register Set Cycle Time -5 MIN. 55 70 40 15 15 1 15 10 15 30 5 5 MAX. MIN. 60 72 42 18 15 1 18 12 15 30 6 6 -6 MAX. UNITS NOTES 70000 100000 nS tCK 10 10 0.7 0.55 0.4 0.55 0.55 12 12 0.7 0.6 0.45 0.55 0.55 nS 16 -0.7 -0.55 0.45 0.45 Min. (tCL,tCH) tHP -0.5 0.9 0.4 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.72 -0.25 0.6 0.6 2.2 -0.7 -0.6 0.45 0.45 Min. (tCL,tCH) tHP -0.55 0.9 0.4 0.45 0.45 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.75 0.75 2.2 tCK 11 nS 1.1 0.6 1.1 0.6 tCK nS 11 tCK nS 0.6 1.25 0.25 11 0.6 1.28 0.25 tCK 11 Max tAC -0.7 0.5 2 75 10 10 0.7 1.5 -0.7 -0.7 0.5 2 75 10 12 0.7 0.7 1.5 nS 64 64 tCK ns tCK mS nS - 12 - W942516CH 7.7 AC Test Conditions PARAMETER Input High Voltage (AC) Input Low Voltage (AC) Input Reference Voltage Termination Voltage Input Signal Peak to Peak Swing Differential Clock Input Reference Voltage Input Difference Voltage. CLK and CLK Inputs (AC) Input Signal Minimum Slew Rate Output Timing Measurement Reference Voltage SYMBOL VIH VIL VREF VTT VSWING VR VID (AC) SLEW VOTR VALUE VREF +0.31 VREF -0.31 0.5 x VDDQ 0.5 x VDDQ 1.0 Vx (AC) 1.5 1.0 0.5 x VDDQ UNIT V V V V V V V V/nS V VDDQ VIH min (AC) VTT V SWING (MAX) VREF VIL max (AC) Measurement point RT= 50 ohms VSS T output T Z = 50 ohms 30pF Output SLEW = (VIH min (AC) - VILmax (AC)) / T A.C. TEST LOAD (A) Notes: (1) (2) (3) (4) (5) (6) (7) (8) (9) Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. All voltages are referenced to VSS, VSSQ. .( 2.6V0.1V for DDR400) Peak to peak AC noise on VREF may not exceed 2% VREF(DC). VOH = 1.95V, VOL = 0.35V VOH = 1.9V, VOL = 0.4V The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. These parameters depend on the output loading. Specified values are obtained with the output open. - 13 - Publication Release Date: May 20, 2003 Revision A2 W942516CH (10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed slope. (11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., TDQSS = 0.75 x tCK, tCK = 7.5 nS, 0.75 x 7.5 nS = 5.625 nS is rounded up to 5.6 nS.) (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK)+VICK( CLK )}/2. (15) Refer to the figure below. CLK VX CLK VICK VSS VID(AC) VICK VX VX VICK VX VICK VX VID(AC) 0 V Differential VISO VISO(min) VSS VISO(max) (16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. - 14 - W942516CH 8. OPERATION MODE The following table shows the operation commands. 8.1 Simplified Truth Table COMMAND DEVICE STATE CKEN-1 CKEN DM (4) SYM. BS0, BS1 A10 A12, A11, A9-A0 CS RAS CAS WE ACT PRE PREA WRIT WRITA READ READA MRS EMRS NOP BST DSL AREF SELF SELEX Bank Active Bank Precharge Precharge All Write Write with Auto Precharge Read Read with Auto Precharge Mode Register Set Extended Mode Regiser Set No Operation Burst Read Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Power Down Dode Entry Power Down Mode Exit Data Write Enable Data Write Disable Idle (3) (3) H H H X X X X X X X X X X X X H L H X X X X X X X X X X X X X X X V V X V V V V L, L H, L X X X X X X V L H L H L H C V X X X X X X V X X V V V V C V X X X X X X L L L L L L L L L L L H L L H L H L H L X X L L L H H H H L L H H X L L X H X H X H X X H H H L L L L L L H H X L L X H X H X H X X H L L L L H H L L H L X H H X X X X X X X X Any Any Active Active (3) H H H H H H H H H H H L (3) Active Active Idle Idle Any (3) (3) Active Any Idle Idle Idle (Self Refresh) Idle/ (5) Active Any (Power Down) Active Active PD H L X X X X PDEX WDE WDD Notes: L H H H X X X L H X X X X X X X X X 1. V = Valid X = Don't Care L = Low level H = High level 2. CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. 4. These are state designated by the BS0, BS1 signals. 5. LDM, UDM (W942516CH) 6. Power Down Mode can not entry in the burst cycle. - 15 - Publication Release Date: May 20, 2003 Revision A2 W942516CH 8.2 Function Truth Table CS H L L Idle L L L L L H L L Row Active L L L L L H L L L Read L L L L L H L L L Write L L L L L RAS CAS X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L WE ADDRESS COMMAND ACTION NOTES (Note 1) CURRENT STATE X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS Nop Nop ILLEGAL ILLEGAL Row activating Nop Refresh or Self refresh Mode register accessing Nop Nop Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop Term burst, new read: Determine AP ILLEGAL ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL Term burst, start read: Determine AP Term burst, start read: Determine AP ILLEGAL Term burst. precharging ILLEGAL ILLEGAL 6, 7 6 3 8 3 6 4 4 3 5 2 2 3 3 - 16 - W942516CH Function Truth Table, continued CURRENT STATE CS RAS CAS WE ADDRESS COMMAND ACTION NOTES H L L Read with Auto Prechange L L L L L L H L L Write with Auto Precharge L L L L L L H L L L Precharging L L L L L H L L Row Activating L L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop-> Idle after tRP Nop-> Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after tRP ILLEGAL ILLEGAL Nop-> Row active after tRCD Nop-> Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 3 3 3 3 3 3 3 3 3 3 3 - 17 - Publication Release Date: May 20, 2003 Revision A2 W942516CH Function Truth Table, continued CURRENT STATE CS RAS CAS WE ADDRESS COMMAND ACTION NOTES Write Recovering H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H H L L X H H H L X H H L L H H L L X H H L L H H L L X H H L H L X H H L X X H L H L H L H L X H L H L H L H L X H L H X X X H L X X X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X X X X X X X X X DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/WRIT ACT/PRE/PREA AREF/SELF/MRS/EMRS Nop->Row active after tWR Nop->Row active after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Enter precharge after tWR Nop->Enter precharge after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Idle after tRC Nop->Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Row after tMRD Nop->Row after tMRD ILLEGAL ILLEGAL ILLEGAL 3 3 3 3 3 3 3 3 Write Recovering with Auto Precharge H L L L L L L L L Refreshing H L L L L L Mode Register Accessing H L L L L DSL NOP BST READ/WRIT ACT/PRE/PREA/ARE F/SELF/MRS/EMRS Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisfy burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don't satisfy tWR Remark: H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data - 18 - W942516CH 8.3 Function Truth Table for CKE CKE n-1 n CURRENT STATE CS X H L L L X X X X X H L L L L X X H L L L L X X RAS CAS X X H L X X X X X X X H L L X X X X H L L X X X WE ADDRESS ACTION NOTES Self Refresh H L L L L L X H H H H L X H L H L L L L L X H L L L L L X H X X H H L X X X X X X H L H L X X X H L H L X X X X X X X X X X X X X X H X X X X X X H X X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self Refresh->Idle after tXSNR Exit Self Refresh->Idle after tXSNR ILLEGAL ILLEGAL Maintain Self Refresh INVALID Exit Power down->Idle after tIS Maintain power down mode Refer to Function Truth Table Enter Power down Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table 2 2 2 2 2 1 Power Down H L L All banks Idle H H H H H H L Row Active H H H H H H L Any State Other Than Listed Above Notes: H 1. Self refresh can enter only from the all banks idle state. 2. Power down can enter only from bank idle or row active state. Remark: H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data - 19 - Publication Release Date: May 20, 2003 Revision A2 W942516CH 8.4 Simplified Stated Diagram SELF REFRESH SREF SREFX IDLE MRS/EMRS MODE REGISTER SET AREF AUTO REFRESH PD PDEX ACT ACTIVE POWERDOWN POWER DOWN PDEX PD ROW ACTIVE BST Read Read Write Write Write Read Read Write A Write A Read A Read A Read A PRE Write A PRE PRE Read A POWER APPLIED POWER ON PRE PRE CHARGE Automatic Sequence Command Sequence - 20 - W942516CH 9. FUNCTIONAL DESCRIPTION 9.1 Power Up Sequence (1) Apply power and attempt to CKE at a low state ( 0.2V), all other inputs may be undefined 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF. Start Clock and maintain stable condition for 200 S (min.). After stable power and clock, apply NOP and take CKE high. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8. (an additional 200 cycles(min) of clock are required for DLL Lock) Issue precharge command for all banks of the device. Issue two or more Auto Refresh commands. Issue MRS-Initialize device operation. (If device operation mode is set at sequence 5, sequence 8 can be skipped.) (2) (3) (4) (5) (6) (7) (8) 9.2 Command Function 1. Bank Activate Command ( RAS = "L", CAS = "H", WE = "H", BS0, BS1 = Bank, A0 to A12 = Row Address) The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row addresses are latched on A0 to A12 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. 2. Bank Precharge Command ( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don't care) The Bank Precharge command percharges the bank designated by BS. The precharged bank is switched from the active state to the idle state. 3. Precharge All Command ( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Don't care, A10 = "H", A0 to A9, A11, A12 = Don't care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 4. Write Command ( RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column Address) Publication Release Date: May 20, 2003 Revision A2 - 21 - W942516CH The write command performs a Write operation to the bank designated by BS. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation. 5. Write with Auto Precharge Command ( RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column Address) The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. 6. Read Command ( RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column Address) The Read command performs a Read operation to the bank designated by BS. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation. 7. Read with Auto Precharge Command ( RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column Address) The Read with Auto precharge command automatically performs the Precharge operation after the Read operation. 1) READA tRAS (min) - (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge command. 2) tRCD(min) READA < tRAS(min) - (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command. 8. Mode Register Set Command ( RAS = "L", CAS = "L", WE = "L", BS0 = "L", BS1 = "L", A0 to A12 = Register Data) The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes. 9. Extended Mode Register Set Command ( RAS = "L", CAS = "L", WE = "L", BS0 = "H", BS1 = "L", A0 to A12 = Register data) - 22 - W942516CH The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL enable/disable, decoded by A0. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes. 10. No-Operation Command ( RAS = "H", CAS = "H", WE = "H") The No-Operation command simply performs no operation (same command as Device Deselect). 11. Burst Read Stop Command ( RAS = "H", CAS = "H", WE = "L") The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation. 12. Device Deselect Command ( CS = "H") The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 13. Auto Refresh Command ( RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = Don't care) The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation must be performed 8192 times within 64ms. The next command can be issued after tREF from the end of the Auto Refresh command. When the Auto Refresh command is used, all banks must be in the idle state. 14. Self Refresh Entry Command ( RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = don't care) The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh operation is automatically performed. Self Refresh mode is exited by taking CKE "high" (the Self Refresh Exit command). During self refresh, DLLl is disable. 15. Self Refresh Exit Command (CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H") This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after tXSNR (tXSRD for Read Command) from the end of this command. - 23 - Publication Release Date: May 20, 2003 Revision A2 W942516CH 16. Data Write Enable /Disable Command (DM = "L/H" or LDM, UDM = "L/H") During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to DQ15. 9.3 Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS latency from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. 9.4 Write Operation Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising &falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto Precharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation. 9.5 Precharge There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state. - 24 - W942516CH 9.6 Burst Termination When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of ( CAS latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted "high": during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination. 9.7 Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 8192 times(rows)within 64ms. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enter issuing the Self Refresh command (CKE asserted "low"). while all banks are in the idle state. The device is in Self Refresh mode for as long as cke held "low". In the case of 8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within 7.8 S before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 S and the last distributed Auto Refresh commands must be performed within 7.8 S before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 S. In Self Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation. 9.8 Power Down Mode Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode. When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking CKE: "high" can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode. 9.9 Mode Register Operation The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and BS0, BS1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register filed to select a - 25 - Publication Release Date: May 20, 2003 Revision A2 W942516CH type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode) The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation. 1. Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4, and 8 words. A2 0 0 0 0 1 A1 0 0 1 1 x A0 0 1 0 1 x Burst Length Reserved 2 words 4 words 8 words Reserved 2. Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words. A3 0 0 Addressing Mode Sequential Interleave - 26 - W942516CH * Address Sequence of Sequential Mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 ACCESS ADDRESS n n+1 n+2 n+3 n+4 n+5 n+6 n+7 8 words (address bits A2, A1 and A0) Not carried from A2 to A3 BURST LENGTH 2 words (address bits is A0) not carried from A0 to A1 4 words (address bit A0, A1) Not carried from A1 to A2 * Addressing Sequence of Interleave Mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. 9.9.1.1 Address Sequence for Interleave Mode DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 ACCESS ADDRESS A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 8 words 4 words BURST LENGTH 2 words - 27 - Publication Release Date: May 20, 2003 Revision A2 W942516CH 3. CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved 2.5 Reserved 4. DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is "1", DLL is reset. 5. Mode Register /Extended Mode register change bits (BS0, BS1) These bits are used to select MRS/EMRS. BS1 0 0 1 BS0 0 1 x A12-A0 Regular MRS Cycle Extended MRS Cycle Reserved 6. Extended Mode Register field 1) DLL Switch field (A0) This bit is used to select DLL enable or disable A0 0 1 DLL Enable Disable 2) Output Driver Size Control field (A1) This bit is used to select Output Driver Size, both Full strength and Half strength are based on JEDEC standard. A1 0 1 Output Driver Full Strength Half Strength 7. Reserved field * Test mode entry bit (A7) This bit is used to enter Test mode and must be set to "0" for normal operation. * Reserved bits (A9, A10, A11, A12) These bits are reserved for future operations. They must be set to "0" for normal operation. - 28 - W942516CH 10. TIMING WAVEFORMS 10.1 Command Input Timing tCK tCK CLK CLK tIS CS tIH tCH tCL tIS RAS tIH tIS CAS tIH tIS WE tIH tIS A0~A12 BS0, 1 tIH Refer to the Command Truth Table 10.2 Timing of the CLK Signals CLK CLK tCK CLK CLK VX VX VX VIH VIL tCH tCL VIH VIH(AC) VIL(AC) VIL tT tT - 29 - Publication Release Date: May 20, 2003 Revision A2 W942516CH Timing Waveforms, continued 10.3 Read Timing (Burst Length = 4) tCH CLK tCL tCK CLK tIS CMD tIH READ tIS tIH ADD Col tDQSCK tDQSCK tRPST Hi-Z Preamble tDQSQ tQH tQH tDQSQ Postamble tDQSQ Hi-Z CAS latency=2 Hi-Z DQS tDQSCK tRPRE Output (Data) Hi-Z tAC QA0 DA0 QA1 DA1 QA2 DA2 tDQSCK QA3 DA3 tHZ tDQSCK tLZ tDQSCK CAS latency=2.5 Hi-Z DQS Preamble tDQSQ Output (Data) Hi-Z tAC tLZ tQH tQH tDQSQ tRPRE tRPST Hi-Z Postamble tDQSQ Hi-Z QA0 DA0 QA1 DA1 QA2 DA2 QA3 DA3 tHZ Note: The correspondence of LDQS, UDQS to DQ. ( W942516AH) LDQS UDQS DQ0~7 DQ8~15 - 30 - W942516CH Timing Waveforms, continued 10.4 Write Timing (Burst Length = 4) tCH CLK tCL tCK CLK CMD WRIT tIS ADD Col tIH tDSH tDSS tDSH tDSS x4, x8 device tWPRES tWPRE Preamble tDS tDQSH tDQSL tDQSH tWPST DQS tDS tDH tDH DA1 DA2 Postamble tDS tDH DA3 Input (Data) DA0 tDQSS x16 device tDSH tDQSH tDSS tDQSL tDSH tDQSH tDSS tWPST tWPRES tWPRE Preamble tDS LDQS Postamble tDS tDH tDS tDH tDH DA3 DQ0~7 tDQSS tDSSK DA0 DA1 DA2 tDSSK tDSSK tDSSK tDSH tWPRES UDQS tDSS tDQSL tDSH tDQSH tDSS tWPST tDQSH tWPRE Preamble tDS tDH tDS tDS Postamble tDH DA3 tDH DA1 DA2 DQ8~15 DA0 tDQSS tDSH Note: x16 has 2DQS's (UDQS for uper byte and LDQS for lower byte). Even if one of the 2 bytes is not used, both UDQS and LDQS must be toggled. - 31 - Publication Release Date: May 20, 2003 Revision A2 W942516CH Timing Waveforms, continued 10.5 DM, Data Mask (W942508CH /W942504CH) CLK /CLK CMD WRIT DQS tDS tDS tDH tDH DM tDIPW DQ D0 D1 D3 tDIPW Masked 10.6 DM, Data Mask (W942516CH) CLK /CLK CMD WRIT LDQS tDS tDS tDH tDH LDM tDIPW DQ0~ DQ7 D0 D1 tDIPW Masked D3 UDQS tDS tDS tDH tDH UDM tDIPW DQ8~ DQ15 D0 Masked D2 D3 tDIPW - 32 - W942516CH Timing Waveforms, continued 10.7 Mode Register Set (MRS) Timing CLK CLK tMRD CMD MRS NEXT CMD ADD Register Set data A0 A2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BS0 BS1 "0" "0" Reserved "0" "0" "0" "0" "0" Reserved DLL Reset CAS Latency Addressing Mode Burst Length 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A3 0 1 A6 0 0 0 0 1 1 1 Mode Register Set or Extended Mode Register Set 1 A5 0 0 1 1 0 0 1 1 A8 0 * "Reserved" should stay "0" during MRS cycle. BS1 0 0 1 1 1 BS0 0 1 0 1 A4 0 1 0 1 0 1 0 1 A0 0 1 0 1 0 1 0 1 Burst Length Sequential Reserved 2 4 8 Interleaved Reserved 2 4 8 Reserved Reserved Addressing Mode Sequential Interleaved CAS Latency Reserved 2 3 Reserved 2.5 Reserved DLL Reset No Yes MRS or EMRS Regular MRS cycle Extended MRS cycle Reserved - 33 - Publication Release Date: May 20, 2003 Revision A2 W942516CH Timing Waveforms, continued 10.8 Extend Mode Register Set (EMRS) Timing CLK CLK tMRD CMD EMRS NEXT CMD ADD Register Set data A0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BS0 BS1 "0" "0" A1 "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" Mode Register Set or Extended Mode Register Set Reserved BS1 0 0 1 1 BS0 0 1 0 1 0 1 DLL Switch Output Driver 0 1 DLL Switch Enable Disable Output Driver Size Full Strength Hall Strength MRS or EMRS Regular MRS cycle Extended MRS cycle * "Reserved" should stay "0" during EMRS cycle. - 34 - W942516CH Timing Waveforms, continued 10.9 Auto Precharge Timing (Read Cycle, CL = 2) 1) tRCD (READA) tRAS (min) - (BL/2) x tCK tRAS tRP CLK CLK BL=2 CMD ACT READA AP ACT DQS DQ Q0 Q1 BL=4 CMD ACT READA AP ACT DQS DQ Q0 Q1 Q2 Q3 BL=8 CMD ACT READA AP ACT DQS DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Notes: CL2 shown; same command operation timing with CL = 2.5 In this case, the internal precharge operation begin after BL/2 cycle from READA command. Represents the start of internal precharging. The Read with Auto precharge command cannot be interrupted by any other command. AP - 35 - Publication Release Date: May 20, 2003 Revision A2 W942516CH Auto Precharge Timing (Read cycle, CL = 2), continued 2) tRCD/RAP(min) tRCD (READA) < tRAS (min) - (BL/2) x tCK tRAS CLK CLK BL=2 CMD ACT tRAP tRCD DQS tRP READA AP ACT DQ Q0 Q1 BL=4 CMD ACT tRAP tRCD DQS READA AP ACT DQ Q0 Q1 Q2 Q3 BL=8 CMD ACT tRAP tRCD DQS READA AP ACT DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Notes: CL2 shown; same command operation timing with CL = 2.5 In this case, the internal precharge operation does not begin until after tRAS (min) has command. AP Represents the start of internal precharging. The Read with Auto Precharge command cannot be interrupted by any other command. - 36 - W942516CH Timing Waveforms, continued 10.10 Auto Precharge Timing (Write Cycle) CLK CLK tDAL BL=2 CMD WRITA AP ACT DQS DQ D0 D1 tDAL BL=4 CMD WRITA AP ACT DQS DQ D0 D1 D2 D3 BL=8 CMD WRITA tDAL AP ACT DQS DQ D0 D1 D2 D3 D4 D5 D6 D7 The Write with Auto Precharge command cannot be interrupted by any other command. AP Represents the start of internal precharging . - 37 - Publication Release Date: May 20, 2003 Revision A2 W942516CH Timing Waveforms, continued 10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) CLK CLK CMD ACT READ A READ B READ C READ D READ E tRCD tCCD COl,Add,A Col,Add,B tCCD Col,Add,C tCCD Col,Add,D tCCD Col,Add,E ADD Row Address DQS DQ QA0 QA1 QB0 QB1 QC0 10.12 Burst Read Stop (BL = 8) CLK CLK CMD READ BST CAS Latency=2 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 CAS Latency=2.5 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 - 38 - W942516CH Timing Waveforms, continued 10.13 Read Interrupted by Write & BST (BL = 8) CLK CLK CAS Latency=2 CMD READ BST WRIT DQS DQ CAS Latency=2.5 CMD READ Q0 Q1 Q2 Q3 Q4 Q5 D0 D1 D2 D3 D4 D5 D6 D7 BST WRIT DQS DQ Q0 Q1 Q2 Q3 Q4 Q5 D0 D1 D2 D3 D4 D5 D6 D7 Burst Read cycle must be terminated by BST Command to avoid I/O conflict. 10.14 Read Interrupted by Precharge (BL = 8) CLK CLK CMD READ PRE CAS Latency=2 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 CAS Latency=2.5 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 - 39 - Publication Release Date: May 20, 2003 Revision A2 W942516CH Timing Waveforms, continued 10.15 Write Interrupted by Write (BL = 2, 4, 8) CLK CLK CMD ACT WRIT A WRIT B WRIT C WRIT D WRIT E tRCD tCCD COl. Add. A Col.Add.B tCCD tCCD tCCD Col. Add. E ADD Row Address Col. Add. C Col. Add. D DQS DQ DA0 DA1 DB0 DB1 DC0 DC1 DD0 DD1 10.16 Write Interrupted by Read (CL = 2, BL = 8) CLK CLK CMD WRIT READ DQS DM tWTR DQ D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Data must be masked by DM Data masked by READ command, DQS input ignored. - 40 - W942516CH Timing Waveforms, continued 10.17 Write Interrupted by Read (CL = 2.5, BL = 4) CLK CLK CMD WRIT READ DQS DM tWTR DQ D0 D1 D2 D3 Q0 Q1 Q2 Q3 Data must be masked by DM 10.18 Write Interrupted by Precharge (BL = 8) CLK CLK CMD WRIT PRE ACT tWR DQS tRP DM DQ D0 D1 D2 D3 D4 D5 D6 D7 Data masked by PRE command, DQS input ignored. Data must be masked by DM - 41 - Publication Release Date: May 20, 2003 Revision A2 W942516CH Timing Waveforms, continued 10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) tCK = 100 MHz CLK CLK tRC(b) tRC(a) tRRD CMD tRRD ACTb ACTa READAa READAb ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRP(b) tRP(a) DQS Preamble CL(a) DQ Postamble Preamble Postamble CL(b) Q0a Q1a Q0b Q1b ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b APa APb 10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) CLK CLK tRC(b) tRC(a) tRRD tRRD CMD ACTa ACTb tRCD(a) READAa READAb ACTa ACTb tRAS(a) tRCD(b) tRAS(b) tRP(a) tRP(b) DQS Preamble CL(a) CL(b) Q0a Q1a Postamble DQ Q2a Q3a Q0b Q1b Q2b Q3b ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b APa APb - 42 - W942516CH Timing Waveforms, continued 10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) CLK CLK tRC(a) tRRD tRRD tRRD tRRD CMD ACTa ACTb tRCD(a) tRAS(a) ACTc READAa ACTd READAb ACTa READAc tRP tRCD(b) tRAS(b) tRCD(c) tRAS(c) tRCD(d) tRAS(d) DQS Preamble CL(a) CL(b) Q0a Q1a Q0b Q1b Postamble Preamble DQ ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d APa APb 10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) CLK CLK tRC(a) tRRD tRRD tRRD tRRD CMD ACTa tRCD(a) ACTb READAa ACTc READAb ACTd READAc ACTa READAd tRAS(a) tRCD(b) tRAS(b) tRCD(c) tRAS(c) tRP(a) tRCD(d) tRAS(d) DQS Preamble CL(a) CL(b) CL(c) Q0a Q1a CL(b) Q1a DQ Q0a Q2a Q3a Q0b Q1b Q2b Q3b ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d APa APb APc - 43 - Publication Release Date: May 20, 2003 Revision A2 W942516CH Timing Waveforms, continued 10.23 Auto Refresh Cycle CLK CLK CMD PREA NOP AREF NOP AREF NOP CMD tRP tRFC tRFC CKE has to be kept "High" level for Auto-Refresh cycle. 10.24 Active Power Down Mode Entry and Exit Timing CLK CLK tIH CKE tIS tCK tIH tIS Entry CMD NOP NOP Exit NOP CMD NOP 10.25 Precharged Power Down Mode Entry and Exit Timing CLK CLK tIH CKE tIS tCK tIH tIS Entry CMD NOP NOP Exit NOP CMD NOP - 44 - W942516CH Timing Waveforms, continued 10.26 Self Refresh Entry and Exit Timing CLK CLK tIH CKE tIS tCK tIH tIS CMD PREA NOP tRP SELF SELFX NOP CMD Entry Exit tXSNR tXSRD SELF SELFX NOP ACT NOP READ NOP Entry Exit - 45 - Publication Release Date: May 20, 2003 Revision A2 W942516CH 11. PACKAGE DIMENSION TSOP 66l - 400 mil - 46 - W942516CH 12. REVISION HISTORY REVISION A1 DATE Aug. 28, 2002 Jan. 9, 2003 Feb. 14, 2003 A2 May 20, 2003 PAGE 28 DESCRIPTION Preliminary datasheet Add CAS Latency = 3 option Modified AC timing spec. Add CL2.5 optional in DDR400 Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 47 - Publication Release Date: May 20, 2003 Revision A2 |
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