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HVL3224QE
LCD CONTROLLER
HVL3224QE LCD CONTROLLER
May/30//2003
HYVIX 1
HVL3224QE
LCD CONTROLLER
GENERAL DESCRIPTION
The HYVIX-MAIN-R003, color-graphics 100 Pin TQFP LCD controller board displays 320-by-240 dot graphics for 65K STN colors. A 16-bit high-speed bus interface and external highspeed SRAM write function enable efficient data transfers and high-speed rewriting of data to the graphics RAM. The feature of this product is less afterimage than old product and possible 2 mode programming (pixel mode, block mode). The HVL3224QE is suitable for any midsized product, such as PDA, digital camera, GPS and DVD/VCD player.
QE 24 32 VL H
FEATURES
The HVL3224QE has the following features: y y y y y y y y y y y y y y y y 65K color bitmap STN-LCD display controller RGB (5:6:5) format Less afterimage than old product Max display area (Horizontal 320 lines x Vertical 240 lines) LCD panel interface(frame, line, data 4 or 8 bits, clock(latch pulse), dispoff, bias) External frame memory interface (SRAM) Moving picture for the general color STN LCD panel Any size support within the max size Color inverting Display On/Off Flexible display resolution Display data writing start line and column address set Pixel write and block write Bias selection Logic supply (3.3V) C-MOS silicon process Low current consumption Package (100 pin TQFP) y y Max 30 frames 16 bit BUS interface
HYVIX
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HVL3224QE
LCD CONTROLLER
PIN ASSIGNMENT - 100 TQFP
75
74
73
72
71
70
69
68
67
65
64
62
61
60
59
57
56
55
54
53
52 SA12
66
63
58
VSS
LVDD
LVDD VSS SA13 SA14 SA15 SA16 SA17 WE OE CE VSS
SD12
SD10
SD11
SD13
SD14
SD15
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
LVDD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 VSS FR FM LP XCLK OFF LVDD XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 PLLTEST BYPASS DATA15 DATA14 CLOCK RESET TSTEN CHGO VSS DATA13 HVDD HVDD ADD1 LVDD ADD0 LVDD ADD3 ADD2
SA10
SA11
VSS
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SD8
SD9
SA0
SA9
51
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
HIVIX
HVL65K100XA
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 LVDD DATA8 DATA9 DATA10 DATA11 DATA12 LVDD VSS 25
XPD
VSS
VSS
VSS
11
12
16
WR
TP
CS
17
19
20
22
10
13
14
15
18
21
23
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1
2
5
3
4
6
7
8
9
3
HVL3224QE
LCD CONTROLLER
PIN DEMENSION
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HVL3224QE
LCD CONTROLLER
PIN DESCRIPTION
Signals PLL TEST XPD VSS HVDD VSS HVDD CHGO VSS BYPASS TP TSTEN CLOCK RESET CS LVDD WR ADD3 ADD2 ADD1 ADD0 LVDD DATA15 DATA14 DATA13 VSS LVDD DATA12 DATA11 DATA10 DATA9 DATA8 LVDD DATA7 DATA6 DATA5 DATA4 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VSS INPUT INPUT INPUT INPUT INPUT INPUT VDD INPUT INPUT INPUT INPUT INPUT VDD INPUT INPUT INPUT VSS VDD INPUT INPUT INPUT INPUT INPUT VDD INPUT INPUT INPUT INPUT MPU 3.3V MPU MPU MPU MPU MPU 3.3V MPU MPU MPU GND 3.3V MPU MPU MPU MPU MPU 3.3V MPU MPU MPU MPU External Data I/O port Power Supply for logic circuits(3.3V) External Data I/O port Common Ground Power Supply for logic circuits(3.3V) External Data I/O port Power Supply for logic circuits(3.3V) External Interface Address Input port I/O INPUT INPUT VSS VDD VSS VDD Connected to N. C. N. C. GND 3.3V GND 3.3V N. C. GND N. C. N. C. N. C. Functions For PLL Test For PLL Test Common Ground Power Supply for logic circuits(3.3V) Common Ground Power Supply for logic circuits(3.3V) For PLL Test Common Ground For PLL Test For Chip Debugging For Chip Debugging Main Clock Chip Reset External Interface Chip select, Active "0" Power Supply for logic circuits(3.3V) Chip Write Signal
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HVL3224QE
LCD CONTROLLER
DATA3 DATA2 DATA1 DATA0 VSS CE OE WE SA17 SA16 SA15 SA14 SA13 VSS LVDD SA12 SA11 SA10 SA9 SA8 VSS SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 LVDD SD15 SD14 SD13 SD12 SD11 SD10 SD9
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
INPUT INPUT INPUT INPUT VSS OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT VSS VDD OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT VSS OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT VDD BID BID BID BID BID BID BID
MPU MPU MPU MPU GND EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM GND 3.3V EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM GND EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM 3.3V EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM SRAM Data I/O port
Power Supply for logic circuits(3.3V)
External Data I/O port
Common Ground SRAM Chip Enable, Active "0" SRAM Output Enable, Active "0" SRAM Write Enable, Active "0"
SRAM Address Output port
Common Ground
Power Supply for logic circuits(3.3V)
SRAM Address Output port
Common Ground
SRAM Address Output port
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HVL3224QE
LCD CONTROLLER
SD8 VSS LVDD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 VSS FR FM LP XCLK OFF LVDD XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 VSS
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
BID VSS VDD BID BID BID BID BID BID BID BID VSS OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT VDD OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT VSS
EXT. SRAM GND 3.3V EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM EXT. SRAM GND LCM LCM LCM LCM LCM 3.3V LCM LCM LCM LCM LCM LCM LCM LCM GND
SRAM Data I/O port Common Ground
Power Supply for logic circuits(3.3V)
SRAM Data I/O port
Common Ground LCD Bias Signal LCD Synchronous Signal for driving scanning line LCD Data Signal Latch Clock LCD Data Signal Shift Clock LCD OFF
Power Supply for logic circuits(3.3V)
LCD Display Data Output port
Common Ground
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LCD CONTROLLER
PIN CROSS REFERENCE : NUMERICAL ORDER BY PIN NUMBER
PIN # PIN NAME PIN # PIN NAME PIN # PIN NAME PIN # PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PLLTEST XPD VSS MVDD VSS AVDD CHGO LPVSS BYPASS TP TSTEN CLOCK RESET CS RD WR ADD3 ADD2 ADD1 ADD0 VCCIO DATA15 DATA14 DATA13 GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCCINT DATA12 DATA11 DATA10 DATA9 DATA8 VCCIO DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND CE OE WE SA17 SA16 SA15 SA14 SA13 GND 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 VCCINT SA12 SA11 SA10 SA9 SA8 GND SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 VCCIO SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 GND 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VCCINT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 GND FR FM LP XCLK OFF VCCIO XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 GND
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HVL3224QE
LCD CONTROLLER
FUNCTIONAL DESCRIPTION
HVL3224QE receives the image pixel data from the interface (like a camera or Microprocessor) and saves it in SRAM. After that HVL3224QE brings the pixel data in order and makes it go through the unique data conversion algorithm and changes it to the proper color data through the RGB table, and then it is transmitted to color STN LCD with an address.
Read Operation
Read Waveform
tRC Address tAA RD tOE tRLZ CS tACE DataOut tCLZ DataValid tCHZ tRHZ
tOH
Read Cycle Parameter Read cycle time Address access time Chip select (CS) access time Output enable (RD) access time Output hold from address change CS Low to output in low Z CS High to output in high Z RD Low to output in low Z RD High to output in high Z Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tRLZ tRHZ Min 10 3 0 0 Max 10 10 5 5 5 Unit ns ns ns ns ns ns ns ns ns
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HVL3224QE
LCD CONTROLLER
Write Operation
Write Waveform
tWC tAH tWR Address
tCW CS tAW tAS WR tDW DataIN tWZ DataOUT Dataundefined HighZ DataValid tWP
tDH
tOW
Write Cycle Parameter Write cycle time Chip enable (CS) to write end Address setup to write end Address setup time Write pulse width (RD=high) Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in High-Z Output active from write end Symbol tWC tCW tAW tAS tWP1 tWR tAH tDW tDH tWZ tOW Min 10 5 5 0 5 0 0 5 0 0 5 Max 0 5 Unit ns ns ns ns ns ns ns ns ns ns ns
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HVL3224QE
LCD CONTROLLER
LCD Interface Example
HIROSE HIF3F-40PA 3.3V FR LP OFF D0 D2 D4 D6 3.3V FM XCLK D1 D3 D5 D7
2
* Insert a 33 U resistance to each signal line and connect Driver * Use a thick and short signal line to each signal * Use a thick and wide GND line
Step-Up Circuit (LCD Power)
D R I V E R
STN LCD
39
0V
0V
40
INVERTER
5V 0V
Back Light
LCD Interface Timing Chart
LP
XCLK XD0 ~XD7
SEG 944~951 SEG 952~959 SEG 0~7 SEG 8~15
#1DATA
SEG 944~951
SEG 952~959
SEG 0~7
SEG 8~15
FLM
LP
(Reduction)
240xT
FLM
(Reduction)
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HVL3224QE
LCD CONTROLLER
CONTROL REGISTER DESCRIPTION
Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 Rst LPI 1
FMI 1
LPI 9
FMI 9
LPI 8
FMI 8
LPI 7
FMI 7
LPI 6
FMI 6
LPI 5
FMI 5
LPI 4
FMI 4
LPI 3
FMI 3
LPI 2
FMI 2
bit 0 MG Inv LPI LPW LPW LPW LPW LPW LPW 0
0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
5
5
4
4
3
3
2
2
1
1
0
0
FMI FMW FMW FMW FMW FMW FMW
M7
M6
M5
M4
M3
M2
M1
M0
XL8 XL7 XL6 XL5 XL4 XL3 XL2 XL1 XL0 YL8 YL7 YL6 YL5 YL4 YL3 YL2 YL1 YL0 X8 Y8 R3 R2 R1 R0 G5 G4 G3 X7 Y7 G2 X6 Y6 G1 X5 Y5 G0 X4 Y4 B4 X3 Y3 B3 X2 Y2 B2 X1 Y1 B1 X0 Y0 B0
0x0A R4 0x0B 0x0C 0x0D 0x0E 0x0F
Table 2-1 LCD Decoder Registers
y y y y y y y y y y
MG : M generator function enable Rst : Software Reset Inv : Set by 1, The color is turned over Set by 0, The color won't be changed Doff : Screen off M7~M0 : M Configuration XL8~XL0 : Point out the color LCD horizontal resolution YL8~YL0 : Point out the color LCD vertical resolution X0~8 : Column Data address of the main frame memory Y0~8 : Row Data address of the main frame memory (default) R4~R0, G5~G0, B4~B0 : RGB display data (5:6:5)bit
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HVL3224QE
LCD CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Item Power Supply Voltage Input Voltage Output Voltage Output Current/Pin Storage Temperature Symbol VDD VI VO IOUT TSTG Limits -0.3 to 4.0 -0.3 to VDD + 0.5 -0.3 to VDD + 0.5 30 -65 to 150
*1 *1
Unit V V V mA C
*1: Possibles to use from -0.3V to 7.0V of N channel open drain bi-directional buffers, input buffer in the IDC and IDH systems and Fail Safe cells.
RECOMMENDED OPERATING CONDITIONS
Item Power Supply Voltage Input Voltage Ambient Temperature Normal Input Rising Time Normal Input Falling Time Schmitt Input Rising Time Schmitt Input Falling Time
Symbol VDD VI Ta tri tfa tri tfa
Min. 3.00 VSS 0 -40
Typ. 3.30
Max. 3.60 VDD
*1
Unit V V C ns ns ms ms
25 25
70 85*3 50 50 5 5
*2
*1: Possible to use 5.25 or 5.50V of N channel open drain bi-directional buffers, input buffer in the IDC and IDH systems and Fail Safe cells. *2: The ambient temperature range is recommended for Tj = 0 to 80C *3: The ambient temperature range is recommented for Tj = -40 to 125C
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HVL3224QE
LCD CONTROLLER
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V 0.3V, VSS = 0V, Ta = -40 to 85C)
Item Quiescent Current*1 Input Leakage Current Off State Leakage Current High Level Output Voltage Symbol IDDS ILI IOZ VOH IOH=-0.1mA(Type S), -1mA(Type M) -2mA(Type 1), -6mA(Type 2) -12mA(Type 3) VDD=Min. IOL=0.1mA(Type S), 1mA(Type M) 2mA(Type 1), 6mA(Type 2) 12mA(Type 3) VDD=Min. LVTTL Level, VDD=Max. LVTTL Level, VDD=Min. LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt PCI Level, VDD=Max. PCI Level, VDD=Min. PCI Response VOH=0.90V, VDD=Min. VOL=2.52V, VDD=Max. PCI Response VOH=1.80V, VDD=Min. VOL=0.65V, VDD=Max. Type 1 Pull Up Resistor
*2
Conditions Quiescent Conditions
Min. -1 -1 VDD -0.4
Typ. Max. Unit 170 1 1 A A A V
Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage High Level Input Voltage*3 Low Level Input Voltage
*3
VOL VIH1 VIL1 VT1+ VT1VH1 VIH3 VIL3 IOH3
0.4 2.0 0.8 1.1 0.6 0.1 1.8 0.9 -36 -115 48 137 20 40 20 40 50 2.4 1.8
V V V V V V V V mA mA mA mA
High Level Output Current*3
Low Level Output Current*3
IOL3
RPU
VI = 0V Type 2 Type 1
Pull Down Resistor*2
RPD
VI = VDD Type 2 Bus Hold Response, VIN=2.0V VDD=Min. Bus Hold Response, VIN=0.8V VDD=Min. Bus Hold Response, VIN=0.8V VDD=Max. Bus Hold Response, VIN=2.0V VDD=Max. f =1MHz, VDD=0V f =1MHz, VDD=0V f =1MHz, VDD=0V
(100) 120 k (200) 100 240 (100) 50 120 k (200) 100 240 -20 17 A A A A 10 10 10 pF pF pF
High Level Maintenance Current Low Level Maintenance Current High Level Reversal Current Low Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance
IBHH IBHL IBHHO IBHLO CI CO CIO
-350 210
*1: The quiescent current is a typical value (Tj=85C) for each master. For details, please see Tables 1-9 and 1-10. *2: The values parenthesized means in case of Ta=0 to 70C. Values are doubled for VDD=3.3V-0.3V, VSS=0V, and Ta=-40C to 85C. *3: Complies with Rev. 2.2 of PCI standard.
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HVL3224QE
LCD CONTROLLER
TYPICAL APPLICATION PART LIST
No. Qty 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 12 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reference C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12 C13, C14 D1,D2 JP1 JP2 JP3 J1 L1 R1 R2 R3 R4 SW1 U1 U2 U3 Y1 104 100uF 16V GREEN (LED) HEADER 20X2 JUMPER 3X1 HEADER 25X2 CON2 BEAD FERRITE 1K 220 470 200 TAC HVL3224QE K6R4016V1C-T10 EZ1117-3.3V 50MHz HYVIX SAMSUNG SEMTECK Part Mfg
SCHEMATIC
HYVIX
15
5
U1 JP1 3.3V FM XCLK 3.3V 3.3V 1 2 7 9 10 11 PLLTEST XPD CHGO BYPASS TP TSTEN CE OE WE CLOCK RESET CS WR ADD3 ADD2 ADD1 ADD0 FR LP OFF XD0 XD2 XD4 XD6 XD1 XD3 XD5 XD7 CLOCK RESET CS WR 12 13 14 16 17 18 19 20 ADD3 ADD2 ADD1 ADD0 42 43 44 CE OE WE
4
3
2
1
U2
D
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
7 8 9 10 13 14 15 16
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
D
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 HEADER 20X2 45 46 47 48 49 52 53 54 55 56 58 59 60 61 62 63 64 65 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 2 3 4 5 18 19 20 21 22 23 24 25 26 27 42 43 44
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16
29 30 31 32 35 36 37 38
SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
39 40
LB UB
VCC VCC
11 33
3.3V
WE OE
17 41
WE OE
GND GND
12 34
CE
6
CS 3.3V
C
JP3
K6R4016V1C-T10
C
3.3V
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 22 23 24 27 28 29 30 31 33 34 35 36 37 38 39 40 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 HVDD HVDD 4 6 3.3V
Y1 J1 1 2 CON2
5V
1
E/D
VCC
4
3.3V
2
GND
OUT
3
CLOCK
R4 200
SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
67 68 69 70 71 72 73 74 77 78 79 80 81 82 83 84
SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
DATA0 DATA2 DATA4 DATA6 DATA8 DATA10 DATA12 DATA14 ADD0 ADD2
DATA1 DATA3 DATA5 DATA7 DATA9 DATA11 DATA13 DATA15 ADD1 ADD3
50MHz
CS WR
RST1
3.3V
5V
U3 C13 100uF 16V + C14 100uF 16V
L1
15 21 26 32 51 66 76 91 LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD FR FM LP XCLK OFF 86 87 88 89 90
FR FM LP XCLK OFF
5V
3
VIN
VOUT
2
1
2
3.3V
GND
B
+
B
BEAD FERRITE 3.3V
EZ1117-3.3V
1
XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
92 93 94 95 96 97 98 99
XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 HEADER 25X2
3 5 8 25 41 50 57 75 85 100 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS HVL3224QE
JP2 RST2 3.3V
R1 1K
SW1 R2 220 D1 GREEN R3 470 5V GREEN D2 #610, TIC, KITI, 6FL, Suwon Univ., San 2-2, Wawoo-ri, Bongdam-eub, Hwasung city, Kyungki-do, Korea Title C11 104 C12 104 STN LCD Controller (HVL3224QE) Size A4 Date: Document Number Monday, June 02, 2003 Sheet 1 of 1 Rev 1
RST1 RESET RST2
1 2 3
JUMPER
TAC
3.3V
A
C9 104 C10 104
A
HYVIX Co., LTD
C1 104
C2 104
C3 104
C4 104
C5 104
C6 104
C7 104
C8 104
The capacitors are closely connected with each 3.3V power pin of IC.
4 3
5
2
1

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