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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8131
Features
* 2.488Gb/s 32:1 Mux with Clock Generator * SONET STS-48/SDH STM-16 * LVPECL Differential High Speed Serial Data and Clock Outputs
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
* 32 TTL Parallel Data Inputs with Odd/Even Parity Check * 128 Pin, 14x20x2 mm Enhanced-PQFP * Single 3.3V Supply * 2.15W Max Power Dissipation
General Description
The VSC8131 multiplexes 32 TTL compatible 77.76Mb/s Parallel Data Inputs (D0-D31) into a single LVPECL 2.488 Gb/s serial output (DO+) for use in SONET STS-48/SDH STM-16 systems. An integrated Clock Multiplier Unit (CMU) generates a LVPECL 2.488 GHz clock signal (CO+) from an externally supplied LVPECL compliant 77.76MHz reference clock (REFCLK+) which is used to retime the transmitted serialized data. A Divide-by-32 TTL clock output (CK78OUT) is used as a clock input (CK78IN) for timing of the parallel data inputs. Parity Checking (PARBIT) is performed on the incoming data with a selectable even or odd TTL parity mode input (PARMODE) and a TTL Parity Error (PARERR) output. A TTL Loss Of Lock (LOL) output indicator is used to report the loss of the REFCLK+ or for conditions resulting in the CMU losing lock to incoming clock.
VSC8131 Block DIagram
CK78IN PARMODE PARBIT Parity Register PARERR
D0 Parallel Data Receivers D31 Clock/32 Input Registers
32:1 Multiplexer Output Register DO+ DO-
CK78OUT
Timing Generator
CO+ CO-
REFCLK+ REFCLK-
CMU x32
Bit Rate Clock LOL
G52249-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Preliminary Datasheet
VSC8131
Functional Description
Low Speed Interface The timing for the low speed parallel interface is based upon the CK78OUT output signal. The intent is to have the device upstream from the VSC8131 use the CK78OUT clock signal as the timing source for its final output stage latch. CK78IN is to be driven by CK78OUT, refer to Figure 1. This reduces the setup time of the VSC8131. The maximum propagation delay permitted from CK78OUT to CK78IN is specified by tCKPROP in the AC Characteristics. The setup and hold time of the data inputs are specified with respect to the rising edge of CK78IN. D0-D31, CK78OUT, and CK78IN are TTL compatible inputs. Figure 1: Low Speed System Interface
33
D[0:31], PARBIT
33
CK78IN
Upstream Device
VSC8131
CK78OUT REFCLK
Divide by 32 2.488 GHz PLL
Parity A parity check is performed between the parity bit input (PARBIT) and the 32 parallel data inputs (D0D31). Even versus odd parity checking is selected with PARMODE. Set PARMODE low to test for odd parity. Set PARMODE high to test for even parity. The parity error output (PARERR) is set to a logic high when a parity error has occurred. The PARERR signal can be changed from an active high to active low signal by complementing the PARMODE input. PARERR is re-calculated each time new parallel data is clocked in. The newly calculated PARERR result is clocked out on the rising edge of CK78IN 2 cycles after the data is loaded. PARBIT, PARMODE, and PARERR conform to TTL output levels.
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52249-0, Rev. 3.0
11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8131
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
High Speed Data Output The high speed data will be multiplexed in the sequence D0, D1 up to D31 with D0 being transmitted first. The high speed data output driver consists of a differential pair designed to drive a 50 transmission line. The transmission line should be terminated with a 100 resistor at the load between the true and complement outputs, refer to Figure 2. No connection to a termination voltage is required. The output driver is back terminated to 50 on-chip, providing snubbing of any reflections. If used single-ended, the high speed output driver must still be terminated differentially at the load with a 100 resistor between the true and complement output signals. High Speed Clock Output The high speed clock output driver consists of a differential pair designed to drive a 50 transmission line. The transmission line should be terminated with a 100 resistor at the load between the true and complement output, refer to Figure 2. No connection to a termination voltage is required. The output driver is back terminated to 50 on-chip, providing a snubbing of any reflections. If used single-ended, the high speed output driver must still be terminated differentially at the load with a 100 resistor between the true and complement output signals. Figure 2: Termination for High Speed Clock and Data Output Drivers
VCC
50
50 100
Pre-Driver
Z0 = 50
VEE
G52249-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Preliminary Datasheet
VSC8131
Clock Generator An on-chip Phase Locked Loop (PLL) generates the 2.488 GHz transmit clock from the externally provided REFCLK input. The on-chip PLL uses a low phase noise reactance based Voltage Controlled Oscillator (VCO) with an on-chip loop filter. The loop bandwidth of the PLL is within the SONET specified limit of 2MHz. The REFCLK is 77.76MHz and should be of high quality. Noise on the REFCLK below the loop band width of the PLL will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a VCXO may be required to avoid passing REFCLK noise with greater than 4ps RMS of jitter to the output. Such a condition would create an output from the VSC8131 which has the REFCLK noise in addition to the intrinsic jitter from the VSC8131 itself. REFCLK is a LVPECL level and is required to be a differential signal in order to meet the 4pS RMS jitter spec. The true and complement inputs of the differential PECL receiver are internally biased to VCC/2 so that the REFCLK signal can be AC coupled without using external bias resistors, refer to Figure 3. REFCLK can be DC coupled by simply over-driving the internal bias voltage. Figure 3: REFCLK Internal Bias Configuration
VCC = +3.3V
INPUT
VCC
2
INPUT
VCC
All Resistors 3.3K
2
VEE = 0V
Loss of Lock The Loss Of Lock (LOL) output is used to indicate if the CMU is locked. A loss of lock condition is reported when the CMU does not lock to the REFCLK frequency or when the REFCLK input signal is not present. LOL is high when the CMU is locked. LOL is low when the REFCLK input signal is not present (input floating due to cut line or input stuck high or low). The LOL signal will appear as a pulse train of 1's and 0's when the REFCLK is present, but the CMU is not locked to the REFCLK's frequency. The frequency of the LOL pulse train can be anywhere from 500Hz to 50MHz.
Page 4
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52249-0, Rev. 3.0
11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8131
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Supplies This device is specified as a LVPECL device with a single +3.3V supply. Normal operation is to have VCC=+3.3V and VEE=ground. Should the user desire to use the device in an ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be -3.3V. If used with VEE tied to -3.3V, the TTL I/O signals are still referenced to VEE. Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is recommended that the VCC power supply be decoupled using a 0.1F and 0.01F capacitor placed in parallel on each VCC power supply pin as close to the package as possible. If room permits, a 0.001F capacitor should also be placed in parallel with the 0.1F and 0.01F capacitors mentioned above. Recommended capacitors are low inductance ceramic SMT X7R devices. For the 0.1F capacitor, a 0603 package should be used. The 0.01F and 0.001F capacitors can be either 0603 or 0403 packages. Extra care needs to be taken when decoupling the analog power supply pins (labeled VCCANA). In order to maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8131, the analog power supply pins should be filtered from the main power supply with a 10H C-L-C pi filter. If preferred, a ferrite bead may be used to provide the isolation. The 0.1F and 0.01F decoupling capacitors are still required and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead). For low frequency decoupling, 47F tantalum low inductance SMT caps are sprinkled over the board's main +3.3V power supply and placed close to the C-L-C pi filter. If the device is being used in an ECL environment with a negative 3.3V supply, then all references to decoupling VCC must be changed to VEE, and all references to decoupling +3.3V must be changed to -3.3V.
G52249-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Preliminary Datasheet
VSC8131
AC Characteristics
Table 1: VSC8131 Multiplexer AC Characteristics (Over recommended operating conditions) Parameter
tDRCLK tDCLK32 tDC32 tDCLOL tDSU tDH tPEO tCKPROP tCMD tr, tf tr, tf tr, tf tr, tf tr, tf REFCLK period CK78IN period CK78OUT (CLK/32) duty cycle LOL Duty Cycle (When CMU is not locked) D(0-31) and PARBIT set-up time (wrt CK78IN rising edge) D(0-31) and PARBIT hold time (wrt CK78IN rising edge) Parity error output timing; rising edge of CK78IN to PARERR Allowable propagation delay for connecting CK78OUT to CK78IN High speed clock output (CO+) timing; falling edge of CO+ to muxed data output (DO+) REFCLK rise and fall times (10%-90%) D(0.31) rise and fall times (10%-90%) CK78OUT, LOL and PARERR rise and fall times (10%-90%) DO+ rise and fall times (20%-80%) CO+ rise and fall times (20%-80%) 40 40 1.0 1.0 1.9 0 100 150 150
Description
Min
Typ
12.8 12.8 -
Max
60 60 6.0 3.0 270 1.5 2.0 4.0 170 170
Units
ns ns % % ns ns ns ns ps ns ns ns ps ps
Figure 4: VSC8131 Multiplexer Waveforms
C 78O T K U
Parallel data clock output tDC32 tCKPR P O tDCLK32 tDC32
C 78IN K
Parallel data clock input tDSU tDH
P RB , D A IT (0...31)
Parity and parallel data inputs
V LIDD T (1) A AA
V LIDD T (2) A AA
P RER A R
Parity error output
tPEO
tPEO
R EFCLK
R eference clock input tDRCLK
CO +
H speed differential clock output igh tCM D
D+ O
H speed differential serial data output igh
D 0
DDDD 12 3 4
... ... ... ... ... ... D277D28 D29 D30 D31
Serialized D ata
N TE: O
=D on't care
tDCLK32
D0 IS MSB AND TRANSMITTED FIRST
Page 6
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52249-0, Rev. 3.0
11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8131
DC Characteristics
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Table 2: VSC8131 Multiplexer DC Characteristics (Over recommended operating conditions) Parameters
VOH(DO) VOL(DO) VOD(DO)
Description
Output HIGH voltage (DO) Output LOW voltage (DO) Output differential voltage (DO) Output common mode voltage Output HIGH voltage (CO) Output LOW voltage (CO) Output differential voltage (CO) Output common mode voltage Back Termination Impedance (DO, CO) Input HIGH voltage (LVPECL) Input LOW voltage (LVPECL) Differential Input voltage (LVPECL) Input Common Mode Range (LVPECL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH Current (TTL) Input LOW Current (TTL) Supply voltage Power dissipation
Min
VCC-0.050 VCC-1.20 550
Typ
-- -- 850
Max
VCC VCC-0.60 1200
Units
V V mV
Conditions
50 Ohm Termination to VCC 50 Ohm Termination to VCC 100 Ohm Termination between DO+ at Load 100 Ohm Termination between DO+ at Load 50 Ohm Termination to VCC 50 Ohm Termination to VCC 100 Ohm Termination between CO+ at Load 100 Ohm Termination between CO+ at Load Guaranteed, not tested
VCM(DO) VOH(CO) VOL(CO) VOD(CO)
2.10 VCC-0.050 VCC-1.20 500
-- -- 850
3.00 VCC VCC-0.60 1200
V V V mV
VCM(CO) RO VIH VIL VIN VICM VOH VOL VIH VIL IIH IIL VCC PD
2.10 40 1.5 0 400 1.5-VIN/2 2.4
-
3.00 60
V Ohm V V mV V V
-
VCC-1.0v 1600 VCC-1.0VIN/2 0.5
IOH=-4.0 mA IOL=+4.0 mA
V V V uA uA V W mA
2.0 0.0
5.5 0.8 500 -500
VIN=2.4V VIN=0.5V 3.3V+ 5% Outputs open, VCC = VCC max Outputs open, VCC = VCC max
3.14 -- --
-- 1.7 495
3.47 2.15 620
ICC
Supply Current
G52249-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Preliminary Datasheet
VSC8131
Clock Multiplier Unit
Table 3: VSC8131 CMU Performance Parameters
TJ LBW PeakJ
Description Output Clock and Data Jitter PLL Loop Bandwidth Jitter Peaking Tuning Range
Min
--
Max
4 2.0 0.1
Units
ps. MHz dB ppm
Conditions RMS, tested to SONET specification with 2ps RMS jitter on REFCLK -3dB point of jitter transfer curve REFCLK to DO
-100
+100
Absolute Maximum Ratings (1)
Power Supply Voltage, (VCC)....................................................................................................... -0.5V to +3.8V DC Input Voltage (Differential inputs) .................................................................................-0.5V to VCC +0.5V DC Input Voltage (TTL inputs) .................................................................................................... -0.5V to +5.5V DC Output Voltage (TTL Outputs)...................................................................................... -0.5V to VCC + 0.5V Output Current (TTL Outputs) .............................................................................................................. +/-50mA Output Current (Differential Outputs)....................................................................................................+/-50mA Case Temperature Under Bias ...................................................................................................... -55o to +125oC
Recommended Operating Conditions
Power Supply Voltage, (VCC)..............................................................................................................+3.3V+5% Operating Temperature Range ...........................................................0oC Ambient to +85oC Case Temperature
Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC8131 is rated to 1500V based on the human body model.
Page 8
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52249-0, Rev. 3.0
11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8131
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Figure 5: Parametric Measurement Information
TTL Rise and Fall Time
80% 20%
Tr
Tf
Parametric Test Load Circuit Serial Output Load
Z0 = 50
50 VCC-2V
G52249-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Preliminary Datasheet
VSC8131
Package Pin Description
Table 4: Package Pin Identification Signal
NC TEST TEST VCC VEE VEE VEE VCC CO+ COVCC VCC NC NC VEE VEE VEE VCC DO+ DOVCC NC VCC VCC VCC VEE VEE VEE VEE VEE NC NC NC NC NC NC
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
I/O
I I PWR PWR PWR PWR PWR O O PWR PWR PWR PWR PWR PWR O O PWR PWR PWR PWR PWR PWR PWR PWR PWR -
Level
GND GND +3.3V GND GND GND +3.3V LVPECL LVPECL +3.3V +3.3V GND GND GND +3.3V LVPECL LVPECL +3.3V +3.3V +3.3V +3.3V GND GND GND GND GND -
Pin Description
Leave Unconnected
2.488 GHz Clock, true 2.488 GHz Clock, compliment
Leave Unconnected Leave Unconnected
Serialized Data, true Serialized Data, compliment Leave Unconnected
Leave Unconnected Leave Unconnected Leave Unconnected Leave Unconnected Leave Unconnected Leave Unconnected
Page 10
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52249-0, Rev. 3.0
11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8131
Table 4: Package Pin Identification Signal
NC NC VCC VEE NC VEE VCC NC NC NC NC NC LOL VCC VEE PARERR CK78OUT VCC CK78IN NC VEE D31 D30 VCC D29 D28 NC VCC NC VCC D27 D26 VEE D25 D24 VCC D23
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Pin
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
I/O
PWR PWR PWR PWR O PWR PWR O O PWR I PWR I I PWR I I PWR PWR I I PWR I I PWR I
Level
+3.3V GND GND +3.3V TTL +3.3V GND TTL TTL +3.3V TTL GND TTL TTL +3.3V TTL TTL +3.3V +3.3V TTL TTL GND TTL TTL +3.3V TTL parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parity error
Pin Description
Leave Unconnected Leave Unconnected
Leave Unconnected
Leave Unconnected Leave Unconnected Leave Unconnected Leave Unconnected Leave Unconnected CMU loss of lock
divide-by-32 clock out divide-by-32 clock in Leave Unconnected (LSB)
Leave Unconnected Leave Unconnected
G52249-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Table 4: Package Pin Identification Signal
D22 VCC D21 D20 VEE D19 D18 VCC D17 D16 VCC D15 D14 VEE D13 D12 VCC D11 D10 VCC D9 D8 VEE D7 D6 VCC D5 D4 VCC VCC NC D3 D2 VCC D1 D0 VEE
Preliminary Datasheet
VSC8131
Pin
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
I/O
I PWR I I PWR I I PWR I I PWR I I PWR I I PWR I I PWR I I PWR I I PWR I I PWR PWR I I PWR I I PWR
Level
TTL +3.3V TTL TTL GND TTL TTL +3.3V TTL TTL +3.3V TTL TTL GND TTL TTL +3.3V TTL TTL +3.3V TTL TTL GND TTL TTL +3.3V TTL TTL +3.3V +3.3V TTL TTL +3.3V TTL TTL GND parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data parallel data
Pin Description
Leave Unconnected parallel data parallel data
(MSB)
Page 12
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52249-0, Rev. 3.0
11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8131
Table 4: Package Pin Identification Signal
PARBIT PARMODE VCC TEST NC REFCLK+ REFCLKVCC VEE TEST TEST VEE_ANA VCC_ANA NC NC VEE VEE VCC
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Pin
111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
I/O
I I PWR I I I PWR PWR O O PWR PWR PWR PWR PWR
Level
TTL TTL +3.3V GND LVPECL LVPECL +3.3V GND GND +3.3V GND GND +3.3V parity bit
Pin Description
parity mode select (even vs. odd)
Leave Unconnected CMU reference clock, true CMU reference clock, compliment
Leave Unconnected Leave Unconnected Analog Power for CMU Analog Power for CMU Leave Unconnected Leave Unconnected
NC = No Connection. These pins must be left floating - do not connect to a supply potential. Connecting any of these pins to a power supply rail may cause improper operation or failure of the device; or in extreme cases, may cause permanent damage to the device.
G52249-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 13
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Preliminary Datasheet
VSC8131
Package Information
Figure 6: 128 PQFP Package Drawing
PIN 128 PIN 1
PIN 102
Key
RAD. 2.92 .50 (2)
mm
2.35 0.25 2.00 17.20 14.00 23.20 20.00 .88 .50 .22 0-7 .30 .20
Tolerance
MAX MAX +.10 .20 .10 .20 .10 +.15/-.10 BASIC .05 TYP TYP
A A1 A2
E1 E
D D1 E
EXPOSED INTRUSION 0.127 MAX. EXPOSED HEATSINK
2.54 .50
E1 L e b
PIN 64
PIN 38 D1 D TOP VIEW 10 TYP.
R R1
A2
A
A1 10 TYP.
e
R
R1
1
STANDOFF
A
Notes: 1) 2) 3) Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package.
.25
A1
0.17
MAX.
b
LEAD COPLANARITY
NOTES:
L
Package #: 101-322-5 Issue #: 2
Page 14
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52249-0, Rev. 3.0
11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8131
Package Thermal Considerations
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in the following table
Table 5: Thermal Resistance Symbol
jc ja
Description
Thermal resistance from junction to case. Thermal resistance from junction to ambient with no airflow, including conduction through the leads.
C/W
2.2
25.6
Thermal Resistance with Airflow Shown in the table below is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst case power of the device multiplied by the thermal resistance. Table 6: Thermal Resistance with Airflow Airflow
100 lfpm 200 lfpm 400 lfpm 600 lfpm
ca (oC/W)
19.8 16.7 14.6 13.0
Maximum Ambient Temperature without Heatsink The worst case ambient temperature without use of a heatsink is given by the equation:
T A ( MAX ) = T C ( MAX ) - P ( MAX ) CA
where: A(MAX) Ambient Air temperature C(MAX) Case temperature (85oC for VSC8131) P(MAX) Power (2.15W for VSC8131) CA Theta case to ambient at appropriate airflow The results of this calculation are listed below:
G52249-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 15
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
Table 7: Maximum Ambient Air Temperature without Heatsink Airflow
none 100 lfpm 200 lfpm 400 lfpm 600 lfpm Max Ambient Temp oC 33.2 42.4 49.1 53.6 57.1
Preliminary Datasheet
VSC8131
Note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow.
Notice
This document contains preliminary information about a new product in the preproduction phase of development. The information in this document is based on initial product characterization. Vitesse reserves the right to alter specifications, features, capabilities, functions, manufacturing release dates, and even general availability of the product at any time. The reader is cautioned to confirm this datasheet is current prior to using it for design.
Warning
Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
Page 16
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52249-0, Rev. 3.0
11/9/99

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