 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE SY100S318 FEATURES s Max. propagation delay of 800ps s IEE min. of -55mA s Extended supply voltage option: VEE = -4.2V to -5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75K input pull-down resistors s s s s 70% faster than Fairchild 40% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages DESCRIPTION The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/ AND gate with both true and complementary outputs, designed for use in high-performance ECL systems. The inputs on this device have 75K pull-down resistors. PIN CONFIGURATIONS D5a D4a VEES D1b D3a D2a D1a 4 3 2 1 28 27 26 11 10 9 8 7 6 5 D2b D3b VEE VEES D4b D1c D2c 12 13 14 15 16 17 18 O O VCCA VCC VCC D2e D1e Top View PLCC J28-1 BLOCK DIAGRAM D1a D2a D3a D4a D5a D1b D2b D3b D4b D1c D2c D3c D4c D1d D2d D3d D4d D1e D2e 19 20 21 22 23 24 25 D3c D4c D1d VEES D2d D3d D4d D1c D4b VEE D2c D3b D3c D4c D1d D2d D3d D4d 1 2 3 4 5 6 24 23 22 21 20 19 18 Top View Flatpack F24-1 17 16 15 14 D2b D1b D5a D4a D3a D2a D1a 13 7 8 9 10 11 12 D2e VCC VCCA D1e O O O O PIN NAMES Pin Dna - Dne O-O VEES VCCA Function Data Inputs (n = 1...5) Data Outputs VEE Substrate VCCO for ECL Outputs Rev.: G Amendment: /0 1 Issue Date: July, 1999 Micrel SY100S318 LOGIC EQUATION O = (D1a + D2a + D3a + D4a + D5a) (D1b + D2b + D3b + D4b) (D1c + D2c + D3c + D4c) (D1d + D2d + D3d + D4d) (D1e + D2e) DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current, All Inputs Power Supply Current Min. -- -55 Typ. -- -41 Max. 200 -25 Unit A mA Condition VIN = VIH (Max.) Inputs Open AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tTLH tTHL Parameter Propagation Delay Data to Output Transition Time 20% to 80%, 80% to 20% Min. 300 200 Max. 900 900 TA = +25C Min. 300 200 Max. 900 900 TA = +85C Min. 300 200 Max. 900 900 Unit ps ps Condition PLCC VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tTLH tTHL Parameter Propagation Delay Data to Output Transition Time 20% to 80%, 80% to 20% Min. 300 200 Max. 800 900 TA = +25C Min. 300 200 Max. 800 900 TA = +85C Min. 300 200 Max. 800 900 Unit ps ps Condition 2 Micrel SY100S318 TIMING DIAGRAM 0.7 0.1 ns INPUT 0.7 0.1 ns -0.95V 80% 50% 20% -1.69V TRUE tPHL tPLH 50% OUTPUT tPLH tPHL 80% 50% 20% tTLH tTHL COMPLEMENT Propagation Delay and Transition Times NOTE: VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND PRODUCT ORDERING CODE Ordering Code SY100S318FC SY100S318JC SY100S318JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial 3 Micrel SY100S318 24 LEAD CERPACK (F24-1) Rev. 03 4 Micrel SY100S318 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 5 |
Price & Availability of SY100S318FC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |