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| QL4058 QuickRAM Data Sheet * * * * * * 58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights High Performance & High Density * 58,000 Usable PLD Gates with 252 I/Os * 300 MHz 16-bit Counters, 400 MHz Advanced I/O Capabilities * Interfaces with both 3.3 V and 5.0 V devices * PCI compliant with 3.3 V and 5.0 V busses Datapaths, 160+ MHz FIFOs * 0.35 m four-layer metal non-volatile CMOS process for smallest die sizes for -1/-2/-3/-4 speed grades * Full JTAG boundary scan * I/O Cells with individually controlled Registered Input Path and Output Enables High Speed Embedded SRAM * 18 dual-port RAM modules, organized in user-configurable 1,152 bit blocks * 5 ns access times, each port independently accessible * Fast and efficient for FIFO, RAM, and ROM functions 18 RAM Blocks 1,008 High Speed Logic Cells Easy to Use / Fast Development Cycles * 100% routable with 100% utilization and Interface complete pin-out stability * Variable-grain logic cells provide high performance and 100% utilization * Comprehensive design tools include high quality Verilog/VHDL synthesis Figure 1: QuickRAM Block Diagram (c) 2002 QuickLogic Corporation www.quicklogic.com * * * * * * 1 QL4058 QuickRAM Data Sheet Rev H Architecture Overview The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with Dual-Port SRAM modules. The QL4058 is a 58,000 usable PLD gate member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35 m four-layer metal process using QuickLogic's patented ViaLinkTM technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL4058 contains 1,008 logic cells and 18 Dual Port RAM modules (see Figure 1). Each RAM module has 1,152 RAM bits, for a total of 20,736 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x 18 (wide), 128 x 9, 256 x 4, or 512 x 2 (see Figure 4). With a maximum of 252 I/Os, the QL4058 is available in 208-PQFP, 240-pin PQFP, and 456-pin PBGA packages. Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see Figure 2). This approach allows up to 512-deep configurations as large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device. Software support for the complete QuickRAM family, including the QL4058, is available through two basic packages. The turnkey QuickWorksTM package provides the most complete ESP software solution from design entry to logic synthesis, to place and route, to simulation. The QuickTools package provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for design entry, synthesis, or simulation. The QuickLogicTM variable grain logic cell features up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM Module (1,152 bits) WDATA RDATA Figure 2: QuickRAM Module Bits 2 * * * www.quicklogic.com * * * (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H Product Summary Total of 252 I/O Pins * 244 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades * 8 high-drive input/distributed network pins Eight Low-Skew Distributed Networks * Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs--each driven by an input-only pin * Six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control--each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback High Performance Silicon * Input + logic cell + output total delays = under 6 ns * Data path speeds over 400 MHz * Counter speeds over 300 MHz * FIFO speeds over 160+ MHz (c) 2002 QuickLogic Corporation www.quicklogic.com * * * * * * 3 QL4058 QuickRAM Data Sheet Rev H 4 * * * www.quicklogic.com * * * (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H Electrical Specifications AC Characteristics at VCC = 3.3 V, TA = 25C (K = 1.00) To calculate delays, multiply the appropriate K factor from Table 10: Operating Range by the following numbers in the tables provided. QS A1 A2 A3 A4 A5 A6 QS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 QC QR AZ OZ QZ NZ FZ Figure 3: QuickRAM Logic Cell Table 1: Logic Cell Symbol Parameter 1 tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delaya Setup Time Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width a Propagation Delays (ns) Fanout (5) 2 1.7 1.7 0.0 1.0 1.2 1.2 1.3 1.1 1.9 1.8 3 1.9 1.7 0.0 1.2 1.2 1.2 1.5 1.3 1.9 1.8 4 2.2 1.7 0.0 1.5 1.2 1.2 1.8 1.6 1.9 1.8 5 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. (c) 2002 QuickLogic Corporation www.quicklogic.com * * * * * * 5 QL4058 QuickRAM Data Sheet Rev H [8:0] [17:0] WA WD WE WCLK RE RCLK RA RD ASYNCRD [8:0] [17:0] [1:0] MODE Figure 4: QuickRAM Module Table 2: RAM Cell Synchronous Write Timing Symbol Parameter 1 tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA) a Propagation Delays (ns) Fanout 2 1.0 0.0 1.0 0.0 1.0 0.0 5.3 3 1.0 0.0 1.0 0.0 1.0 0.0 5.6 4 1.0 0.0 1.0 0.0 1.0 0.0 5.9 5 1.0 0.0 1.0 0.0 1.0 0.0 7.1 1.0 0.0 1.0 0.0 1.0 0.0 5.0 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. Table 3: RAM Cell Synchronous Read Timing Symbol Logic Cells tSRA tHRA tSRE tHRE tRCRD RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RDa Parameter 1 1.0 0.0 1.0 0.0 4.0 Propagation Delays (ns) Fanout 2 1.0 0.0 1.0 0.0 4.3 3 1.0 0.0 1.0 0.0 4.6 4 1.0 0.0 1.0 0.0 4.9 5 1.0 0.0 1.0 0.0 6.1 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. * * * www.quicklogic.com * * * 6 (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H Table 4: RAM Cell Asynchronous Read Timing Symbol Parameter 1 RPDRD RA to RDa 3.0 Propagation Delays (ns) Fanout 2 3.3 3 3.6 4 3.9 5 5.1 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. Table 5: Input-Only / Clock Cells Symbol Parameter 1 tIN tINI tISU tIH tICLK tIRST tIESU tIEH High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time Propagation Delays (ns) Fanout 2 3 4 8 12 24 1.5 1.6 1.8 1.9 2.4 2.9 4.4 1.6 1.7 .19 2.0 2.5 3.0 4.5 3.1 3.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.7 0.8 1.0 1.1 1.6 2.1 3.6 0.6 0.7 0.9 1.0 1.5 2.0 3.5 2.3 2.3 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Table 6: Clock Cells Symbol Parameter 1 tACK tGCKP tGCKB Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Fanouta 2 3 4 8 10 11 1.2 1.2 1.3 1.3 1.5 1.6 1.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.8 0.8 0.9 0.9 1.1 1.2 1.3 a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to eight loads per half column. The global clock has up to 11 loads per half column. (c) 2002 QuickLogic Corporation www.quicklogic.com * * * * * * 7 QL4058 QuickRAM Data Sheet Rev H Table 7: I/O Cell Input Delays Symbol Parameter 1 tI/O tISU tIH tIOCLK tIORST tIESU tIEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock to Q Input Register Reset Delay Input Register Clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.3 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanouta 2 1.6 3.1 0.0 1.0 0.9 2.3 0.0 3 1.8 3.1 0.0 1.2 1.1 2.3 0.0 4 2.1 3.1 0.0 1.5 1.4 2.3 0.0 8 3.1 3.1 0.0 2.5 2.4 2.3 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. Table 8: I/O Cell Output Delays Symbol Parameter 3 tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state a Propagation Delays (ns) Output Load Capacitance (pF) 50 2.5 2.6 1.7 2.0 75 3.1 3.2 2.2 2.6 100 3.6 3.7 2.8 3.1 150 4.7 4.8 3.9 4.2 - 2.1 2.2 1.2 1.6 2.0 1.2 Output Delay High to Tri-statea a. These loads are used for tPXZ (see Figure 5) tPHZ 1 5 pF 1 tPLZ 5 pF Figure 5: Loads used for tPXZ 8 * * * www.quicklogic.com * * * (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H DC Characteristics The DC specifications are provided in the tables below. Table 9: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity Value -0.5 V to 4.6 V -0.5 V to 7.0 V -0.5 V to VCCIO +0.5 V 200 mA Parameter DC Input Current ESD Pad Protection Storage Temperature Lead Temperature Value 20 mA 2000 V -65C to +150C 300C Table 10: Operating Range Symbol Parameter Military Min VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade -1 Speed Grade K Delay Factor -2 Speed Grade -3 Speed Grade -4 Speed Grade 3.0 3.0 -55 0.42 0.42 0.42 Max 3.6 5.5 125 2.03 1.64 1.37 Industrial Min 3.0 3.0 -40 0.43 0.43 0.43 0.43 0.43 Max 3.6 5.5 85 1.90 1.54 1.28 0.90 0.82 Commercial Min 3.0 3.0 0 0.46 0.46 0.46 0.46 0.46 Max 3.6 5.25 70 1.85 1.50 1.25 0.88 0.80 V V C C n/a n/a n/a n/a n/a Unit (c) 2002 QuickLogic Corporation www.quicklogic.com * * * * * * 9 QL4058 QuickRAM Data Sheet Rev H Table 11: DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOH = -12 mA IOH = -500 A IOL = 16 mAa IOL = 1.5 mA VI = VCCIO or GND VI = VCCIO or GND -10 -10 Conditions Min 0.5 VCC -0.5 2.4 0.9VCC 0.45 0.1 VCC 10 10 10 VO = GND VO = VCC VI, VIO = VCCIO or GND -15 40 0.50 (typ) 0 -180 210 2 100 Max VCCIO + 0.5 0.3 VCC Units V V V V V V A A pF mA mA mA A VOL II IOZ CI IOS ICC ICCIO Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitanceb Output Short Circuit Currentc D.C. Supply Current d D.C. Supply Current on VCCIO a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. b. Capacitance is sample tested only. Clock pins are 12 pF maximum. c. Only one output at a time. Duration should not exceed 30 seconds. d. For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer applications group (see Contact Information) 10 * * * www.quicklogic.com * * * (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H Kv and Kt Graphs Voltage Factor vs. Supply Voltage 1.1000 1.0800 1.0600 1.0400 Kv 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) Figure 6: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80 Kt Junction Temperature C Figure 7: Temperature Factor vs. Operating Temperature (c) 2002 QuickLogic Corporation www.quicklogic.com * 11 * * * * * QL4058 QuickRAM Data Sheet Rev H Power-up Sequencing VCCIO Voltage VCC (VCCIO -VCC)MAX VCC 400 us Time Figure 8: Power-up Requirements The following requirements must be met when powering up the device (see Figure 8): this recommendation can cause permanent damage to the device. * VCCIO must lead VCC when ramping the device. * The power supply must take greater than or equal to 400 s to reach VCC. Ramping to VCC/VCCIO earlier than 400 s can cause the device to behave improperly. An internal diode is present in-between VCC and VCCIO, as shown in Figure 9. V CC V CCIO * When ramping up the power supplies keep (VCCIO -VCC)MAX 500 mV. Deviation from Internal Logic Cells, RAM blocks, etc IO Cells Figure 9: Internal Diode Between VCC and VCCIO 12 * * * www.quicklogic.com * * * (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H JTAG TCK TMS TRSTB TAp Controller State Machine (16 States) Instruction Decode & Control Logic Instruction Register RDI Mux Boundary-Scan Register (Data Register) Mux TDO Bypass Register Internal Register I/O Registers User Defined Data Register Figure 10: JTAG Block Diagram Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges. One of these challenges concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. (c) 2002 QuickLogic Corporation www.quicklogic.com * 13 * * * * * QL4058 QuickRAM Data Sheet Rev H The JTAG 1149.1 standard requires the following three tests: * Extest Instruction. The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. * Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register connects the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. 14 * * * www.quicklogic.com * * * (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H Pin Descriptions Table 12: Pin Descriptions Pin TDI/RSI Function Test Data In for JTAG /RAM init. Serial Data In Active low Reset for JTAG /RAM init. reset out Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG /RAM init. clock out Special Test Mode High-drive input and/or array network driver Description Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization. Must be grounded during normal operation. Can be configured as either or both. TRSTB/RRO TMS TCK TDO/RCO STM I/ACLK I/GCLK I I/O VCC VCCIO GND High-drive input and/or global Can be configured as either or both. network driver High-drive input Input/Output pin Power supply pin Input voltage tolerance pin Ground pin Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3 V supply. Connect to 5.0 V supply if 5 V input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground. Available on 456-PBGA only. Connect to ground plane on PCB if heat sinking desired. Otherwise may be left unconnected. GND/THERM Ground/Thermal pin Ordering Information QL 4058 - 1 PQ208 C QuickLogic device QuickRAM device part number Speed Grade 0 = Quick 1 = Fast 2 = Faster 3 = Faster *4 = Wow Operating Range C = Commercial I = Industrial M = Military Package Code PQ208 = 208-pin PQFP PQ240 = 240-pin PQFP PB456 = 456-pin PBGA * Contact QuickLogic regarding availabliity (c) 2002 QuickLogic Corporation www.quicklogic.com * 15 * * * * * QL4058 QuickRAM Data Sheet Rev H 208 and 240 PQFP Pinout Diagrams Pin 1 Pin 157 QuickRAM QL4058-1PQ208C Pin 53 Pin 105 Figure 11: Top View of 208 Pin PQFP Pin 1 Pin 181 QuickRAM QL4058-1PQ240C Pin 61 Pin 121 Figure 12: Top View of 240 Pin PQFP 16 * * * www.quicklogic.com * * * (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H 208 and 240 PQFP Pinout Table Table 13: 208/240 PQFP Pinout Table 240 PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 208 PQFP 208 1 2 3 4 5 NC 6 7 8 9 10 11 12 13 14 NC 15 16 17 18 19 20 NC 21 22 23 24 25 26 27 28 29 30 31 32 NC 33 NC 34 35 36 NC 37 38 39 NC 40 41 42 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I ACLK/I VCC GCLK/I GCLK/I VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O 240 PQFP 51 52 53 54 55 56 57 58 59 60 NC NC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC 84 85 86 87 88 89 90 91 92 93 94 95 96 97 208 PQFP 43 44 45 46 47 48 NC 49 50 51 52 53 54 NC NC 55 56 NC 57 58 59 60 61 62 63 64 NC 65 66 67 NC 68 69 70 NC 71 NC 72 73 74 NC 75 76 77 78 79 80 81 82 83 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O GND I/O I/O I/O I/O VCCIO 240 PQFP 98 99 100 101 102 103 104 105 106 107 108 109 110 NC 111 NC NC 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 208 PQFP 84 85 86 87 88 89 90 91 92 NC 93 94 95 96 97 98 99 100 NC 101 NC 102 NC NC 103 104 105 NC 106 107 108 109 NC 110 111 112 113 114 115 116 117 NC 118 119 120 121 NC 122 123 124 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 240 PQFP 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 NC 181 182 183 184 185 186 187 188 189 190 191 192 193 208 PQFP 125 126 127 128 NC 129 130 131 132 133 134 135 136 NC 137 NC 138 139 140 141 142 NC 143 144 145 NC 146 147 148 149 150 151 152 153 154 155 156 157 158 NC 159 160 161 162 163 164 165 166 NC 167 Function I/O I/O GND I/O I/O GLCK/I ACLK/I VCC GLCK/I GLCK/I VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O 240 PQFP 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 208 PQFP 168 169 NC 170 171 172 173 174 175 NC 176 177 178 179 NC 180 181 182 NC 183 184 185 186 187 188 NC 189 190 191 192 193 194 NC 195 196 197 198 NC 199 200 201 202 203 204 205 206 207 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO (c) 2002 QuickLogic Corporation www.quicklogic.com * 17 * * * * * QL4058 QuickRAM Data Sheet Rev H 208 and 240 PQFP Mechanical Drawing Figure 13: 208 PQFP Mechanical Drawing * * * www.quicklogic.com * * * 18 (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H 456 PBGA Pinout Diagram TOP View QuickRAM QL4058-1PB456C BOTTOM View 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF PIN A1 CORNER Figure 14: 456 PBGA Pinout Diagram (c) 2002 QuickLogic Corporation www.quicklogic.com * 19 * * * * * QL4058 QuickRAM Data Sheet Rev H 456 PBGA Pinout Table Table 14: 456 PBGA Pinout Table 456 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 Function I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O VCCIO I/O I/O NC I/O NC I/O I/O I/O NC I/O NC I/O I/O I/O I/O NC I/O NC NC NC NC NC I/O NC NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O STM 456 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 Function I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O TCK NC I/O I/O I/O GND NC NC I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O GND I/O NC NC I/O GND I/O I/O I/O 456 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 Function I/O I/O I/O I/O GND VCC GND NC GND I/O GND GND VCC GND GND GND NC GND NC GND VCC GND I/O I/O I/O I/O I/O I/O NC NC VCC VCC NC I/O I/O I/O I/O I/O I/O I/O NC GND NC I/O I/O I/O NC I/O NC I/O NC NC 456 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 Function NC I/O NC I/O I/O I/O I/O NC GND NC NC I/O I/O I/O NC NC I/O I/O VCC GND I/O I/O NC I/O I/O I/O I/O I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC I/O I/O NC I/O ACLK / I GCLK/I I/O NC GND GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC 456 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 Function NC I/O I/O I/O GCLK/I I/O I/O GCLK/I VCC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND I/O I/O NC I/O I/O I/O NC I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC GCLK / I GCLK / I NC ACLK / I NC I/O I/O NC NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM VCC NC NC I/O GCLK / I (Sheet 1 of 2) 20 * * * www.quicklogic.com * * * (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H Table 14: 456 PBGA Pinout Table (Continued) 456 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 Function I/O I/O I/O I/O VCC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND I/O I/O NC I/O NC I/O I/O I/O GND NC I/O I/O I/O I/O I/O I/O NC NC NC GND NC I/O NC I/O I/O I/O I/O I/O 456 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 Function NC NC I/O I/O I/O NC NC I/O NC I/O I/O GND I/O NC I/O I/O I/O I/O NC NC VCC VCC NC I/O I/O I/O NC I/O I/O I/O GND VCC NC NC NC VCC GND NC I/O GND 456 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 Function VCC I/O NC VCC GND NC VCC GND I/O NC I/O I/O I/O I/O NC GND NC NC NC NC NC NC I/O NC I/O VCCIO NC NC NC NC I/O I/O I/O NC GND NC I/O I/O I/O NC 456 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 Function I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O TRSTB NC I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 456 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Function I/O I/O I/O I/O I/O NC NC TMS I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O NC I/O I/O NC NC I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O (Sheet 2 of 2) (c) 2002 QuickLogic Corporation www.quicklogic.com * 21 * * * * * QL4058 QuickRAM Data Sheet Rev H 456 PBGA Mechanical Drawing Figure 15: 456 PBGA Mechanical Drawing 22 * * * www.quicklogic.com * * * (c) 2002 QuickLogic Corporation QL4058 QuickRAM Data Sheet Rev H Contact Information Telephone:408 990 4000 (US) 416 497 8884 (Canada) 44 1932 57 9011 (Europe) 49 89 930 86 170 (Germany) 852 8106 9091 (Asia) 81 45 470 5525 (Japan) E-mail: info@quicklogic.com Support:support@quicklogic.com Web site:http://www.quicklogic.com/ Revision History Table 15: Revision History Revision A B C D E F G H Date not avail. not avail. not avail. not avail. not avail. not avail. May 2000 May 2002 Update of AC/DC Specs and reformat Added Kfactor, Power-up, JTAG and mechanical drawing information. Reformatted. Comments First release. Copyright Information Copyright (c) 2002 QuickLogic Corporation. All Rights Reserved. The information contained in this product brief, and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic, pASIC, and ViaLink are registered trademarks, and SpDE and QuickWorks are trademarks of QuickLogic Corporation. Verilog is a registered trademark of Cadence Design Systems, Inc. * * * * (c) 2002 QuickLogic Corporation www.quicklogic.com * 23 * |
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