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NCV7382 Advance Information Enhanced LIN Transceiver
The NCV7382 is a physical layer device for a single wire data link capable of operating in applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor which uses the network. The NCV7382 is designed to work in systems developed for LIN 1.3 or LIN 2.0. The IC furthermore can be used in ISO9141 systems. Because of the very low current consumption of the NCV7382 in the sleep mode it's suitable for ECU applications with low standby current requirements. This mode allows a shutdown of the whole application. The included wake-up function detects incoming dominant bus messages and enables the voltage regulator.
Features http://onsemi.com MARKING DIAGRAM
8 8 1 SO-8 D SUFFIX CASE 751 1 A L Y W = Assembly Location = Wafer Lot = Year = Work Week V7382 ALYW
* Operating Voltage VS = 6.0 to 18 V * Very Low Standby Current Consumption of Typ. 6.5 mA in Sleep *
Mode LIN-Bus Transceiver: Slew Rate Control for Good EMC Behavior Fully Integrated Receiver Filter BUS Input Voltage -27 V to 40 V Integrated Termination Resistor for LIN Slave Nodes (30 kW) Wake-Up Via LIN Bus Baud Rate up to 20 kBaud Will Work in Systems Designed for Either LIN 1.3 or LIN 2.0 Compatible to ISO9141 Functions High EMI Immunity Bus Terminals Protect Against Short-Circuits and Transients in the Automotive Environment High Impedance Bus Pin for Loss of Ground and Undervoltage Condition Thermal Overload Protection High Signal Symmetry for use in RC-Based Slave Nodes up to 2% Clock Tolerance when Compared to the Master Node "4.0 kV ESD Protection on BUS, VS and INH Pins Control Output for Voltage Regulator with Low On-Resistance for Switchable Master Termination NCV Prefix for Automotive and Other Applications Requiring Site and Change Control
PIN CONNECTIONS
RxD 1 EN 2 VCC 3 TxD 4 (Top View) 8 7 6 5 INH VS BUS GND
* * * * * * * * *
ORDERING INFORMATION
Device NCV7382D NCV7382DR2 Package SO-8 SO-8 Shipping 95 Units/Rail 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) Semiconductor Components Industries, LLC, 2004
1
May, 2004 - Rev. P1
Publication Order Number: NCV7382/D
NCV7382
NCV7382
INH VS
Internal Supply and References
Biasing & Bandgap
Thermal Shutdown
VCC
POR 30 K
SLEW RATE CONTROL TxD
BUS Driver BUS
GND EN MODE CONTROL Wake-Up Filter
RxD Receive Comparator Input Filter
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 Symbol RXD EN VCC TXD GND BUS VS INH Description Receive data from BUS to microprocessor, LOW in dominant state. Enables the normal operation mode when HIGH. 5.0 V supply input. Transmit data from microprocessor to BUS, LOW in dominant state. Ground LIN bus pin, LOW in dominant state. Battery input voltage. Control output for voltage regulator, termination pin for master pull up.
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NCV7382
Electrical Specification All voltages are referenced to ground (GND). Positive currents flow into the IC. The maximum ratings (in accordance with IEC 134) given in the table below are limiting values that do not lead
OPERATING CONDITIONS
Characteristic Battery Supply Voltage (Note 1) Supply Voltage Operating Ambient Temperature Symbol VS VCC TA Min 6.0 4.5 -40 Max 18 5.5 +125 Unit V V C
to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may effect the reliability of the device.
MAXIMUM RATINGS
Rating Battery Supply Voltage Symbol VS t < 1 min Load Dump, t < 500 ms Supply Voltage Transient Supply Voltage Transient Supply Voltage Transient Supply Voltage BUS Voltage VCC VS.tr1 VS..tr2 VS..tr3 VBUS - ISO 7637/1 Pulse 1 (Note 2) ISO 7637/1 Pulses 2 (Note 2) ISO 7637/1 Pulses 3A, 3B t < 500 ms , Vs = 18 V t < 500 ms ,Vs = 0 V Transient Bus Voltage Transient Bus Voltage Transient Bus Voltage DC Voltage on Pins TxD, RxD ESD Capability of BUS, VS & INH Pins ESD Capability of RxD, TxD & Vcc Pins Maximum Latch - Up Free Current at Any Pin Maximum Power Dissipation Thermal Impedance Storage Temperature Junction Temperature Lead Temperature Soldering Reflow: (SMD styles only) VBUS..tr1 VBUS.tr2 VBUS.tr3 VDC ESDHB ESDHB ILATCH Ptot qJA Tstg TJ Tsld ISO 7637/1 Pulse 1 (Note 3) ISO 7637/1 Pulses 2 (Note 3) ISO 7637/1 Pulses 3A, 3B (Note 3) - Human body model, equivalent to discharge 100 pF with 1.5 kW Human body model, equivalent to discharge 100 pF with 1.5 kW - At TA = 125C In Free Air - - 60 second maximum above 183C -5C/+0C allowable conditions -0.3 03 -0.3 -150 - -150 -27 -40 -150 - -150 -0.3 -4.0 -2.0 -500 - - -55 -40 - 40 - 100 150 7.0 4.0 2.0 500 197 152 +150 +150 240 peak V V V V kV kV mA mW C/W C C C Condition Min Max 30 40 +7.0 - 100 150 V V V V V Unit V
1. VS is the IC supply voltage including voltage drop of reverse battery protection diode, VDROP = 0.4 to 1.0 V, VBAT_ECU voltage range is 7.0 to 18 V. 2. ISO 7637 test pulses are applied to VS via a reverse polarity diode and > 2.0 mF blocking capacitor. 3. ISO 7637 test pulses are applied to BUS via a coupling capacitance of 1.0 nF.
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ELECTRICAL CHARACTERISTICS (VS = 6.0 to 18 V, VCC = 4.5 to 5.5 V and TA = -40 to 125C unless otherwise noted.)
Characteristic GENERAL VCC Undervoltage Lockout Supply Current, Dominant Supply Current, Dominant Supply Current, Recessive Supply Current, Recessive Supply Current, Sleep Mode Supply Current, Sleep Mode Thermal Shutdown Thermal Recovery BUS TRANSMIT Short Circuit Bus Current Pull Up Current Bus Pull Up Current Bus Bus Reverse Current, Recessive Bus Reverse Current Loss of Battery Bus Current During Loss of Ground Transmitter Dominant Voltage Transmitter Dominant Voltage Transmitter Dominant Voltage Bus Input Capacitance BUS RECEIVE Receiver Dominant Voltage Receiver Recessive Voltage Center Point of Receiver Threshold Receiver Hysteresis VBUSdom (Notes 5 and 6) VBUSrec (Notes 5 and 6) VBUS_CNT (Notes 4, 5 & 6) VHYS (Notes 4, 5 & 6) - - VBUS_CNT = (VBUSdom + VBUSrec)/2 VBUS_CNTt = (VBUSrec - VBUSdom) 0.4 *VS - 0.487 *VS - - - 0.5 *VS 0.16 *VS - 0.6 *VS 0.512 *VS
-
Symbol
Condition
Min
Typ
Max
Unit
VCC_UV ISd ICCd ISr ICCr ISsl ISsl Tsd (Note 4) Thys (Note 4)
EN = H, TxD = L VS = 18 V, VCC = 5.5 V, TxD = L VS = 18 V, VCC = 5.5 V, TxD = L VS = 18 V, VCC = 5.5 V TxD = H VS = 18 V, VCC = 5.5 V TxD = H VS = 12 V, VCC and TxD = 0 V, TA = 25_ VS = 12 V, VCC and TxD = 0 V - -
2.75 - - - - - - 155 126
- 0.9 0.6 25 50 6.5 6.5 - -
4.3 2.0 2.0 50 75 - 14 180 150
V mA mA mA mA mA mA C C
IBUS_LIM (Notes 5 and 6) IBUS_PU (Notes 5 and 6) IBUS_PU_SLEEP IBUS_PAS_rec (Notes 5 and 6) IBUS (Notes 5 and 6) IBUS_NO_GND (Notes 5 and 6) VBUSdom_DRV_1 VBUSdom_DRV_2 (Note 5) VBUSdom_DRV_3 (Note 5) CBUS (Note 4)
VBUS = VS, Driver On VBUS = 0, VS = 12 V, Driver Off VBUS = 0, VS = 12 V, Sleep Mode VBUS > VS, 8.0 V < VBUS < 18 V 6.0 V < VS < 18 V, Driver Off VS = 0 V, 0 V < VBUS < 18 V VS = 12 V, 0 < VBUS < 18 V Load = 40 mA VS = 6.0 V, Load = 500 W VS = 18 V, Load = 500 W Pulse Response via 10 kW, VPULSE = 12 V, VS = Open
- -600 -100 - - -1.0 - - - -
120 - -75 - - - - - - 25
200 -200 - 20 100 1.0 1.2 1.2 2.0 35
mA mA mA mA mA mA V V V pF
V V V V
4. No production test, guaranteed by design and qualification. 5. In accordance to LIN physical layer specification 1.3. 6. In accordance to LIN physical layer specification 2.0.
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NCV7382
ELECTRICAL CHARACTERISTICS (VS = 6.0 to 18 V, VCC = 4.5 to 5.5 V and TA = -40 to 125C unless otherwise noted.)
Characteristic TXD, EN High Level Input Voltage Low Level Input Voltage TxD Pull Up Resistor EN Pull Down Resistor RXD Low Level Output Voltage Leakage Current INH On Resistance Leakage Current Ron_INH IINH_lk Normal or Standby Mode, VINH = VS - 1.0 V, VS = 12 V EN = L, VINH = 0 V - -5.0 20 - 50 5.0 W mA Vol_rxd Vleak_rxd IRxD = 2.0 mA VRxD = 5.5 V, Recessive - -1.0 - - 0.9 1.0 V mA Vih Vil RIH_TXD RIL_EN Rising Edge Falling Edge VTxD = 0 V VEN = 5.0 V - 0.3*VCC 10 20 - - 15 30 0.7*VCC - 20 40 V V kW kW Symbol Condition Min Typ Max Unit
AC CHARACTERISTICS
Characteristic Propagation Delay Transmitter (Notes 7 and 9) Propagation Delay Transmitter Symmetry (Notes 8 and 9) Propagation Delay Receiver (Notes 7, 9, 12, 13 and 14) Propagation Delay Receiver Symmetry (Notes 9, 11 and 12) Slew Rate Rising and Falling Edge, High Battery (Notes 8, 11 and 12) Slew Rate Rising and Falling Edge, Low Battery (Notes 8, 11 and 12) Slope Symmetry, High Battery (Notes 11 and 12) Symbol ttrans_pdf ttrans_pdr ttrans_sym trec_pdf trec_pdr trec_sym |tSR_HB| Condition Bus Loads: 1.0 KW/1.0 nF, 660 W/6.8 nF, 500 W/10 nF Calculate ttrans_pdf - ttrans_pdr CRxD = 20 pF Calculate ttrans_pdf - ttrans_pdr Bus Loads: VS = 18 V, 1.0 KW/1.0 nF, 660 W/6.8 nF, 500 W/10 nF Bus Loads: VS = 7.0 V, 1.0 KW/1.0 nF, 660 W/6.8 nF, 500 W/10 nF Bus Loads: VS = 18 V, 1.0 KW/1.0 nF, 660 W/6.8 nF, 500 W/10 nF, Calculate tsdom - tsrec Calculate tBUS_rec(min)/100 ms Calculate tBUS_rec(max)/100 ms BUS Rising and Falling Edge Sleep Mode, BUS Rising & Falling Edge Normal -> Sleep Mode Transition Min - -2.0 - -1.5 1.0 Typ - - - - 2.0 Max 5.0 2.0 6.0 1.5 3.0 Unit ms ms ms ms V/ms
|tSR_LB|
0.5
2.0
3.0
V/ms
tssym_HB
-5.0
-
+5.0
ms
Bus Duty Cycle (Note 13) Receiver Debounce Time (Notes 8, 11 and 14) Wake-Up Filter Time EN - Debounce Time
D1 D2 trec_deb twu ten_deb
0.396 - 1.5 30 10
- - - - 20
- 0.581 4.0 150 40
ms/ms ms/ms ms ms ms
7. Propagation delays are not relevant for LIN protocol transmission, value only information parameter. 8. No production test, guaranteed by design and qualification. 9. See Figure 2 - Input/Output Timing. 10. See Figure 8 - Slope Time Calculation. 11. See Figure 3 - Receiver Debouncing. 12. In accordance to LIN physical layer specification 1.3. 13. In accordance to LIN physical layer specification 2.0. 14. This parameter is tested by applying a square wave to the bus. The minimum slew rate for the bus rising and falling edges is 50 V/ms.
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TIMING DIAGRAMS
TxD
50%
ttrans_pdf VBUS 95% 100%
ttrans_pdr
BUS
50%
50%
5% 0% trec_pdf RxD 50% trec_pdr
Figure 2. Input/Output Timing
t < trec_deb VBUS
t < trec_deb
60% 40%
t
VRxD 50%
t
Figure 3. Receiver Debouncing
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VBUS
t
t > twu VINH
twu
t
VCC
t
VEN
t
VRxD
wakeup interrupt
t
Figure 4. Sleep Mode and Wake-Up Procedure
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NCV7382
TEST CIRCUITS FOR DYNAMIC AND STATIC CHARACTERISTICS
NCV7382
VS RL 100 nF VCC 100 nF
BUS CL
EN TxD 2.7 K
INH GND 10 K
RxD 20 pF
Figure 5. Test Circuit for Dynamic Characteristics
NCV7382
100 n VS 500 2 mF + EN BUS 1 nF TxD VCC
GND
RxD
Oscilloscope
Schaffner- Generator Puls3a,3b 12 V Puls1,2,4 + -
Figure 6. Test Circuit for Automotive Transients
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NCV7382
Functional Description
Initialization
After power on, the chip automatically enters the VBAT -standby mode. In this intermediate mode the INH output will become HIGH (VS) and therefore the ECU - voltage regulator will provide the VCC - supply. The transceiver will remain in the VBAT standby mode until the controller sets it to normal operation (EN = High). Bus communication is only possible in normal mode. The NCV7382 switches itself to the VBAT standby mode if VCC is missing or below the undervoltage lockout threshold.
Operating Modes
The EN pin is used to switch the NCV7382 into different operating modes.
Normal Mode
because the transceiver and the external voltage regulator are disabled. If VCC has been switched off, a wake-up request from the bus line (remote wake-up) will cause the NCV7382 to enter the VBAT-standby mode (VCC is present again) and sets the RxD output to low until the device enters the normal operation mode (active LOW interrupt at RxD). If the INH pin is not connected to the regulator or the inhibitable external regulator is not the one that provides the VCC - supply, the normal mode is directly accessible by logic high on the EN pin. (Wake-up via mode change/local wake-up.) In order to prevent an unintended wake-up caused by disturbances in the automotive environment, incoming dominant signals from the bus have to exceed the wake-up delay time.
Thermal Shutdown Mode
All of the NCV7382 is active. Switching to normal mode can only be done with EN = high.
Sleep Mode
The sleep mode (EN = LOW) can only be reached from normal mode and permits a very low power consumption
Table 1. Mode Control
EN 0 0 1 0 0 VCC 0 1 1 0 1 Comment VBAT-Standby, Power On VBAT-Standby, VCC On Normal Mode Sleep Mode
If the junction temperature TJ is higher than 155C, the NCV7382 could be switched into the thermal shutdown mode. Transmitter will be switched off. If TJ falls below the thermal shutdown temperature (typ. 140C), the NCV7382 will be switched to the previous state.
INH Vs Vs Vs Floating Floating
RxD 0 X VCC = Recessive 0 = Dominant 0 VCC
Sleep Mode Regulator not disabled Directly switch to normal mode with EN = 1 Remote wake-up request
0
0/1
Vs
0 - Active low wake-up interrupt
LIN BUS Transceiver
TxD Input
The transceiver consists of a bus-driver (1.2 V @ 40 mA) with slew rate control, current limit, and a receiver with a high voltage comparator with filter circuitry.
BUS Input/Output
The recessive BUS level is generated from the integrated 30 k pull up resistor in series with a diode. The diode prevents the reverse current on VBUS when VBUS > VS. No additional termination resistor is necessary to use the NCV7382 on LIN slave nodes. If this IC is used for LIN master nodes, it is necessary to terminate the bus with an external 1.0 kW resistor in series with a diode to VBAT or INH (See chapter Short Circuit to Ground).
During transmission the signal on TxD will be transferred to the BUS driver for generating a BUS signal. To minimize the electromagnetic emission of the bus line, the BUS driver has integrated slew rate control and wave shaping. Transmitting will be interrupted in the following cases: * Sleep Mode * Thermal Shutdown * VBAT Standby The CMOS compatible input TxD directly controls the BUS level: TxD = low BUS = low (dominant level) TxD = high BUS = high (recessive level)
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NCV7382
The TxD pin has an internal pull up resistor connected to VCC. This secures that an open TxD pin generates a recessive BUS level.
RxD Output
The signal on the BUS pin will be transferred continuously to the RxD pin. Short spikes on the bus signal are filtered with internal circuitry (Figure 3 and Figure 7).
VS VBUS_CNT_max 60% BUS 50% 40% VBUS_CNT_min VhHYS
t
t < trec_deb t < trec_deb
RxD
t
Figure 7. Receive Impulse Diagram
The receive threshold values VBUS_CNT_max and VBUS_CNT_min are symmetrical to 0.5*VS with a hysteresis of 0.16*VS (typ). The LIN specific receive threshold is between 0.4*VS and 0.6*VS. The received BUS signal will be output to the RxD pin: BUS < VBUS_CNT - 0.5 * VHYS RxD = low (BUS dominant) BUS > VBUS_CNT + 0.5 * VHYS RxD = high, floating (BUS recessive) RxD is a buffered open drain output with a typical load of: Resistance: 2.7 kW Capacitance: < 20 pF
EN-Pin
v DV/DT v 3.0 V/ms. This principle provides very good symmetry of the slope times between recessive to dominant and dominant to recessive slopes within the LIN bus load range (CBUS, Rterm). The NCV7382 guarantees data rates up to 20 kbit within the complete bus load range under worst case conditions. The constant slew rate principle holds appropriate voltage levels and can operate within the LIN Protocol Specification for RC oscillator systems with a matching tolerance up to 2%. Operating Under Disturbance
Loss of Battery
The NCV7382 is switched into sleep mode with a falling edge and into normal mode with a rising edge of the EN pin. It will remain in normal mode as long as EN = high (See Figure 4 - Sleep Mode and Wake-Up Procedure for more details). When the NCV7382 is switched to sleep mode, the voltage regulator on the INH pin is switched off. The NCV7382 can be turned off with EN = low independent of the state of the bus-transceiver. The EN input has an internal pulled down to guarantee a low level with EN floating.
Data Rate
If VS and VCC are disconnected from the battery, the bus pin is in high impedance state. There is no impact to the bus traffic.
Loss of Ground
In case of an interrupted ground connection from VS and VCC, there is no influence to the bus line.
Short Circuit to Battery
The transmitter output current is limited to 200 mA (max) in case of short circuit to battery.
Short Circuit to Ground
The NCV7382 is a constant slew rate transceiver. The bus driver operates with a fixed slew rate range of 1.0 V/ms
Negative voltages on the BUS pin are limited primarily to current through the internal 30 K resistor and series diode from VS through a switched device controlled by EN. Secondary contributions are attributed to the resistor and diode hardwired from VS to BUS.
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NCV7382
System designs can have an external resistor (1 k) in series with an external diode to the battery, but short circuit current from bus to ground can be reduced dramatically by using the INH pin as termination pin for the master pull up (See Figure 10 - Application Circuitry). With this new setup, the controller can detect a short circuit of the bus to ground (RxD timeout) and the transceiver can be set into sleep mode. The INH pin will be floating in this case, and the external master pull up resistor will be disconnected from the bus line. Additionally, the internal slave termination resistor is switched off and only a high impedance termination is applied to the bus (typ. 75 mA). This will reduce the failure current of the system by at least an order of magnitude, preventing a fast Application Hints
LIN System Parameter Bus Loading Requirements
Parameter Operating Voltage Range Voltage Drop of Reverse Protection Diode Voltage Drop at the Serial Diode in Pull Up Path Battery Shift Voltage Ground Shift Voltage Master Termination Resistor Slave Termination Resistor Number of System Nodes Total Length of Bus Line Line Capacitance Capacitance of Master Node Capacitance of Slave Node Total Capacitance of the Bus including Slave and Master Capacitance Network Total Resistance Time Constant of Overall System Symbol VBAT VDrop_rev VSerDiode VShift_BAT VShift_GND Rmaster Rslave N LENBUS CLINE CMaster CSlave CBUS RNetwork Min 8.0 0.4 0.4 0 0 900 20 2.0 - - - - 1.0 537 1.0 Typ - 0.7 0.7 - - 1000 30 - - 100 220 220 4.0 - - Max 18 1.0 1.0 0.1 0.1 1100 60 16 40 150 - 250 10 863 5.0 Unit V V V VBAT VBAT W kW - m pF/m pF pF nF W ms
discharge of the car battery. If the failure is removed, the bus level will become recessive again and will wake up the system even if no local wake-up is present or possible.
Thermal Overload
The NCV7382 is protected against thermal overloads. If the chip temperature exceeds the thermal shutdown threshold, the transmitter is switched off until thermal recovery. The receiver continues to work during thermal shutdown.
Undervoltage VCC
The VCC undervoltage lockout feature disables the transmitter until it is above the undervoltage lockout threshold to prevent undesirable bus traffic.
Recommendations for System Design
The goal of the LIN physical layer standard is to have a universal definition of the LIN system for plug and play solutions in LIN networks up to 20 kbd bus speeds. In case of small and medium LIN networks, it's recommended to adjust the total network capacitance to at least 4.0 nF for good EMC and EMI behavior. This can be done by setting only the master node capacitance. The slave node capacitance should have a unit load of typically 220 pF for good EMC/EMI behavior. In large networks with long bus lines and the maximum number of nodes, some system parameters can exceed the defined limits and of the LIN system designer must intervene. The whole capacitance of a slave node is not only the unit load capacitor itself. Additionally, there is the capacitance
of wires and connectors, and the internal capacitance of the LIN transmitter. This internal capacitance is strongly dependent on the technology of the IC manufacturer and should be in the range of 30 pF to 150 pF. If the bus lines have a total length of nearly 40m, the total bus capacitance can exceed the LIN system limit of 10 nF. A second parameter of concern is the integrated slave termination resistor tolerance. If most of the slave nodes have a slave termination resistance at the allowed maximum of 60 kW, the total network resistance is more than 700 W. Even if the total network capacitance is below or equal to the maximum specified value of 10 nF, the network time constant is higher than 7.0 ms. This problem can be solved only by adjusting the master termination resistor to the required maximum network time constant of 5.0 ms (max).
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The LIN Bus output driver of the NCV7382 provides a higher drive capability than necessary (40 mA @ 1.2 V) within the LIN standard (33.6 mA @ 1.2 V). With this driver stage the system designer can increase the maximum LIN networks with a total network capacitance of more than 10 nF. The total network resistance can be decreased to:
Rtl_min + (VBat_max * VBUSdom) IBUS_max + (18 V * 1.2 V) 40 mA + 420 W
NOTE: The setting of the network time constant is necessary in large networks (primarily resistance) and also in small networks (primarily capacitance). The NCV7382 meets the requirements for implementation in RC-based slave nodes. The LIN Protocol Specification requires the deviation of the slave node clock to the master node clock after synchronization must not differ by more than "2%.
MIN/MAX SLOPE TIME CALCULATION
(In accordance to the LIN System Parameter Table)
VBUS
100%
60%
60%
40%
40%
0%
Vdom
tsdom
tsrec
Figure 8. Slope Time and Slew Rate Calculation
(In accordance to LIN physical layer specification 1.3)
The slew rate of the bus voltage is measured between 40% and 60% of the output voltage swing (linear region). The output voltage swing is the difference between dominant and recessive bus voltage.
dV dt + 0.2 * Vswing (t40%-t60%)
The slope time of the recessive to dominant edge is directly determined by the slew rate control of the transmitter:
tslope + Vswing dV dt
The slope time is the extension of the slew rate tangent until the upper and lower voltage swing limits:
tslope + 5 * (t40%-t60%)
The dominant to recessive edge is influenced from the network time constant and the slew rate control, because it's a passive edge. In case of low battery voltages and high bus loads the rising edge is only determined by the network. If the rising edge slew rate exceeds the value of the dominant one, the slew rate control determines the rising edge.
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tBit tBit
TxD
tdom(max) VSUP 100%
trec(min)
tdom(min) 58.1% BUS 28.4%
74.4% 42.2% 58.1%
trec(max) GND 0%
28.4%
RxD
Figure 9. Duty Cycle Measurement and Calculation in Accordance to LIN Physical Layer Specification 2.0
Duty Cycle Calculation
With the timing parameters shown in Figure 9 two duty cycles, based on trec(min) and trec(max) can be calculated as follows: D1* = trec(min)/(2 x tBit) D2* = trec(max)/(2 x tBit) For proper operation at 20 KBit/s (bit time is 50 ms) the LIN driver has to fulfill the duty cycles specified in the AC characteristics for supply voltages of 7...18 V and the three defined standard loads. Due to this simple definition there is no need to measure slew rates, slope times, transmitter delays and dominant
voltage levels as specified in the LIN physical layer specification 1.3. The devices within the D1/D2 duty cycle range also operates in applications with reduced bus speed of 10.4 KBit/s or below. In order to minimize EME, the slew rates of the transmitter can be reduced (by up to [ 2 times). Such devices have to fulfill the duty cycle definition D3/D4 in the LIN physical layer specification 2.0. Devices within this duty cycle range cannot operate in higher frequency 20 KBit/s applications.
*D1 and D2 are defined in the LIN protocol specification 2.0.
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NCV7382
Car Battery Ignition
VBAT 1N4001 VIN Voltage Regulator NCV8502 VOUT 10 mF 100 nF 100 nF 2.2 mF
LIN BUS
Slave ECU
10 k
Reset 47 nF
2.7 K
VCC RxD
VS BUS 220 pF ECU Connector to Single Wire LIN Bus ECU Connector to Single Wire LIN Bus
mP
NCV7380* TxD
GND
GND
*The NCV7380 is a pin compatible low cost transceiver without INH control.
1N4001 VBAT VIN Voltage Regulator NCV8501 ENABLE 10 k
2.2 mF 100 nF
Master ECU
VOUT 10 mF
10 k
Reset 47 nF
100 nF
47 nF
2.7 K
VCC INH RxD
VS 1K
mP
NCV7382 BUS TxD EN 220 pF
GND
GND
Figure 10. Application Circuitry
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NCV7382
ESD/EMC Remarks
General Remarks ESD Test
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
The NCV7382 is tested according to MIL883D (human body model).
EMC
The test on EMC impacts is done according to ISO 7637-1 for power supply pins and ISO 7637-3 for data and signal pins.
POWER SUPPLY PIN VS
Test Pulse 1 2 3a/b 5 Condition t1 = 5.0 s/US = -100 V/tD = 2.0 ms t1 = 0.5 s/US = 100 V/tD = 0.05 ms US = -150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break Ri = 0.5 W, tD = 400 ms tr = 0.1 ms/UP + US = 40 V Duration 5000 Pulses 5000 Pulses 1h 10 Pulses Every 1 Min
DATA AND SIGNAL PINS EN, BUS
Test Pulse 1 2 3a/b Condition t1 = 5.0 s/US = -100 V/tD = 2.0 ms t1 = 0.5 s/US = 100 V/tD = 0.05 ms US = -150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break Duration 1000 Pulses 1000 Pulses 1000 Burst
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NCV7382
PACKAGE DIMENSIONS
SO-8 CASE 751-07 ISSUE AB
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060 7.0 0.275 4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCV7382/D

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