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NCN6001 Compact Smart Card Interface IC
The NCN6001 is an integrated circuit dedicated to the smart card interface applications. The device handles any type of smart card through a simple and flexible microcontroller interface. On top of that, thanks to the built-in chip select pin, several couplers can be connected in parallel. The device is particularly suited for low cost, low power applications, with high extended battery life coming from extremely low quiescent current.
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TSSOP-20 DTB SUFFIX CASE 948E 1
* * * * * * * * * * * * * * * * *
100% Compatible with ISO 7816-3, EMV and GIE-CB Standards Fully GSM Compliant Wide Battery Supply Voltage Range: 2.7 < VCC < 5.5 V Programmable CRD_VCC Supply Handles 1.8 V, 3.0 V or 5.0 V Card Operation Programmable Rise and Fall Card Clock Slopes Programmable Card Clock Divider Built-in Chip Select Logic Allows Parallel Coupling Operation ESD Protection on Card Pins (8.0 kV, Human Body Model) Supports up to 40 MHz Input Clock Built-in Programmable CRD_CLK Stop Function Handles Run or Low State Programmable CRD_CLK Slopes to Cope with Wide Operating Frequency Range Fast CRD_VCC Turn-on and Turn-off Sequence These are Pb-Free Devices*
MARKING DIAGRAM
20 NCN 6001 ALYWG G 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
PIN CONNECTIONS
I/O 1 INT 2 CLK_IN 3 MOSI 4 CLK_SPI 5 EN_RPU 6 MISO 7 CS 8 VCC 9 Lout_L 10 (Top View) 20 CRD_IO 19 CRD_RST 18 CRD_DET 17 CRD_CLK 16 GND 15 C4/S0 14 C8/S1 13 CRD_VCC 12 Lout_H 11 PWR_GND
Typical Applications
E-Commerce Interface Automatic Teller Machine (ATM) Smart Card Point of Sales (POS) System Pay TV System
ORDERING INFORMATION
Device NCN6001DTBR2 Package Shipping
TSSOP-20* 2500 Tape & Reel
NCN6001DTBR2G TSSOP-20* 2500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. Publication Order Number: NCN6001/D
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
January, 2006 - Rev. 3
NCN6001
VCC J1 C1 10 mF 9 1 2 MICROCONTROLLER 3 4 5 7 8 6 R1 47 k VCC GND 10 CLK_IN MOSI CLK_SPI MISO CS EN_RPU Lout_L CRD_CLK CRD_VCC C4/S0 C8/S1 GND PWR_GND VCC I/O INT U1 CRD_DET CRD_IO CRD_RST 17 18 20 19 17 13 15 14 16 11 12 C2 10 mF GND GND 18 7 2 3 5 1 4 8 Swa Swb I/O RST CLK GND VCC C4 C8 ISO7816 18 CRD_DET 500 k VCC CS MISO 7 MOSI 4 CLK_SPI 5 8 3 States DUAL 8-BIT SHIFT REGISTER ADDRESS DECODING b0 b1 DC/DC CONVERTER b7 b6 b5 b4 b3 b2 b1 b0 9 VCC 10 Lout_L 12 Lout_H 13 CRD_VCC 11 PWR_GND GND b7 b6 b5 LOGIC CONTROL b3 b2 b4 15 C4/S0 14 C8/S1 19 CRD_RST 17 CRD_CLK 20 CRD_IO 20 k GROUND 16 GND CRD_VCC
GND
SMARTCARD_C
Lout_H NCN6001 L1 22 mH
GND
Figure 1. Typical Application
VCC 50 k INT 2 INTERRUPT BLOCK PROGRAMMABLE CARD DETECTION
ISO7816 SEQUENCER
CLK_IN EN_RPU
3 6
CLOCK DIVIDER
I/O
1
20 k
Figure 2. Block Diagram
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CARD PINS DRIVER
NCN6001
PIN FUNCTIONS AND DESCRIPTION
Pin 1 Name I/O Type Input/Output Pullup Description This pin is connected to an external microcontroller interface. A bidirectional level translator adapts the serial I/O signal between the smart card and the microcontroller. The level translator is enabled when CS = L, the sub address has been selected and the system operates in the Asynchronous mode. When a Synchronous card is in use, this pin is disconnected and the data and the transaction take place with the MISO b3 register. The internal pullup resistor connected on the mC side is activated and visible by the selected chip only. This pin is activated LOW when a card has been inserted and detected by CRD_DET pin. Similarly, an interrupt is generated when the CRD_VCC output is overloaded, or when the card has been extracted whatever be the transaction status (running or standby). The INT signal is reset to High according to Table 7 and Figure 11. On the other hand, the pin is forced to a logic High when the input voltage VCC drops below 2.0 V. The built-in Schmitt trigger receiver makes this pin suitable for a large type of clock signal (Figure 30). This pin can be connected to either the microcontroller master clock, or to a crystal signal, to drive the external smart cards. The signal is fed to the internal clock selector circuit and translated to the CRD_CLK pin at either the same frequency, or divided by 2 or 4, depending upon the programming mode. Note: The chip guarantees the EMV 50% Duty Cycle when the clock divider ratio is 1/2 or 1/4, even when the CLK_IN signal is out of the 45% to 55% range specified by ISO and EMV specifications. Care must be observed, at PCB level, to minimize the pick-up noise coming from the CLK_IN line. Master Out Slave In: SPI Data Input from the external microcontroller. This byte contents the address of the selected chip among the four possible, together with the programming code for a given interface. Clock Signal to synchronize the SPI data transfer. The built-in Schmitt trigger receiver makes this pin compatible with a wide range of input clock signal (Figure 30). This clock is fully independent from the CLK_IN signal and does not play any role with the data transaction. This pin is used to activate the I/O internal pullup resistor according to the here below true table: EN_RPU = Low I/O Pullup resistor disconnected EN_RPU = High I/O Pullup resistor connected When two or more NCN6001 chips shares the same I/O bus, one chip only shall have the internal pullup resistor enabled to avoid any overload of the I/O line. Moreover, when Asynchronous and Synchronous cards are handled by the interfaces, the activated I/O pullup resistor must preferably be the one associated with the Asynchronous circuit. On the other hand, since no internal pullup bias resistor is built in the chip, pin 6 must be connected to the right voltage level to make sure the logic function is satisfied. Master In Slave Out: SPI Data Output from the NCN6001. This byte carries the state of the interface, the serial transfer being achieved according to the programmed mode (Table 2), using the same CLK_SPI signal and during the same MOSI time frame. The three high bits [b7:b5] have no meaning and shall be discarded by the microcontroller. An external 4.7 kW Pull down resistor might be necessary to avoid misunderstanding of the pin 7 voltage during the High Z state. This pin synchronizes the SPI communication and provides the chip address and selected functions. All the NCN6001 functions, both programming and card transaction, are disabled when CS = H. This pin is connected to the NCN6001 supply voltage and must be bypassed to ground by a 10 mF/6.0 V capacitor. Since tantalum capacitors have relative high ESR, using low ESR ceramic type (MURATA X5R, Resr < 100 mW) is highly recommended. The High Side of the external inductor is connected between this pin and Lout_L/pin 12 to provide the DC/DC function. The current flowing into this inductor is internally sensed and no external shunt resistor is used. Typically, Lout = 22 mH, with ESR < 2.0 W, yields a good efficiency performance for a maximum 65 mA DC output load. Note: The inductor shall be sized to handle the 450 mA peak current flowing during the DC/DC operation (see CoilCraft manufacturer data sheet).
2
INT
OUTPUT Pullup
3
CLK_IN
CLOCK INPUT High impedance
4
MOSI
INPUT
5
CLK_SPI
INPUT
6
EN_RPU
INPUT, Logic
7
MISO
OUTPUT
8
CS
INPUT
9
VCC
POWER
10
Lout_H
POWER
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NCN6001
PIN FUNCTIONS AND DESCRIPTION
Pin 11 Name PWR_GND Type POWER Description This pin is the Power Ground associated with the built-in DC/DC converter and must be connected to the system ground together with GROUND pin 16. Using good quality ground plane is recommended to avoid spikes on the logic signal lines. The High Side of the external inductor is connected between this pin and Lout_H to activate the DC/DC function. The built-in NMOS and PMOS devices provide the switching function together with the CRD_VCC voltage rectification (Figure 17). This pin provides the power to the external card. It is the logic level "1" for CRD_IO, CRD_RST, CRD_C4, CRD_C8 and CRD_CLK signals. The energy stored by the DC/DC external inductor Lout must be smoothed by a 10 mF/Low ESR capacitor, connected across CRD_VCC and GND. Using ceramic type of capacitor (MURATA X5R, ESR < 50 mW) is strongly recommended. In the event of a CRD_VCC UVLOW voltage, the NCN6001 detects the situation and feedback the information in the STATUS bit. The device does not take any further action, particularly the DC/DC converter is neither stopped nor re programmed by the NCN6001. It is up to the external MPU to handle the situation. However, when the CRD_VCC is overloaded, the NCN6001 shuts off the DC/DC converter, runs a Power Down ISO sequence and reports the fault in the STATUS register. Since high transient current flows from this pin to the load, care must be observed, at PCB level, to minimize the series ESR and ESL parasitic values. The NCN6001 demo board provides an example of a preferred PCB layout. Auxiliary mixed analog/digital line to handle either a synchronous card, or as Chip Select Identification (MISO, Bit 0): see Figure 9. The pin is driven by an open drain stage, the pullup resistor being connected to the CRD_VCC supply. When the pin is used as a logic input (asynchronous cards), the positive logic condition applies: Connected to GND Logic = Zero Connected to VCC or left Open Logic = One A built-in accelerator circuit makes sure the output positive going rise time is fully within the ISO/EMV specifications. NOTE: The pin is capable of reading the logic level when the chip operates an asynchronous interface, but is not intended to read the data from the external card when operated in the synchronous mode. It merely returns the logic state forced during a write instruction to the card.
12
Lout_L
POWER
13
CRD_VCC
POWER
14
C8/S0
I/O
15
C4/S1
I/O
Auxiliary mixed analog/digital line to handle either a synchronous card, or as Chip Select Identification (MISO, Bit 1): see Figure 9. The pin is driven by an open drain stage, the pullup resistor being connected to the CRD_VCC supply. When the pin is used as a logic input (asynchronous cards), the positive logic condition applies: Connected to GND Logic = Zero Connected to VCC or left Open Logic = One A built-in accelerator circuit makes sure the output positive going rise time is fully within the ISO/EMV specifications. NOTE: The pin is capable of reading the logic level when the chip operates an asynchronous interface, but is not intended to read the data from the external card when operated in the synchronous mode. It merely returns the logic state forced during a write instruction to the card.
16
GROUND
SIGNAL
The logic and low level analog signals shall be connected to this ground pin. This pin must be externally connected to the PWR_GND pin 12. The designer must make sure no high current transients are shared with the low signal currents flowing into this pin. This pin is connected to the CLK pin of the card connector. The CRD_CLK signal comes from the clock selector circuit output. An internal active pull down NMOS device forces this pin to Ground during either the CRD_VCC startup sequence, or when CRD_VCC = 0 V. The rise and fall slopes, either FAST or SLOW, of this signal can be programmed by the MOSI message (Table 2). Care must be observed, at PCB level, to minimize the pick-up noise coming from the CRD_CLK line.
17
CRD_CLK
OUTPUT
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NCN6001
PIN FUNCTIONS AND DESCRIPTION
Pin 18 Name CRD_DET Type INPUT Description The signal coming from the external card connector is used to detect the presence of the card. A built-in pullup low current source biases this pin High, making it active LOW, assuming one side of the external switch is connected to ground. A built-in digital filter protect the system against voltage spikes present on this pin. The polarity of the signal is programmable by the MOSI message, according to the logic state depicted Table 2. On the other hand, the meaning of the feedback message contained in the MISO register bit b4, depends upon the SPI mode of operation as defined here below: SPI Normal Mode: The MISO bit b4 is High when a card is inserted, whatever be the polarity of the card detect switch. SPI Special Mode: The MISO bit b4 copies the logic state of the Card detect switch as depicted here below, whatever be the polarity of the switch used to handle the detection: CRD_DET = Low MISO/b4 = Low CRD_DET = High MISO/b4 = High In both cases, the chip must be programmed to control the right logic state (Table 2). Since the bias current supplied by the chip is very low, typically 5.0 mA, care must be observed to avoid low impedance or cross coupling when this pin is in the Open state. This pin is connected to the RESET pin of the card connector. A level translator adapts the RESET signal from the microcontroller to the external card. The output current is internally limited to 15 mA. The CRD_RST is validated when CS = Low and hard wired to Ground when the card is deactivated, by and internal active pull down circuit. Care must be observed, at PCB design level, to avoid cross coupling between this signal and the CRD_CLK clock. This pin handles the connection to the serial I/O pin of the card connector. A bidirectional level translator adapts the serial I/O signal between the card and the microcontroller. An internal active pull down MOS device forces this pin to Ground during either the CRD_VCC startup sequence, or when CRD_VCC = 0 V. The CRD_IO pin current is internally limited to 15 mA. Care must be observed, at PCB design level, to avoid cross coupling between this signal and the CRD_CLK clock.
19
CRD_RST
OUTPUT
20
CRD_IO
I/O Pullup
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NCN6001
MAXIMUM RATINGS (TA = +25C unless otherwise noted)
Rating Power Supply Voltage Power Supply Current Note: This current represents the maximum peak current the pin can sustain, not the NCN6001 average consumption. Power Supply Current Digital Input Pins Digital Input Pins Digital Output Pins Digital Output Pins Card Interface Pins Card Interface Pins, excepted CRD_CLK Inductor Current ESD Capability (Note 1) Standard Pins Card Interface Pins CRD_DET Power Dissipation @ Tamb = +85C Thermal Resistance, Junction-to-Air (RqJA) Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature (Note 2) Storage Temperature Range Symbol VCC Ibat Value 6.0 500 Unit V mA
ICC Vin Iin Vout Iout Vcard Icard ILout VESD
150 (Internally Limited) -0.5 V < Vin < VCC +0.5 V, but < 6.0 V "5.0 -0.5 V < Vin < VCC +0.5 V, but < 6.0 V "10 -0.5 V < Vcard < CRD_VCC +0.5 V 15 (Internally Limited) 500 (Internally Limited) 2.0 8.0 4.0
mA V mA V mA V mA mA kV kV kV mW C/W C C C C
PDS RqJA TA TJ TJmax Tstg
320 125 -25 to +85 -25 to +125 +150 -65 to +150
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Human Body Model, R = 1500 W, C = 100 pF. 2. Absolute Maximum Rating beyond which damage to the device may occur.
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NCN6001
DIGITAL PARAMETERS @ 2.7 V < VCC < 5.5 V (-25C to +85C ambient temperature, unless otherwise noted). Note: Digital inputs undershoot < - 0.3 V to ground, Digital inputs overshoot < 0.3 V to VCC.
Rating Input Asynchronous Clock Duty Cycle = 50% @ VCC = 3.0 V Over the Temperature Range @ VCC = 5.0 V Over the Temperature Range Input Clock Rise Time Input Clock Fall Time Input SPI Clock Input CLK_SPI Rise/Fall Time @ Cout = 30 pF Input MOSI Rise/Fall Time @ Cout = 30 pF Output MISO Rise/Fall Time @ Cout = 30 pF Input CS Rise/Fall Time I/O Data Transfer Switching Time, both directions (I/O and CRD_IO), @ Cout = 30 pF I/O Rise Time * (Note 4) I/O Fall Time INT Pullup Resistance Positive Going Input High Voltage Threshold (CLK_IN, MOSI, CLK_SPI, EN_RPU, CS) Negative Going Input High Voltage Threshold (CLK_IN, MOSI, CLK_SPI, EN_RPU, CS) Output High Voltage INT, MISO @ OH = -10 mA Output Low Voltage INT, MISO @ OH = 200 mA Delay Between Two Consecutive CLK_SPI Sequence Pin 3 Symbol FCLKIN - - 3 5 5 4 7 8 1, 20 tRIO tFIO 2 2, 3, 4, 5, 6, 8 2, 3, 4, 5, 6, 8 2, 7 2, 7 5 RITA VIA 0.70 * VCC VILLA 0 VOH VCC -1.0 V VOL - tdclk 33 - - 0.4 - ns - VCC V - 0.3 * VCC V - VCC V - - 20 - - 50 0.8 0.8 80 ms ms kW V Ftr Ftf FCLKSPI trspi, tfspi trmosi, tfmosi trmiso, tfmiso trstr, tfstr 2.5 2.5 - - - - - - - - - - - - - - 30 40 - - 15 12 12 12 12 ns ns MHz ns ns ns ns Min Typ Max Unit MHz
3. Since a 20 kW (typical) pullup resistor is provided by the NCN6001, the external MPU can use an Open Drain connection. On the other hand, NMOS smart cards can be used straightforward.
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NCN6001
POWER SUPPLY @ 2.7 V < VCC < 5.5 V (-25C to +85C ambient temperature, unless otherwise noted).
Rating Input Power Supply Standby Supply Current Conditions: INT = CLK_IN = CLK_SPI = CS = H I/O = MOSI = EN_RPU = H, No Card Inserted VCC = 3.0 V VCC = 5.0 V DC Operating Current CLK_IN = Low, All Card Pins Unloaded @ VCC = 3.3 V, CRD_VCC = 5.0 V @ VCC = 5.5 V, CRD_VCC = 5.0 V VCC Under Voltage DetectionHigh VCC Under Voltage DetectionLow VCC Under Voltage (Note 6) Output Card Supply Voltage @ 2.7 V < VCC < 5.5 V CRD_VCC = 1.8 V @ Iload = 35 mA CRD_VCC = 3.0 V @ Iload = 60 mA CRD_VCC = 5.0 V @ Iload = 65 mA Maximum Continuous Output Current @ CRD_VCC = 1.8 V @ CRD_VCC = 3.0 V @ CRD_VCC = 5.0 V Output Over Current Limit VCC = 3.3 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V VCC = 5.0 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V Output Dynamic Peak Current @ CRD_VCC = 1.8 V, 3.0 V or 5.0 V, Cout = 10 mF (Notes 4 and 5) Output Card Supply Voltage Ripple @ VCC = 3.6 V, Lout = 22 mH, Cout1 = Cout2 = 4.7 mF Ceramic X7R, Iout = 55 mA CRD_VCC = 5.0 V (Note 4) CRD_VCC = 3.0 V CRD_VCC = 1.8 V Output Card Supply Turn On Time @ Lout = 22 mF, Cout1 = 10 mF Ceramic VCC = 2.7 V, CRD_VCC = 5.0 V Output Card Supply Shut Off Time @ Cout1 = 10 mF, Ceramic VCC = 2.7 V, CRD_VCC = 5.0 V, VCCOFF < 0.4 V Pin 9 9 Symbol VCC Iccsb - - 9 Iccop - - 9 VCCLH VCCLL VCCPOR 2.20 2.00 1.50 - - - - - - 1.80 3.00 5.00 - - - 100 150 - 0.5 1.5 2.70 2.60 2.20 V 25 35 50 60 mA Min 2.70 Typ - Max 5.50V Unit V mA
13 VC2H VC3H VC5H 13 Icc 35 60 65 13 Iccov - - 13 Iccd 100 13 - - - - 13 VccTON - 13 VccTOFF - 100 250 - 500 35 35 35 - - - - - - - - - 1.65 2.75 4.75 1.95 3.25 5.25
V
mA
mA
mA
mV
ms
ms
4. Ceramic X7R, SMD type capacitors are mandatory to achieve the CRD_VCC specifications. When an electrolytic capacitor is used, the external filter must include a 220 nF, max 50 mW ESR capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum. Depending upon the PCB layout, it might be necessary to use two 4.7 mF/6.0 V/ceramic/X5R/SMD 0805 in parallel, yielding an improved CRD_VCC ripple over the temperature range. 5. Pulsed current, according to ISO7816-3, paragraph 4.3.2. 6. No function externally available during the VCC POR sequence.
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NCN6001
SMART CARD INTERFACE @ 2.7 V < VCC < 5.5 V (-25C to +85C ambient temperature, unless otherwise noted). Note: Digital inputs undershoot < - 0.3 V to ground, Digital inputs overshoot < 0.3 V to VCC.
Rating CRD_RST @ CRD_VCC = 1.8 V, 3.0 V, 5.0 V Output RESET VOH @ Irst = -200 mA Output RESET VOL @ Irst = 200 mA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @Cout = 30 pF CRD_CLK as a function of CRD_VCC CRD_VCC = +5.0 V or 3.0 V or 1.8V Output Frequency Output VOH @ Icrd_clk = -200 mA Output VOL @ Icrd_clk = 200 mA CRD_CLK Output Duty Cycle CRD_VCC = 5.0 V CRD_VCC = 3.0 V CRD_VCC = 1.8 V (Note 7) Rise & Fall time @ CRD_VCC = 1.80 V to 5.0 V Fast Mode Output CRD_CLK Rise time @ Cout = 30 pF Output CRD_CLK Fall time @ Cout = 30 pF Rise & Fall time @ CRD_VCC = 1.80 V to 5.0 V Slow Mode Output CRD_CLK Rise time @ Cout = 30 pF Output CRD_CLK Fall time @ Cout = 30 pF CRD_IO @ CRD_VCC = 1.8 V 3.0 V, 5.0 V CRD_IO Data Transfer Frequency CRD_IO Rise time @ Cout = 30 pF CRD_IO Fall time @ Cout = 30 pF Output VOH @ Icrd_clk = -20 mA Output VOL @ Icrd_clk = 500 mA, VIL = 0 V CRD_IO Pullup Resistor CRD_C8 Output Rise and Fall Time @ Cout = 30 pF CRD_C4 Output Rise and Fall Time @ Cout = 30 pF CRD_C4 and CRD_C8 Data Transfer Frequency CRD_C8, CRD_C4 Output Voltages High Level @ Irst = -200 mA Low Level @ Irst = +200 mA C8/S0 and C4/S0 Address Bias Current (Note 8) Card Detection Digital Filter Delay: Card Insertion Card Extraction Card Insertion or Extraction Positive Going Input High Voltage Card Insertion or Extraction Negative Going Input Low Voltage Card Detection Bias Pullup Current @ VCC = 5.0 V Output Peak Max Current Under Card Static Operation Mode @ CRD_VCC = 3.0 V or = 5.0 V CRD_RST, CRD_IO, CRD_C4, CRD_C8 Output Peak Max Current Under Card Static Operation Mode @ CRD_VCC = 3.0 V or = 5.0 V CRD_CLK 20 FIO tRIO tFIO VOH VOL 20 14 15 14, 15 14, 15 RCRDPU tRC8, tFC8 tRC4, tFC4 FC48 VOH, VOL CRD_VCC - 0.5 0 14, 15 18 TCRDIN TCRDOFF 18 18 18 1, 20 VIHDET VILDET IDET Icrd_iorst 25 25 0.70 * VCC 0 - - 50 50 - - 10 - 150 150 VCC 0.30 * VCC - 15 Ibc4c8 - - - 1.0 - 0.4 - V V mA ms ms V V mA mA - - - CRD_VCC 0 14 - - - 400 - - - - 20 - - 400 - 0.8 0.8 CRD_VCC 0.4 26 100 100 - kHz ms ms V V kW ns ns kHz Pin 19 VOH VOL tR tF 17 CRD_VCC - 0.5 0 - - - - - - CRD_VCC 0.4 100 100 V V ns ns Symbol Min Typ Max Unit
FCRDCLK VOH VOL
- CRD_VCC - 0.5 0
20 CRD_VCC +0.4
MHz V V
FCRDDC
45 40 40
55 60 60
% % %
tress tfcs
- -
2.1 1.9
4 4
ns ns
trills tulsa
- -
11.5 10.8
16 16
ns ns
- 0.5
17
Icrd_clk
-
-
70
mA
7. Parameter guaranteed by design, function 100% production tested. 8. Depending upon the environment, using and external pullup resistor might be necessary to cope with PCB surface leakage current.
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NCN6001
PROGRAMMING
Write Register " WRT_REG
The WRT_REG register handles three command bits [b5:b7] and five data bits [b0:b4] as depicted in Table 1. These bits are concatenated into a single byte to accelerate the programming sequence. The register can be updated when CS is low only.
Table 1. WRT_REG Bits Definitions
The CRD_RST pin reflects the content of the MOSI WRT_REG[b4] during the chip programming sequence. Since this bit shall be Low to address the internal register of the chip, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
b0 b1
If (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then Case 00 CRD_VCC = 0 V Case 01 CRD_VCC = 1.8 V Case 10 CRD_VCC = 3.0 V Case 11 CRD_VCC = 5.0 V Else if (b7 + b6 + b5) = 110 then b1 drives C4 b0 drives C8 Else if (b7 + b6 + b5) = 101 then Case (b4 + b3 + b2 + b1 + b0) = 0000 CRD_DET = NO Case (b4 + b3 + b2 + b1 + b0) = 0001 CRD_DET = NC Case (b4 + b3 + b2 + b1 + b0) = 0010 SPI_MODE = Special Case (b4 + b3 + b2 + b1 + b0) = 0011 SPI_MODE = Normal End if If (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then Case 00 CRD_CLK = L Case 01 CRD_CLK = CLK_IN Case 10 CRD_CLK = CLK_IN/2 Case 11 CRD_CLK = CLK_IN/4 Else if (b7 + b6 + b5) = 110 then b3 drives CRD_CLK b2 drives CRD_IO Else if (b7 + b6 + b5) = 101 then Case (b4 + b3 + b2 + b1 + b0) = 0000 CRD_DET = NO Case (b4 + b3 + b2 + b1 + b0) = 0001 CRD_DET = NC Case (b4 + b3 + b2 + b1 + b0) = 0010 SPI_MODE = Special Case (b4 + b3 + b2 + b1 + b0) = 0011 SPI_MODE = Normal End if Drives CRD_RST pin (Note 10) 000 001 010 011 100 110 101 111 Select Asynchronous Card #0 (Note 9), four chips bank CS signal Select Asynchronous Card #1 (Note 9), four chips bank CS signal Select Asynchronous Card #2 (Note 9), four chips bank CS signal Select Asynchronous Card #3 (Note 9), four chips bank CS signal Select External Asynchronous Card, dedicated CS signal Select External Synchronous Card, dedicated CS signal Set Card Detection Switch polarity, Set SPI_MODE normal or special. Set CRD_CLK slopes Fast or Slow. Reserved for future use
b2 b3
b4 b5, b6, b7
9. When operating in Asynchronous mode, [b5:b7] are compared with the external voltage levels present pins C4/S0 and C8/S1 (respectively pins 15 and 14). 10. The CRD_RST pin reflects the content of the MOSI WRT_REG[b4] during the chip programming sequence. Since this bit shall be Low to address the internal register of the chip, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
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NCN6001
Table 2. WRT_REG Bits Definitions and Functions
ADDRESS CHIP BANK 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 b7 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b6 X X X X 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 b5 X X X X 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 b4 RST RST RST RST 0 0 0 0 0 0 - RST RST RST RST RST 0 0 0 0 0 0 - b3 0 0 1 1 0 0 0 0 0 0 - 0 0 1 1 CLK 0 0 0 0 0 0 - b2 0 1 0 1 0 0 0 0 1 1 - 0 1 0 1 I/O 0 0 0 0 1 1 - b1 0 0 1 1 0 0 1 1 0 0 - 0 0 1 1 C4 0 0 1 1 0 0 - b0 0 1 0 1 0 1 0 1 0 1 - 0 1 0 1 C8 0 1 0 1 0 1 - PARAMETERS MOSI bits [b3:b2] CRD_CLK Low 1/1 1/2 1/4 - - - - - - - Low 1/1 1/2 1/4 - - - - - - - - MOSI bits [b1:b0] CRD_VCC 0 1.8 V 3.0 V 5.0 V - - - - - - - 0 1.8 V 3.0 V 5.0 V - - - - - - - - MOSI bits [b7:b0] CRD_DET - - - - NO NC Special Normal SLO_SLP FST_SLP RFU - - - - Data to Sync. Card NO NC Special Normal SLO_SLP FST_SLP RFU
11. Chip Bank 1 = Asynchronous cards, four slots addresses 1 to 4. Chip Bank 2 = Asynchronous or synchronous card, single slot. 12. Address 101 and bits [b0 : b4] not documented in the table are reserved for future use. Address 111 is reserved for future use.
Although using the %111XXXXX code is harmless from a NCN6001 silicon standpoint, care must be observed to avoid uncontrolled operation of the interface sharing the same digital bus. When this code is presented on the digital bus, the CRD_RST signal of any interface sharing the CS signal, immediately reflects the digital content of the MOSI bit b4 register. Similarly, the MISO register of the shared interface is presented on the SPI port. Consequently, data collision, at MISO level, and uncontrolled card operation are
likely to happen if the system uses a common Chip Select line. It is strongly recommended to run a dedicated CS bit to any external circuit intended to use the $111xxxxx code. On the other hand, the CRD_RST signal will be forced to Low when the internal register of the chip is programmed to accommodate different hardware conditions (NO/NC, Special/Normal, SLO_SLP/FST_SLP). Generally speaking, such a configuration shall take place during the Power On Reset to avoid CRD_RST activation.
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NCN6001
Read Register " READ_REG
The READ_REG register contains the data read from the interface and from the external card. The selected register is transferred to the MISO pin during the MOSI sequence (CS = Low). Table 3 gives the bits definition. Depending upon the programmed SPI_MODE, the content of READ_REG is transferred on the MISO line
Table 3. MOSI and MISO Bits Identifications and Functions
MOSI b7 0 0 0 0 1 1 MISO z b6 0 0 1 1 0 1 z b5 0 1 0 1 0 0 z b4 RST RST RST RST RST RST Card Detect b3 CLK CLK CLK CLK CLK CLK I/O b2 CLK CLK CLK CLK CLK I/O C4 b1
either on the Positive going (SPI_MODE = Special) or upon the Negative going slope (SPI_MODE = Normal) of the CLK_SPI signal. The external microcontroller shall discard the three high bytes since they carry no valid data.
b0 VCC VCC VCC VCC VCC C8 PWR Monitor
Operating Mode Asynchronous, Program Chip Asynchronous, Program Chip Asynchronous, Program Chip Asynchronous, Program Chip Asynchronous, Program Chip Synchronous, Sets Card Bits Read Back Data
VCC VCC VCC VCC VCC C4 C8
ASYNCHRONOUS MODE In this mode, the CRD_C4 and CRD_C8 pins are used to define the physical addresses of the interfaces when a bank of up to four NCN6001 share the same digital bus. SYNCHRONOUS MODE In this mode, CRD_C4 and CRD_C8 are connected to the smart card and it is no longer possible to share the CS signal with other device. Consequently, a dedicated Chip Select signal must be provided when the interfaces operate in a multiple operation mode (Figure 33). On the other hand, since bits [b4 - b0] of the MOSI register contain the smart card data, programming the
Example:
CRD_VCC output voltage shall be done by sending a previous MOSI message according to Table 1 and Table 2. The CRD_RST pin reflects the content of the MOSI WRT_REG[b4] during the chip programming sequence. Since this bit shall be Low to address the internal register of the chip, care must be observed as this signal will be immediately transferred to the CRD_RST pin. Since no physical address can exist when the chip operates in this mode, the MOSI register must use the format %100XXXXX to program the chip (%100 prefix, XXXXX data).
LDAA STAA LDAA STAA LDAA STAA
#%10010111 MOSI #%11010011 MOSI #%00111110 MOSI
;set RST = H, CLK = 1/1, VCC = 5.0 V ;SYNC. Card: set RST = H, CLK = L, IO = L, C4 = H, C8= H ;ASYNC. Card: set RST = H, CLK = 1/4, VCC = 3.0 V
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NCN6001
STARTUP DEFAULT CONDITIONS At startup, when the VCC power supply is turned on, the internal POR circuit sets the chip in the default conditions as defined in Table 4.
Table 4. Startup Default Conditions
CRD_DET CRD_VCC CRD_CLK CRD_CLK Protocol Normally Open Off tr and tf = SLOW Low Special Mode
CRD_VCC OPERATION The built-in DC/DC converter provides the CRD_VCC voltage and can be programmed to run one of the three possible values, 1.8 V, 3.0 V or 5.0 V, assuming the input voltage VCC is within the 2.7 V to 5.5 V range. In any case, CRD_VCC is voltage regulated, together with a current overload detection. On the other hand, the power conversion is automatically switched to handle either a boost or a buck mode of operation, depending upon the difference between the input voltage VCC and the output supply CRD_VCC. The CRD_VCC output current is a function of the VCC input value as depicted in Table 5.
Table 5. CRD_VCC Output Voltage Range
CRD_VCC 1.80 V 3.0 V 5.0 V Comments Maximum Output DC Current = 35 mA Maximum Output DC Current = 60 mA Maximum Output DC Current = 65 mA
CARD DETECTION The card is detected by the external switch connected pin 18. The internal circuit provides a positive bias of this pin and the polarity of the insertion/extraction is programmable by the MOSI protocol as depicted in Table 2. The bias current is 1.0 mA typical and care must be observed to avoid leakage to ground from this pin to maintain the logic function. In particular, using a low impedance probe (< 1.0 MW) may lead to uncontrolled operation during the debug. Depending upon the programmed condition, the card can be detected either by a Normally Open (default condition) or a Normally Close switch (Table 2). On the other hand, the meaning of the feedback message contained in the MISO register bit b4, depends upon the SPI mode of operation as defined here below: SPI Normal Mode: the MISO bit b4 is High when a card is inserted, whatever be the polarity of the card detect switch. SPI Special Mode: the MISO bit b4 copies the logic state of the Card detect switch as depicted here below, whatever be the polarity of the switch used to handle the detection: CRD_DET = Low MISO/b4 = Low CRD_DET = High MISO/b4 = High
Whatever the CRD_VCC output voltage may be, a built-in comparator makes sure the voltage is within the ISO7816-3/ EMV specifications. If the voltage is no longer within the minimum/maximum values, the DC/DC is switched Off, the Power Down sequence takes place and an interrupt is presented at the INT pin 2. POWERUP SEQUENCE The Powerup Sequence makes sure all the card related signals are Low during the CRD_VCC positive going slope. These lines are validated when CRD_VCC is above the minimum specified voltage (depending upon the programmed CRD_VCC value).
Figure 3. Typical Startup CRD_VCC Sequence
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NCN6001
At powerup, the CRD_VCC voltage rise time depends upon the current capability of the DC/DC converter associated with the external inductor L1 and the reservoir capacitor connected across CRD_VCC and GROUND. During this sequence, the average input current is 300 mA typical (Figure 3), assuming the system is fully loaded during the startup. Finally, the application software is responsible for the smart card signal sequence. On the other hand, at turn off, the CRD_VCC fall time depends upon the external reservoir capacitor and the peak current absorbed by the internal NMOS transistor built across CRD_VCC and GROUND. These behaviors are depicted in Figure 4. Since these parameters have finite values, depending upon the external constraints, the designer must take care of these limits if the tON or the tOFF provided by the data sheets does not meet his requirements.
Figure 4. CRD_VCC Typical Rise and Fall Time
Figure 5. Startup Sequence with ATR
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NCN6001
POWER DOWN SEQUENCE The NCN6001 provides an automatic Power Down sequence, according to the ISO7816-3 specifications, and the communication session terminates immediately. The sequence is launched when the card is extracted, or when the CRD_VCC voltage is overloaded as described by the ISO/CEI 7816-3 sequence depicted hereafter: ISO7816-3 sequence: "Force RST to Low "Force CLK to Low, unless it is already in this state "Force C4 & C8 to Low "Force CRD_IO to Low "Shut Off the CRD_VCC supply Since the internal digital filter is activated for any card insertion or extraction, the physical power sequence will be activated 50 ms (typical) after the card has been extracted. Of course, such a delay does not exist when the MPU intentionally launches the power down. Figure 6 shows the oscillogram captured in the NCN6001 demo board. The internal active pull down NMOS connected across CRD_VCC and GND discharges the external reservoir capacitor in 100 ms (typical), assuming Cout = 10 mF.
Typical delay between each signal is 500 ns
Figure 6. Typical Power Down Sequence
The internal active pull down NMOS connected across CRD_VCC and GND discharges the external reservoir capacitor in 100 ms (typical), assuming Cout = 10 mF.
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NCN6001
DATA I/O LEVEL SHIFTER The level shifter accommodates the voltage difference that might exist between the microcontroller and the smart card. A pulsed accelerator built-in circuit provides the fast
VCC VCC
positive going transient according to the ISO7816-3 specifications. The basic I/O level shifter is depicted in Figure 7.
9 6 U1
EN_RPU
PMOS
200 ns Q1
200 ns Q2 R2
CRD_VCC 13 18 k
R1 I/O 1
18 k
CRD_IO 20 Q3 Q4
SYNC
CARD ENABLE POR SEQ 1 LOGIC AND LEVEL SHIFT
Q5
GND CRD_VCC MOSI/b2 From MOSI decoding GND MOSI/b3 Q5 VCC
Figure 7. Basic I/O Internal Circuit
The transaction is valid when the Chip Select pin is Low, the I/O signal being Open Drain or Totem Pole on either sides. Since the device can operate either in a single or a multiple card system, provisions have been made to avoid CRD_IO current overload. Depending upon the selected mode of operation (ASYNC. or Sync), the card I/O line is respectively connected to either I/O pin 1, or to the MOSI register byte bit 2. On the other hand, the logic level present at the card I/O is feedback to the mC via the MISO register bit 3. The logic level present at pin 6 controls the connection of the internal pullup as depicted in Table 6.
Table 6. I/O Pullup Resistor True Table
EN_RPU Low High NOTE: I/O Pullup Resistor Open, 18 kW disconnected Internal 18 kW pullup active 18 kW typical value Device Operation Parallel Mode Single Device NOTE: Both sides of the interface run with open drain load (worst case condition).
Figure 8. Typical I/O Rise and Fall Time
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NCN6001
GENERAL PURPOSE CRD_C4 AND CRD_C8 These two pins can be used as a logic input to define the address of a given interface (in the range $00 to $11), or as a standard C4/C8 access to the smart card's channels. Since
VCC Vmax U1 U3 Q2 SWITCHED BIAS R1 ADDRESS CONTROL C4 1 2 1 U8 2 VCC U2 I=1A CRD_VCC U6 ESD U9 GND GND Q3 U4 3 Q1 500 R
these pins can be directly connected to the VCC power supply, both output stages are built with switched NMOS/PMOS totem pole as depicted in Figure 9.
CRD_VCC
WRT_C4
LEVEL SHIFTER
3
READ_C4
U5 3 1 U7 2
Figure 9. Typical CRD_C4 Output Drive and Logic Control
The C4 and C8 pins are biased by an internal current source to provide a logic one when the pin is left open. In this case, care must be observed to avoid relative low impedance to ground to make sure the pin is at a High logic level. However, it is possible to connect the pin to VCC (battery supply) to force the logic input to a High level, regardless of the input bias. Thanks to the CONTROL internal signal, the system automatically adapts the mode of operation (chip address or data communication) and, except the leakage, no extra current is drawn from the battery to bias these pins when the logic level is High. When any of these pins is connected to GND, a continuous 1 mA typical sink current will be absorbed from the battery supply.
The switched Totem Pole structure provides the fast positive going transient when the related pin is forced to the High state during a data transfer. In the event of a low impedance connected across C4 or C8 to ground, the current flow is limited to 15 mA, according to the ISO7816-3 specification. The two general purpose pins can transfer data from the external microcontroller to the card and read back the logic state, but none of these pins can read the data coming from the external smart card. On the other hand, both C4 and C8 can read input logic, hence the physical address of a given chip. In order to sustain the 8 kV ESD specified for these pins, an extra protection structure Q3 has been implemented to protect the MOS gates of the input circuit.
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NCN6001
INTERRUPT When the system is powered up, the INT pin is set to High upon POR signal. The interrupt pin 2 is forced LOW when either a card is inserted/extracted, or when a fault is developed across the CRD_VCC output voltage. This signal
Table 7. Interrupt Reset Logic
Interrupt Source Card Insertion Card Insertion Over Load CS L L L CRD_VCC >0 =0 =0 Chip Address Selected Chip MOSI[b7 : B5] = 0xx or MOSI[b7 : B5] = 101 Selected Chip MOSI[b7 :B5] = 0xx or MOSI[b7 : B5] = 101 Selected Chip MOSI[b7 : B5] = 0xx or MOSI[b7 : B5] = 101
is neither combined with the CS signal, nor with the chip address. Consequently, an interrupt is placed on the mC input as soon as one of the condition is met. The INT signal is clear to High upon one of the condition given in Table 7.
When several interfaces share the same digital mC bus, it is up to the software to pool the chips, using the MISO register to identify the source of the interrupt.
T0 T1 T2 T3 T4 T5 T6 T8 T9 T10 T11
CS INT CRD_DET MOSI_b0 MOSI_b1 1 2 CRD_VCC > 0 V CRD_VCC = 0 V OVER LOAD CRD_VCC
3 T7
Figure 10. Basic Interrupt Function
Table 8. Interrupt Reset Logic Operation
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 A card has been inserted into the reader and detected by the CRD_DET signal. The NCN6001 pulls down the interrupt line. The mC sets the CS signal to Low, the chip is now active, assuming the right address has been placed by the MOSI register. The mC acknowledges the interrupt and resets the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed higher than zero volt. The card has been extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L). On the other hand, the PWR_DOWN sequence is activated by the NCN6001. The interrupt pin is clear by the zero volt programmed to the interface. Same as T0 The mC start the DC/DC converter, the interrupt is cleared (same as T2) An overload has been detected by the chip : the CRD_VCC voltage is zero, the INT goes Low. The card is extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L). The card is re-inserted before the interrupt is acknowledged by the mC: the INT pin stays Low. The mC acknowledges the interrupt and reset the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed higher than zero volt. The Chip Select signal goes High, all the related NCN6001 interface(s) are deactivated and no further programming or transaction can take place.
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NCN6001
SPI PORT The product communicates to the external microcontroller by means of a serial link using a Synchronous Port Interface protocol, the CLK_SPI being Low or High during the idle state. The NCN6001 is not intended to operate as a Master controller, but execute commands coming from the MPU. The CLK_SPI, the CS and the MOSI signals are under the microcontroller's responsibility. The MISO signal is generated by the NCN6001, using the CLK_SPI and CS
CS SPI_CLK MPU Asserts Chip Select MPU Enables Clock MPU Sends Bit MOSI RST_COUNTER NCN6001 Sends Bit from READ_REG MISO MPU Reads Bit tclr NCN6001 Reads Bit
lines to synchronize the bits carried out by the data byte. The basic timings are given in Figure 11 and Figure 12. The system runs with two internal registers associated with the MOSI and MISO data: WRT_REG is a write only register dedicated to the MOSI data. READ_REG is a read only register dedicated to the MISO data.
Figure 11. Basic SPI Timings and Protocol
When the CS line is High, no data can be written or read on the SPI port. The two data lines becomes active when CS = Low, the internal shift register is cleared and the communication is synchronized by the negative going edge of the CS signal. The data present on the MOSI line is considered valid on the negative going edge of the CLK_SPI clock and is transferred to the shift register on the next positive edge of the same CLK_SPI clock.
To accommodate the simultaneous MISO transmit, an internal logic identifies the chip address on the fly (reading and decoding the three first bits) and validates the right data present on the line. Consequently, the data format is MSB first to read the first three signal as bits B5, B6 and B7. The chip address is decoded from this logic value and validates the chip according to the C4 and C8 conditions (Figure 12).
CS
MPU Asserts Chip Set B7 B6 B5 B4 B3 B2 B1 B0 MPU Enables Clock CHIP ADDRESS MSB COMMAND AND CONTROL LSB
SPI_CLK
MOSI ADDRESS DECODE MISO
The Chip Address is decoded on the third clock pulse. MISO Line = High Impedance The MISO signal is activated and data transferred
Figure 12. Chip Address Decoding Protocol and MISO Sequence
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NCN6001
When the eight bits transfer is completed, the content of the internal shift register is latched on the positive going edge of the CS signal and the NCN6001 related functions are updated accordingly.
Select Chip from SYNCHRONOUS Bank Chip Nx CS SPI_CLK MPU Enables B7 B6 Clock B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 tdclk Chip Ny
CHIP ADDRESS MOSI SET_RST SET_CLK SET_VCC ADDRESS DECODE MISO Special Mode MISO Normal Mode MSB
COMMAND AND CONTROL LSB MSB LSB
MISO Line = High Impedance MISO Line = High Impedance Special Mode: MISO is synchronized with the SPI_CLK Positive going slope
Normal Mode: MISO is synchronized with the SPI_CLK Negative going slope
Figure 13. Basic Multi Command SPI Bytes
Since the four chips present in the Asynchronous Bank have an individual physical address, the system can control several of these chips by sending the data content within the same CS frame as depicted in Figure 13. The bits are decoded on the fly and the related sub blocks are updated accordingly. According to the SPI general specification, no code or activity will be transferred to any chip when the CS is High.
When two SPI bytes are sequentially transferred on the MOSI line, the CLK_SPI sequence must be separated by at least one half positive period of this clock (see tdclk parameter). The oscillograms shown in Figure 14 and Figure 15 illustrate the SPI communication protocol (source: NCN6001 demo board).
Figure 14. Programming Sequence, Chip Address = $03
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NCN6001
Protocol: Special Mode
Protocol: Standard SPI
Figure 15. MISO Read Out Sequences
DC/DC OPERATION The power conversion is based on a full bridge structure capable to handle either step up or step down power supply (Figure 16). The operation is fully automatic and, beside the
VCC 6 10 mF C1 GND CMD_1.8V CMD_3.0V CMD_5.0V CMD_STOP MIXED LOGIC/ANALOG BLOCK G_Q1 Q3 G_Q3 10 Q5 L1 22 mH Q6 Q4 GND 12 Q1 Q2 GND
output voltage programming, does not need any further adjustments.
CRD_VCC 13 Q7 C2 10 mF
G_HIZ G_Q4 G_Q2 G_Q7
11
PWR_GND GND
Figure 16. Basic DC/DC Converter
In order to achieve the 250 ms max time to discharge CRD_VCC to 400 mV called by the EMV specifications, an active pull down NMOS is provided (Q7) to discharge the
external CRD_VCC reservoir capacitor. This timing is guaranteed for a 10 mF maximum load reservoir capacitor value (Figure 4).
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NCN6001
The system operates with a two cycles concept (all comments are referenced to Figure 16 and Figure 17): 1 - Cycle 1 Q1 and Q4 are switched ON and the inductor L1 is charged by the energy supplied by the external battery. During this phase, the pair Q2/Q3 and the pair Q5/Q6 are switched OFF. The current flowing the two MOSFET Q1 and Q4 is internally monitored and will be switched OFF when the Ipeak value (depending upon the programmed output voltage value) is reached. At this point, Cycle 1 is completed and Cycle 2 takes place. The ON time is a function of the battery voltage and the value of the inductor network (L and Zr) connected across pins 10/11. A 4 ms timeout structure ensures the system does run in a continuous Cycle 1 loop 2 - Cycle 2 Q2 and Q3 are switched ON and the energy stored into the inductor L1 is dumped into the external load through Q2. During this phase, the pair Q1/Q4 and the pair Q5/Q6 are switched OFF. The current flow period is constant (900 ns typical) and Cycle 1 repeats after this time if the CRD_VCC voltage is below the specified value. When the output voltage reaches the specified value (1.8 V, 3.0 V or 5.0 V), Q2 and Q3 are switched OFF immediately to avoid over voltage on the output load. In the meantime, the two extra NMOS Q5 and Q6 are switched ON to fully discharge any current stored into the inductor, avoiding ringing and voltage spikes over the system. Figure 17 illustrates the theoretical waveforms present in the DC/DC converter.
Charge CRD_VCC ton toff
CRD_VCC Charged (Time is Not to Scale)
Next CRD_VCC Charge
Q1/Q4 Q2/Q3 Q5/Q6 Ipeak IL CRD_VCC Voltage Regulated Vripple
CRD_VCC
Figure 17. Theoretical DC/DC Operating Waveforms
When the CRD_VCC is programmed to zero volt, or when the card is extracted from the socket, the active pull down Q7 rapidly discharges the output reservoir capacitor, making sure the output voltage is below 0.4 V when the card slides across the ISO contacts. Based on the experiments carried out during the NCN6001 characterization, the best comprise, at time of printing this document, is to use two 4.7 mF/10 V/ ceramic/X7R capacitors in parallel to achieve the CRD_VCC filtering. The ESR will not extend 50 mW over
the temperature range and the combination of standard parts provide an acceptable -20% to +20% tolerance, together with a low cost. Table 9 gives a quick comparison between the most common type of capacitors. Obviously, the capacitor must be SMD type to achieve the extremely low ESR and ESL necessary for this application. Figure 18 illustrates the CRD_VCC ripple observed in the NCN6001 demo board depending upon the type of capacitor used to filter the output voltage.
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NCN6001
Table 9. Ceramic/Electrolytic Capacitors Comparison
Manufacturers MURATA MURATA VISHAY VISHAY - Type/Series CERAMIC/GRM225 CERAMIC/GRM225 Tantalum/594C/593C Electrolytic/94SV Electrolytic Low Cost Format 0805 0805 - - - Max Value 10 mF/6.3 V 4.7 mF/6.3 V 10 mF/16 V 10 mF/10 V 10 mF/10 V Tolerance -20%/+20% -20%/+20% - -20%/+20% -35%/+50% Typ. Z @ 500 kHz 30 mW 30 mW 450 mW 400 mW 2.0 W
The DC/DC converter is capable to start with a full load connected to the CRD_VCC output as depicted in Figure 19.
In this example, the converter is fully loaded when the system starts from zero.
Test Conditions: Cout = 2x 4.7 mF/6 V/ceramic X7R, Temp = +25C Iout = Maximum Specification
Figure 18. Typical CRD_VCC Ripple Voltage
Figure 19. Output Voltage Startup Under Full Load Conditions
74 72 70 68 Eff(%) 66 64 62 60 58 2.5 3.0 3.5 4.0 Vbat (V) 4.5 5.0 5.5 Vout = 1.8 V Vout = 3.0 V Vout = 5.0 V
The curves illustrate the typical behavior under full output current load (35 mA, 60 mA and 65 mA), according to EMV specifications.
Lout = 22 mH/ESR = 2 W
Figure 20. CRD_VCC Efficiency as a Function of the Input Supply Voltage
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NCN6001
During the operation, the inductor is subject to high peak current as depicted Figure 21 and the magnetic core must sustain this level of current without damage. In particular, the ferrite material shall not be saturated to avoid uncontrolled current spike during the charge up cycle. Moreover, since the DC/DC efficiency depends upon the losses developed into the active and passive components, selecting a low ESR inductor is preferred to reduce these losses to a minimum.
Test Conditions: Input VCC voltage = 5.0 V Current = 200 mA/div Tamb = +20C
Figure 21. Typical Inductor Current
According to the ISO7816-3 and EMV specifications, the interface shall limits the CRD_VCC output current to 200 mA maximum, under short circuit conditions. The NCN6001 supports such a parameter, the limit being depending upon the input and output voltages as depicted in Figure 22.
180 160 140 120 Iout 100 80 60 40 20 0 2 3 4 Vbat Iomax = F (Vbat) 5 6 Vo = 1.8 V Vo = 3.0 V Vo = 5.0 V
On the other hand, the circuit is designed to make sure no over current exist over the full temperature range. As a matter of fact, the output current limit is reduced when the temperature increases: see Figure 23.
160 150 140 Iout (mA) 130 120 110 100 -25 Vo = 3.0 V Vo = 5.0 V
Vo = 1.8 V
-5
15
35
55
75
95
115
TEMPERATURE (C)
Figure 22. Output Current Limits
Figure 23. Output Current Limit as a Function of the Temperature
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NCN6001
SMART CARD CLOCK DIVIDER The main purpose of the built-in clock generator is threefold: 1. Adapts the voltage level shifter to cope with the different voltages that might exist between the MPU and the Smart Card. 2. Provides a frequency division to adapt the Smart Card operating frequency from the external clock source. 3. Controls the clock state according to the smart card specification. In addition, the NCN6001 adjusts the signal coming from the microprocessor to get the Duty Cycle window as defined by the ISO7816-3 specification. The byte content of the SPI port, B2 & B3, fulfills the programming functions when CS is Low as depicted in Figure 25 and Figure 24. The clock input stage (CLK_IN) can handle a 20 MHz frequency maximum signal, the divider being capable to provide a 1:4 ratio. Of course, the ratio must be defined by the engineer to cope with the Smart Card considered in a given application and, in any case, the output clock [CRD_CLK] shall be limited to 20 MHz maximum. In order to minimize the dI/dt and dV/dV developed in the CRD_CLK line, the output stage includes a special function to adapt the slope of the clock signal for different applications. This function is programmed by the MOSI register (Table 2: WRT_REG Bits Definitions and Functions) whatever be the clock division. In order to avoid any duty cycle out of the smart card ISO7816-3 specification, the divider is synchronized by the
VCC CLK_IN U1 DIGITAL_MUX B2 B3 Programming CRD_CLK Division SYNC A ASYNC B OUT SEL LEVEL SHIFTER AND CONTROL CRD_CLK
last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio (Figure 24). Consequently, the output CRD_CLK frequency division can be delayed by four CLK_IN pulses and the microcontroller software must take this delay into account prior to launch a new data transaction. On the other hand, the output signal Duty Cycle cannot be guaranteed 50% if the division ratio is 1 and if the input Duty Cycle signal is not within the 46-56% range. The input signals CLK_IN and MOSI/b3 are automatically routed to the level shifter and control block according to the mode of operation.
CLOCK_IN CLOCK : 1 CLOCK : 2 CLOCK : 4 B2 B3 Clock is updated upon CLOCK: 4 rising edge CRD_CLK CLOCK programming is activated by the B2 + B3 logic state These bits program CLOCK = 1:1 ratio Internal CLOCK Divider
Figure 24. Typical Clock Divider Synchronization
CRD_VCC
SYNC
B0 B1
Programming CRD_CLK Slope NOTE: Bits [B0...B3] come from SPI data
Figure 25. Basic Clock Divider and Level Shifter
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NCN6001
The input clock can be divided by 1/1, 1/2 or 1/4, depending upon the specific application, prior to be applied to the smart card driver. On the other hand, the positive and negative going slopes of the output clock (CRD_CLK) can be programmed to optimize the operation of the chip
Table 10. Output Clock Rise and Fall Time Selection
B0 0 0 1 1 B1 0 1 0 1 CRD_CLK Division Ratio - 1 1/2 1/4 CRD_CLK SLO_SLP Output Clock = Low 10 ns (typ.) 10 ns (typ.) 10 ns (typ.) CRD_CLK FST_SLP Output Clock = Low 2 ns (typ.) 2 ns (typ.) 2 ns (typ.)
(Table 10). The slope of the output clock can be programmed on the fly, independently of either the CRD_VCC voltage or the operating frequency, but care must be observed as the CRD_RST will reflect the logic state present at MOSI/b4 register.
Figure 26. Force CRD_CLK to Low
Figure 27. Force CRD_CLK to Active Mode
Figure 28. CRD_CLK Programming
Note: Waveforms recorded without external compensation network.
Figure 29. CRD_CLK Operating Low Speed (Top Trace), Full Speed (Bottom Trace)
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NCN6001
INPUT SCHMITT TRIGGERS All the Logic Input pins have built-in Schmitt trigger circuits to protect the NCN6001 against uncontrolled operation. The typical dynamic characteristics of the related pins are depicted in Figure 30. The output signal is guaranteed to go High when the input voltage is above 0.70* VCC, and will go Low when the input voltage is below 0.30* VCC.
OUTPUT
or under voltage situation, updates the READ_REG register accordingly and forces INT pin to Low. This register can be read out by the MPU. Battery Voltage: Both the over and under voltage are detected by the NCN6001, the READ_REG register being updated accordingly. The external MPU can read the register through the MISO pin to take whatever is appropriate to cope with the situation. ESD PROTECTION The NCN6001 includes silicon devices to protect the pins against the ESD spikes voltages. To cope with the different ESD voltages developed across these pins, the built-in structures have been designed to handle either 2.0 kV, when related to the microcontroller side, or 8.0 kV when connected with the external contacts. Practically, the CRD_RST, CRD_CLK, CRD_IO, CRD_C4, and CRD_C8 pins can sustain 8.0 kV, the maximum short circuit current being limited to 15 mA. The CRD_VCC pin has the same ESD protection, but can source up to 65 mA continuously, the absolute maximum current being internally limited to 150 mA. PRINTED CIRCUIT BOARD LAYOUT Since the NCN6001 carries high speed currents together with high frequency clock, the printed circuit board must be carefully designed to avoid the risk of uncontrolled operation of the interface. A typical single sided PCB layout is provided in Figure 32 highlighting the ground technique. Dual face printed circuit board may be necessary to solve ringing and cross talk with the rest of the system.
Vbat
ON
OFF INPUT 0.3 Vbat 0.7 Vbat Vbat
Figure 30. Typical Schmitt Trigger Characteristic
SECURITY FEATURES In order to protect both the interface and the external smart card, the NCN6001 provides security features to prevent catastrophic failures as depicted hereafter. Pin Current Limitation: In the case of a short circuit to ground, the current forced by the device is limited to 15 mA for any pins, except CRD_CLK pin. No feedback is provided to the external MPU. DC/DC Operation: The internal circuit continuously senses the CRD_VCC voltage and, in the case of either over
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J1 D1 VCC GND INT TP2 C8 TP13 See Note C3 22 pF C2 GND U2 GND 10 mF GND VCC CS TP4 CRD_IO TP9 CLK_SP TP6 CLK_IN I/O TP1 TP3 MISO TP5 MOSI TP7 CRD_DET TP8 RST TP10 CLK C4 VCC TP11 TP12 TP14
VCC
R1
2.2 k
10 mF
C1
GND
CS CLK_SP1 MOSI MISO
I/O INT R8 R5 4.7 k GND VCC P1 EX_CLK R6 47 k 10 LoutL L1 22 mH LoutH 12 47 R See Note
9 1 2 3 7 8 5 4
J4 SMARTCARD_D 11 Swa 10 Swb 7 I/O 2 3 RST CLK 4 C4 8 1 C8 VCC ISO7816 5 GND GND
CRD_DET 18 VCC 20 I/O CRD_IO 19 INT CRD_RST 17 CLK_IN CRD_CLK MISO CRD_VCC 13 CS CLK_SP 15 MOSI C4/S0 14 C8/S1 16 PWR_GND 11 6 GND EN_RPU GND
CONTROL AND I/O
NCN6001
TEST BOARD SCHEMATIC DIAGRAM
Figure 31. NCN6001 Engineering Test Board Schematic Diagram
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NOTE: GND VCC R4 D4 2.2 K CRD_VCC Q1 R7 2N2222 47 k J9 GROUND 1 GND 2 Capacitor C2 and Resistor R8 are adjusted at final checkout. Depending upon the PCB layout, these two components may or may not be necessary. GND
28
J5
321
C8 4.7 mF
C7 4.7 mF
CLK_SEL
VCC
R9
GND
1k
Identify NCN6001 Demo Board
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TP15 GND
1
NCN6001
Component Side (Top)
Copper Side (Bottom)
Top side
Figure 32. NCN6001 Demo Board Printed Circuit Board Layout
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NCN6001
Table 11. Demo Board Bill of Material
Desig. C1 C2 C3 C7 C8 D1 D4 J1 J4 J5 J9 L1 P1 Q1 R1 R4 R5 R6 R7 R8 R9 TP1 TP10 TP11 TP12 TP13 TP14 TP15 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 U1 Part Type 10 mF 10 mF 22 pF 4.7 mF 4.7 mF VCC CRD_VCC CONTROL & I/O SMARTCARD CLK_SEL GROUND 22 mH EX_CLK 2N2222 2.2 k 2.2 k 4.7 k 47 k 47 k 47 R 1.0 k CLK_IN RST CLK C4 C8 VCC GND INT I/O CS MISO CLK_SPI MOSI DET CRD_IO NCN6001 Footprint 1206 1206 805 1206 1206 SIP2 SIP2 IDC50 SMARTCARD_ISO SIP3 GND_TEST 1008 SMB TO-18 805 805 805 805 805 805 805 TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT ON Semiconductor Smart Card Connector Connector Connector Inductor SMB Connector NPN Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT TEST_POINT Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares Radio Spares 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 203-4910 CoilCraft Radio Spares ON Semiconductor 1008PS-223-M 112-2993 Description Capacitor Capacitor Capacitor Capacitor Capacitor LED diode LED diode Supplier MURATA MURATA MURATA MURATA MURATA Radio Spares Radio Spares Fujitsu FCI GRM40-034X5R-475K6.3 GRM40-034X5R-475K6.3 180-8467 180-8495 FCN-704Q050-AU/M 7434-L01-35S01 Part Number GRM40-X5R-106K6.3 GRM40-X5R-106K6.3
13. All resistors are $5%, 1/4 W , unless otherwise noted. All capacitors are ceramic, $10%, 6.3 V, unless otherwise noted.
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NCN6001
VCC C1 10 mF MICROCONTROLLER
MULTIPLE SMART CARD READER
9 1 2 3 4 5 7 8 6 10 U1 CRD_DET VCC I/O CRD_IO CRD_RST INT CLK_IN CRD_CLK MOSI CRD_VC C C4/S0 CLK_SPI MISO C8/S1 GND CS EN_RPU PWR_GND Lout_L Lout_H L1 22 mH NCN6001 9 1 2 3 4 5 7 8 6 10 18 20 19 17 13 15 14 16 11 12 GND
17 18 7 2 3 5
Swa ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS Swb I/O RST CLK GND
GND
STROBE_ASYNC STROBE_SYNC
1 V 4 CC 8 C4 C8
SMARTCARD C2 10 mF GND ADDRESS = $00
GND
U2 CRD_DET VCC I/O CRD_IO INT CRD_RST CLK_IN CRD_CLK MOSI CRD_VC C C4/S0 CLK_SPI MISO C8/S1 CS GND EN_RPU PWR_GND Lout_L L2 22 mH NCN6001
17 Swa 18 GND 18 Swb 20 7 I/O 2 19 RST 17 3 CLK 13 5 GND 15 1 VCC V 14 4 CC 8 C4 16 C8 11 SMARTCARD C2 12 Lout_H 10 mF GND ISO7816 ISO7816 ISO7816
ADDRESS = $01
9 1 2 3 4 5 7 8 6 10 J5 Swa ASYNCHRONOUS 17 GND 18 20 19 17 13 15 14 16 11 12 18 Swb 7 I/O 2 RST 3 CLK 5 GND 1 VCC 4 C4 8 C8 U4 CRD_DET VCC I/O CRD_IO CRD_RST INT CLK_IN CRD_CLK MOSI CRD_VC C C4/S0 CLK_SPI MISO C8/S1 GND CS PWR_GND EN_RPU Lout_H Lout_L L5 22 mH NCN6001 9 1 2 3 4 5 7 8 6 10 9 1 2 3 4 5 7 8 6 10
SMARTCARD
C6 10 mF GND
VCC
17 Swa 18 GND 18 Swb 20 7 I/O 19 2 RST 17 3 CLK 13 5 GND 15 1 V 14 4 CC VCC 8 C4 16 C8 11 C2 SMARTCARD 12 10 mF Lout_L Lout_H GND ADDRESS = $02 L3 22 mH NCN6001 17 Swa U5 18 GND 18 Swb CRD_DET VCC 20 7 I/O CRD_IO I/O 2 19 RST INT CRD_RST 17 3 CLK_IN CRD_CLK CLK 13 5 MOSI GND CRD_VC 15 1 C C4/S0 CLK_SPI V 14 4 CC MISO C8/S1 VCC 8 C4 16 C8 CS GND 11 EN_RPU PWR_GND C2 SMARTCARD 12 10 mF Lout_L Lout_H GND L4 22 mH ADDRESS = $03 NCN6001 U3 CRD_DET VCC I/O CRD_IO INT CRD_RST CLK_IN CRD_CLK MOSI CRD_VC C C4/S0 CLK_SPI MISO C8/S1 CS GND EN_RPU PWR_GND
ISO7816
Figure 33. Typical Multiple Parallel Interfaces
The five interfaces share a common microcontroller bus, a bank of four NCN6001 supporting asynchronous card with a dedicated CS line, the fifth one being used by to the synchronous
or asynchronous transactions with a unique CS line. On the other hand, the only activated I/O pullup resistor shall be one of the Asynchronous bank.
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ISO7816
NCN6001
Table of Contents COMPACT SMART CARD INTERFACE IC . . . . . . . . . . . . MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIGITAL PARAMETERS SECTION . . . . . . . . . . . . . . . . . . POWER SUPPLY SECTION . . . . . . . . . . . . . . . . . . . . . . . . Figure 17. Theoretical DC/DC Operating Waveforms 1 6 7 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 18. Typical CRD_VCC Ripple Voltage . . . . . . . . . 23 Figure 19. CRD_VCC Efficiency as a Function of the Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 20. CRD_VCC Efficiency as a Function of the Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 21. Typical Inductor Current . . . . . . . . . . . . . . . . . 24 Figure 22. Output Current Limits . . . . . . . . . . . . . . . . . . . . 24 Figure 23. Output Current Limit as a Function of the Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 24. Typical Clock Divider Synchronization . . . . . 25 Figure 25. Basic Clock Divider and Level Shifter . . . . . . 25 Figure 26. Force CRD_CLK to Low . . . . . . . . . . . . . . . . . 26 Figure 27. Force CRD_CLK to Active Mode . . . . . . . . . . 26 Figure 28. CRD_CLK Programming . . . . . . . . . . . . . . . . . 26 Figure 29. CRD_CLK Operating Low Speed (Top Trace), Full Speed (Bottom Trace) . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 30. Typical Schmitt Trigger Characteristic . . . . . . 27 Figure 31. NCN6001 Engineering Test Board Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 32. NCN6001 Demo Board Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 33. Typical Multiple Parallel Interfaces . . . . . . . . 31 Tables Index DIGITAL PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 POWER SUPPLY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SMART CARD INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 1. WRT_REG Bits Definitions . . . . . . . . . . . . . . . . . 10 Table 2. WRT_REG Bits Definitions and Functions . . . . 11 Table 3. MOSI and MISO Bits Identifications and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Startup Default Conditions . . . . . . . . . . . . . . . . . 13 Table 5. CRD_VCC Output Voltage Range . . . . . . . . . . . 13 Table 6. I/O Pullup Resistor True Table . . . . . . . . . . . . . . 16 Table 7. Interrupt Reset Logic . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Interrupt Reset Logic Operation . . . . . . . . . . . . . 18 Table 9. Ceramic/Electrolytic Capacitors Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 10. Output Clock Rise and Fall Time Selection . . 26 Table 11. Demo Board Bill of Material . . . . . . . . . . . . . . . 30
SMART CARD INTERFACE SECTION . . . . . . . . . . . . . . . 9 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STARTUP DEFAULT CONDITIONS . . . . . . . . . . . . . . . . . 13 CARD DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CRD_VCC OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . 13 POWERUP SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . 13 POWER DOWN SEQUENCE . . . . . . . . . . . . . . . . . . . . . . 15 DATA I/O LEVEL SHIFTER . . . . . . . . . . . . . . . . . . . . . . . . 16 GENERAL PURPOSE CRD_C4 and CRD_C8 . . . . . . . . 17 INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC/DC OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SMART CARD CLOCK DIVIDER . . . . . . . . . . . . . . . . . . . INPUT SHITTY TRIGGERS . . . . . . . . . . . . . . . . . . . . . . . . SECURITY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRINTED CIRCUIT BOARD LAY OUT . . . . . . . . . . . . . . TEST BOARD SCHEMATIC DIAGRAM . . . . . . . . . . . . . . ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 27 27 27 27 28 33 34
Figures Index Figure 1. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 3. Typical Startup CRD_VCC Sequence . . . . . . . 13 Figure 4. CRD_VCC Typical Rise and Fall Time . . . . . . 14 Figure 5. Startup Sequence with ATR . . . . . . . . . . . . . . . 14 Figure 6. Typical Power Down Sequence . . . . . . . . . . . . 15 Figure 7. Basic I/O Internal Circuit . . . . . . . . . . . . . . . . . . 16 Figure 8. Typical I/O Rise and Fall Time . . . . . . . . . . . . . 16 Figure 9. Typical CRD_C4 Output Drive and Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. Basic Interrupt Function . . . . . . . . . . . . . . . . . . 18 Figure 11. Basic SPI Timings and Protocol . . . . . . . . . . . 19 Figure 12. Chip Address Decoding Protocol and MISO Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13. Basic Multi Command SPI Bytes . . . . . . . . . . 20 Figure 14. Programming Sequence, Chip Address = $03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 15. MISO Read Out Sequences . . . . . . . . . . . . . . 21 Figure 16. Basic DC/DC Converter . . . . . . . . . . . . . . . . . . 21
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NCN6001
ABBREVIATIONS
Lout_L and Lout_H Cout Class A Class B CRD_C4 CRD_C8 CRD_CLK CRD_DET CRD_IO CRD_RST CRD_VCC CRD_VCC Cs CS EMV FST_SLP GIE-CB Icc INT ISO mC MISO MOSI NC NO POR RFU SPI T0 T1 SLO_SLP VCC DC/DC External Inductor Output Capacitor 5V Smart Card 3V Smart Card Interface IC Card Digital Control Interface IC Card Digital Control Interface IC Card Clock Input Card Insertion/Extraction Detection Interface IC Card Data Link Interface IC Card RESET Input Interface IC Card Power Supply Line Card Power Supply Input Parasitic Stray Capacitance Chip Select Europay Master Card Visa CRD_CLK Fast Slope (tr and tf) Groupement Inter Economique - Carte Bancaire Current at Card VCC pin Interrupt International Standards Organization Microcontroller Master In Slave Out: Data from the Interface Master Out Slave In: Data from the External Microcontroller Normally Close Normally Open Power On Reset Reserved Future Use Serial Port Interface Smart Card Data Transfer Procedure by Bytes Smart Card Data Transfer Procedure by Strings CRD_CLK Slow Slope (tr and tf) MPU Power Supply Voltage
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NCN6001
PACKAGE DIMENSIONS
TSSOP-20 DTB SUFFIX CASE 948E-02 ISSUE B
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
20
11
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
NCN6001/D

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