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W681310
3V SINGLE-CHANNEL VOICEBAND CODEC
Data Sheet
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Publication Release Date: September 2005 Revision B13
W681310
1. GENERAL DESCRIPTION
The W681310 is a general-purpose single channel PCM CODEC with pin-selectable -Law or A-Law companding. The device is compliant with the ITU G.712 specification. It operates from a single +3V power supply and is available in 20-pin SOG, SSOP and TSSOP package options. Functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems. W681310 performance is specified over the industrial temperature range of -40C to +85C. The W681310 includes an on-chip precision voltage reference and an additional power amplifier, capable of driving 300 loads differentially up to a level of 3.544V peak-to-peak. The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The data transfer protocol supports both long-frame and short-frame synchronous communications for PCM applications, and IDL and GCI communications for ISDN applications. W681310 accepts eight master clock rates between 256 kHz and 4.800 MHz, and an on-chip pre-scaler automatically determines the division ratio for the required internal clock. For fast evaluation and prototyping purposes, the W681310DK development kit is available.
2. FEATURES
* * * * * * * * * * * Single +3V power supply (2.7V to 5.25V) Typical power dissipation of 10 mW, power-down mode of 0.5 W Fully-differential analog circuit design On-chip precision reference of 0.886 V for a -5 dBm TLP at 600 Push-pull power amplifiers with external gain adjustment with 300 load capability Eight master clock rates of 256 kHz to 4.800 MHz Pin-selectable -Law and A-Law companding (compliant with ITU G.711) CODEC A/D and D/A filtering compliant with ITU G.712 Industrial temperature range (-40C to +85C) Packages: 20-pin SOG (SOP), SSOP and TSSOP Pb-Free package options available
*
* * * * * * * * * * *
ApplIcations
VoIP, Voice over Networks Digital telephone systems and communication
Wireless voice devices PABX/SOHO systems Local loop card SOHO routers Fiber-to-curb equipment Enterprise phones ISDN equipment Modems/PC cards Digital Voice Recorders
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W681310
3. BLOCK DIAGRAM
Receive PCM Interface
BCLKR FSR PCMR BCLKT FST PCMT
Re Int PC cei erf M ve ace Transmit PCM Interface Tra Int ns PC erf mitM ace G.712 CODEC G.711 /A -Law
PAO+ PAOPAI RO ROAO AI+ AI-
/A-Law VREF VAG
512 kHz MCLK
256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz 4096 kHz & 4800 kHz
Pre -Scaler scaler
256 kHz 8 kHz
Voltage reference
Power Conditioning
VDD
PUI
VSS
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Publication Release Date: September 2005 Revision B13
W681310
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM .............................................................................................................................. 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION............................................................................................................ 8 7.1. Transmit Path ................................................................................................................................ 8 7.2. Receive Path ................................................................................................................................. 9 7.3. Power Management....................................................................................................................... 9 7.3.1. Analog and Digital Supply ..................................................................................................... 10 7.3.2. Analog Ground Reference Bypass ....................................................................................... 10 7.3.3. Analog Ground Reference Voltage Outpt ............................................................................. 10 7.4. PCM INTERFACE ....................................................................................................................... 10 7.4.1. Long Frame Sync.................................................................................................................. 11 7.4.2. Short Frame Sync ................................................................................................................. 11 7.4.3. General Circuit Interface (GCI) ............................................................................................. 11 7.4.4. Interchip Digital Link (IDL)..................................................................................................... 12 7.4.5. System Timing ...................................................................................................................... 12 8. TIMING DIAGRAMS.......................................................................................................................... 13 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20 9.1. Absolute Maximum Ratings ......................................................................................................... 20 9.2. Operating Conditions ................................................................................................................... 20 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21 10.1. General Parameters .................................................................................................................. 21 10.2. Analog Signal Level and Gain Parameters ............................................................................... 22 10.3. Analog Distortion and Noise Parameters .................................................................................. 23 10.4. Analog Input and Output Amplifier Parameters......................................................................... 24 10.5. DIGITAL I/O ...............................................................................................................................26 10.5.1. -Law Encode Decode Characteristics............................................................................... 26 10.5.2. A-Law Encode Decode Characteristics .............................................................................. 27 10.5.3. PCM Codes for Zero and Full Scale ................................................................................... 28 10.5.4. PCM Codes for 0dBm0 Output ........................................................................................... 28 11. TYPICAL APPLICATION CIRCUIT................................................................................................. 29 12. PACKAGE SPECIFICATION .......................................................................................................... 31 -4-
W681310
12.1. 20L SOG (SOP)-300mil ............................................................................................................. 31 12.2. 20L SSOP-209 mil ..................................................................................................................... 32 12.3. 20L TSSOP - 4.4X6.5mm .......................................................................................................... 33 13. ORDERING INFORMATION........................................................................................................... 34 14. VERSION HISTORY ....................................................................................................................... 35
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Publication Release Date: September 2005 Revision B13
W681310
5. PIN CONFIGURATION
VREF ROPAI PAOPAO+ VDD FSR PCMR BCLKR PUI
1 2 3 4 5 6 7 8 9 10
20 19 18
SINGLE CHANNEL CODEC
17 16 15 14 13 12 11
VAG AI+ AIAO /A-Law /A VSS FST PCMT BCLKT MCLK
SOG/SSOP/TSSOP
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W681310
6. PIN DESCRIPTION
Pin Name VREF ROPAI PAOPAO+ VDD FSR Pin No. 1 2 3 4 5 6 7 Functionality This pin is used to bypass the on-chip VDD/2 voltage reference. It needs to be decoupled to VSS through a 0.1 F ceramic decoupling capacitor. No external loads should be tied to this pin. Inverting output of the receive smoothing filter. This pin can typically drive a 2 k load to 0.886 volt peak referenced to the analog ground level. This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage. Inverting power amplifier output. The PAO- and PAO+ can drive a 300 load differentially to 1.772 volt peak referenced to the VAG voltage level. Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300 load differentially to 1.772 volt peak referenced to the VAG voltage level. Power supply. This pin should be decoupled to VSS with a 0.1F ceramic capacitor. 8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit and receive are synchronous operations. PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins. PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD. This pin can also be tied to the BCLKT when transmit and receive are synchronous operations. Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS, the part is powered down. System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz, 4096 kHz & 4800 kHz. For a better performance, it is recommended to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the case of 256 and 512 kHz frequency. PCM transmit bit clock input pin. This pin accepts clocks of 512 kHz to 6176 kHz in the GCI mode and 256 kHz to 4800kHz in all other PCM modes. PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins. 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes. This is the supply ground. This pin should be connected to 0V. Compander mode select pin. -Law companding is selected when this pin is tied to VDD. A-Law companding is selected when this pin is tied to VSS. Analog output of the first gain stage in the transmit path. Inverting input of the first gain stage in the transmit path. Non-inverting input of the first gain stage in the transmit path. Mid-Supply analog ground pin, which supplies a VDD/2 volt reference voltage for all-analog signal processing. This pin should be decoupled to VSS with a 0.01F capacitor. This pin becomes high impedance when the chip is powered down. Publication Release Date: September 2005 Revision B13
PCMR BCLKR
8 9
PUI MCLK
10 11
BCLKT PCMT FST VSS /A-Law AO AIAI+ VAG
12 13 14 15 16 17 18 19 20
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W681310
7. FUNCTIONAL DESCRIPTION
W681310 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a complete -Law and A-Law compander. The -Law and A-Law companders are designed to comply with the specifications of the ITU-T G.711 recommendation. The block diagram in section 3 shows the main components of the W681310. The chip consists of a PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats. The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The power conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. The main CODEC block diagram is shown in section 3.
VA VAG G
+
+
PAO+ PAO PAI
Receive Path
8 D/A Converter w + fC= 3400Hz H Smoot Smoothing n Filter 1 Smoothing Smoot nFilter 2
RO -
/A/ACont Control ol
Transmit Path
AO 8 /A /A- Control Cont A/D Converter ++ fC = 200Hz fC = 200 High Pass H High Filt Filter Pas fC= 3400Hz = Ant-Aliasing H Ant-Aliasi i Filter n Ant-Aliasi Ant-Aliasing Filter AI+ AI -
Figure 7.1 The W681310 Signal Path
7.1. Transmit Path
The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain setting (see application examples in section 11). The device has an input operational amplifier whose output is the input to the encoder section. If the input amplifier is not required for operation it can be powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. The AO pin is selected as an input when AI+ is tied to VDD and the AI- pin is selected as an input when AI+ is tied to VSS (see Table 7.1). -8-
W681310
AI+ VDD 1.2 to VDD-1.2 VSS
Input Amplifier Powered Down Powered Up Powered Down
Input AO AI+, AIAI-
Table 7.1 Input Amplifier Modes of operation
When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the analog ground voltage VAG. The output of the input amplifier is fed through a 3.4 kHz switched capacitor low pass filter to prevent aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is digitized. The signal is converted into a compressed 8-bit digital representation with either -Law or A-Law format. The -Law or A-Law format is pin-selectable through the /A-Law pin. The compression format can be selected according to Table 7.2.
/A-Law Pin VSS VDD
Format A-Law -Law
Table 7.2. Pin-selectable Compression Format
The digital 8-bit -Law or A-Law samples are fed to the PCM interface for serial transmission at the sample rate supplied by the external frame sync FST.
7.2. Receive Path
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed through the pin-selectable -Law or A-Law expander and converted to analog samples. The mode of expansion is selected by the /A-Law pin as shown in Table 7.2. The analog samples are filtered by a low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification. A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered to provide the receive output signal RO-. The RO- output can be externally connected to the PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By using external resistors (see section 11 for examples), various gain settings of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting PAI to VDD.
7.3. POWER MANAGEMENT
Publication Release Date: September 2005 Revision B13
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W681310
7.3.1. Analog and Digital Supply
The power supply for the analog and digital parts of the W681310 must be 2.7V to 5.25V. This supply voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 F ceramic capacitor.
7.3.2. Analog Ground Reference Bypass
The system has an internal precision voltage reference which generates the VDD/2 mid-supply analog ground voltage. This voltage needs to be decoupled to VSS at the VREF pin through a 0.1 F ceramic capacitor.
7.3.3. Analog Ground Reference Voltage Outpt
The analog ground reference voltage is available for external reference at the VAG pin. This voltage needs to be decoupled to VSS through a 0.01 F ceramic capacitor. The analog ground reference voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing.
7.4. PCM INTERFACE
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of operation of the interface are shown in Table 7.3.
BCLKR 64 kHz to 4.800 MHz VSS VSS VDD VDD
FSR 8 kHz VSS VDD VSS VDD
Interface Mode Long or Short Frame Sync ISDN GCI with active channel B1 ISDN GCI with active channel B2 ISDN IDL with active channel B1 ISDN IDL with active channel B2
Table 7.3 PCM Interface mode selections
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W681310
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 64 kHz to 4.800 MHz clock and connecting the FSR or FST pin to the 8 kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 sec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section.
7.4.2. Short Frame Sync
The W681310 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the bit-clock, the W681310 starts clocking out the data on the PCMT pin, which will also change from high to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway the LSB. The Short Frame Sync operation of the W681310 is based on an 8-bit data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK. The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section. The GCI interface supports bit clocks of 512 kHz to 6176 kHz for data rates of 256 kHz to 3088 kHz.
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Publication Release Date: September 2005 Revision B13
W681310
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not used for data transmission and also in the time slot of the unused channel. For more timing information, see the timing section.
7.4.5. System Timing
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz, 4096 kHz & 4800 kHz master clock rates. The system clock is supplied through the master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and 8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W681310 will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become low impedance.
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W681310
8. TIMING DIAGRAMS
T FTRH M T F T R SM TM CK H TM CK L T R ISE T FA L L
M CLK
TM CK T FS T F SL T FTRH T FTRS T FTFH TBCK H TBCK L
F ST
BCLK T
0
T FD TD
1
2
3
T B DTD
4
5
6
7
8
T H ID T H ID
0
TBCK
1
PC M T
D7 M SB
D6
D5
D4
D3
D2
D1 D0 L SB
T FS T F SL
F SR
T FRRH T FRRS T FRFH
TBCK H
TBCK L
BCLK R
0
1
2
3
4
5
6
7
8
0
TBCK
1
PC M R
D7 M SB
TDRS
D6
D5
TDRH
D4
D3
D2
D1
D0 L SB
Figure 8.1 Long Frame Sync PCM Timing
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W681310
SYMBOL 1/TFS TFSL 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFDTD TBDTD THID DESCRIPTION FST, FSR Frequency FST / FSR Minimum Low Width BCLKT, BCLKR Frequency BCLKT, BCLKR HIGH Pulse Width BCLKT, BCLKR LOW Pulse Width BCLKT 0 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 1 Falling edge Setup Time BCLKT 2 Falling Edge to FST Falling Edge Hold Time FST Rising Edge to Valid PCMT Delay Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the Later of FST Falling Edge, or BCLKT 8 Falling Edge to PCMT Output High Impedance TFRRH TFRRS TFRFH TDRS TDRH BCLKR 0 Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR 1 Falling edge Setup Time BCLKR 2 Falling Edge to FSR Falling Edge Hold Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge 20 80 50 0 50 --------------------ns ns ns ns ns
1
MIN --TBCK 64 50 50 20 80 50 ----10
TYP 8 -------------------
MAX --4800 ----------60 60 60
UNIT kHz sec kHz ns ns ns ns ns ns ns ns
Table 8.1 Long Frame Sync PCM Timing Parameters
1
TFSL must be at least TBCK - 14 -
W681310
T FTRHM T F T R SM TM CK H TM CK L T R ISE T FA L L
M CLK
TM CK T FTFH T FTFS T FS
F ST
T FTRH T FTRS TBCK H TBCK L
BCLK T
-1
0
1
T B D TD
2
3
TBDTD
4
5
6
7
8
T H ID
0
TBCK
1
PC M T
D7 M SB
D6
D5
D4
D3
D2
D1 D0 L SB
T FS T FRFH T FRFS
F SR
T FRRH TFRRS TBCK H TBCK L
BCLK R
-1
0
1
2
3
4
5
6
7
8
0
TBCK
1
PC M R
D7 M SB
TDRS
D6
D5
T DRH
D4
D3
D2
D1
D0 L SB
Figure 8.2 Short Frame Sync PCM Timing
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Publication Release Date: September 2005 Revision B13
W681310
SYMBOL 1/TFS 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFTFS TBDTD THID TFRRH TFRRS TFRFH TFRFS TDRS TDRH
DESCRIPTION FST, FSR Frequency BCLKT, BCLKR Frequency BCLKT, BCLKR HIGH Pulse Width BCLKT, BCLKR LOW Pulse Width BCLKT -1 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 0 Falling edge Setup Time BCLKT 0 Falling Edge to FST Falling Edge Hold Time FST Falling Edge to BCLKT 1 Falling Edge Setup Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from BCLKT 8 Falling Edge to PCMT Output High Impedance BCLKR -1 Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR 0 Falling edge Setup Time BCLKR 0 Falling Edge to FSR Falling Edge Hold Time FSR Falling Edge to BCLKR 1 Falling Edge Setup Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge
MIN --64 50 50 20 80 50 50 10 10 20 80 50 50 0 50
TYP 8 -------------------------------
MAX --4800 ------------60 60 -------------
UNIT kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 8.2 Short Frame Sync PCM Timing Parameters
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W681310
TFS
F ST
T F SR H
T F SF H T F SR S 0 1 2 T B D TD 3 4 5 6 TB DTD D5 D4 D3 D2 D1 D0 L SB T DRS TDRH D5 D4 D3 D2 D1 D0 L SB D7 M SB 7 8 9 T H ID 10 11 12 13 14 TBCK H 15 16 TBCK L 17 18 T H ID D1 D0 L SB TDRS D6 D5 TDRH D4 D3 D2 D1 D0 L SB
BCLK T
-1
TB DTD D7 M SB D6 D5
TB DTD
TBCK
PC M T
D7 M SB
D6
D4 D3 D2
PC M R
D7 M SB
D6
BCH = 0 B 1 C hannel
BCH = 1 B 2 C hannel
Figure 8.3 IDL PCM Timing
SYMBOL 1/TFS 1/TBCK TBCKH TBCKL TFSRH TFSRS TFSFH TBDTD THID
DESCRIPTION FST Frequency BCLKT Frequency BCLKT HIGH Pulse Width BCLKT LOW Pulse Width BCLKT -1 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 0 Falling edge Setup Time BCLKT 0 Falling Edge to FST Falling Edge Hold Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the BCLKT 8 Falling Edge (B1 channel) or BCLKT 18 Falling Edge (B2 Channel) to PCMT Output High Impedance Valid PCMR to BCLKT Falling Edge Setup Time PCMR Hold Time from BCLKT Falling Edge
MIN --256 50 50 20 60 20 10 10
TYP 8 -----------------
MAX --4800 ----------60 50
UNIT kHz kHz ns ns ns ns ns ns ns
TDRS TDRH
20 75
-----
-----
ns ns
Table 8.3 IDL PCM Timing Parameters
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Publication Release Date: September 2005 Revision B13
W681310
T FS
F ST
T F SR H
T FSF H T FSR S TBCK H TBCK L
BCLK T
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
T FDTD
T B DTD D5 D4 D3 D2
T H ID D1 D0
T B DTD D7 D6 D5
T B DTD
TBCK D1 D0 L SB
T H ID
PC M T
D7 M SB
D6
D4 D3 D2
L SB M SB TDRS TDRH D5 D4 D3 D2 D1 D0 D7 L SB M SB TDRS D6 D5 T DRH D4 D3 D2
PC M R
D7 M SB
D6
D1 D0 L SB
BCH = 0 B 1 C hannel
BCH = 1 B 2 C hannel
Figure 8.4 GCI PCM Timing
SYMBOL 1/TFST 1/TBCK TBCKH TBCKL TFSRH TFSRS TFSFH TFDTD TBDTD THID
DESCRIPTION FST Frequency BCLKT Frequency BCLKT HIGH Pulse Width BCLKT LOW Pulse Width BCLKT 0 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 1 Falling edge Setup Time BCLKT 1 Falling Edge to FST Falling Edge Hold Time FST Rising Edge to Valid PCMT Delay Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the BCLKT 16 Falling Edge (B1 channel) or BCLKT 32 Falling Edge (B2 Channel) to PCMT Output High Impedance Valid PCMR to BCLKT Rising Edge Setup Time PCMR Hold Time from BCLKT Rising Edge
Table 8.4 GCI PCM Timing Parameters
MIN --512 50 50 20 60 20 ----10
TYP 8 -------------------
MAX --6176 ----------60 60 50
UNIT kHz kHz ns ns ns ns ns ns ns ns
TDRS TDRH
20 ---
-----
--60
ns ns
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W681310
SYMBOL 1/TMCK
DESCRIPTION Master Clock Frequency
MIN ---
TYP 256 512 1536 1544 2048 2560 4096 4800
MAX ---
UNIT kHz
TMCKH / TMCK TMCKH TMCKL TFTRHM TFTRSM TRISE TFALL
MCLK Duty Operation
Cycle
for
256
kHz
45% 50 50 50 50 -----------------
55% --------50 50 ns ns ns ns ns ns
Minimum Pulse Width HIGH for MCLK(512 kHz or Higher) Minimum Pulse Width LOW for MCLK (512 kHz or Higher) MCLK falling Edge to FST Rising Edge Hold Time FST Rising Edge to MCLK Falling edge Setup Time Rise Time for All Digital Signals Fall Time for All Digital Signals
Table 8.5 General PCM Timing Parameters
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Publication Release Date: September 2005 Revision B13
W681310
9. ABSOLUTE MAXIMUM RATINGS
9.1. ABSOLUTE MAXIMUM RATINGS Condition
Junction temperature Storage temperature range Voltage Applied to any pin Voltage applied to any pin (Input current limited to +/-20 mA) VDD - VSS 1500C -650C to +1500C (VSS - 0.3V) to (VDD + 0.3V) (VSS - 1.0V) to (VDD + 1.0V) -0.5V to +6V
Value
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
9.2. OPERATING CONDITIONS Condition
Industrial operating temperature Supply voltage (VDD) Ground voltage (VSS)
0
Value
-40 C to +85 C +2.7V to +5.25V 0V
0
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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W681310
10. ELECTRICAL CHARACTERISTICS
10.1. GENERAL PARAMETERS
Symbol VIL VIH VOL VOH IDD ISB Ipd IIL IOL CIN COUT Parameters Input LOW Voltage Input HIGH Voltage PCMT Output LOW Voltage PCMT Output HIGH Voltage VDD Current (Operating) - ADC + DAC VDD Current (Standby) VDD Current (Power Down) Input Leakage Current PCMT Output Leakage Current Digital Input Capacitance PCMT Output Capacitance
1. Typical values: TA = 25C , VDD = 3.0 V 2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested.
Conditions
Min (2)
Typ (1)
Max (2) 0.6
Units V V
2.2 IOL = 1.6 mA IOL = -1.6 mA No Load FST & FSR =Vss ; PUI=VDD PUI= Vss VSSV V mA A A A A pF pF
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Publication Release Date: September 2005 Revision B13
W681310
10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS
VDD=2.7V to 3.6V; VSS=0V; TA=-40C to +85C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz; FST=FSR=8kHz Synchronous operation.
PARAMETER
SYM.
CONDITION
TYP.
TRANSMIT (A/D) MIN. MAX. ------+0.20
RECEIVE (D/A) MIN. -------0.20 MAX. ------+0.20
UNIT
Absolute Level Max. Transmit Level Absolute Gain (0 dBm0 @ 1020 Hz; TA=+25C) Absolute Gain variation with Temperature Frequency Response, Relative to 0dBm0 @ 1020 Hz
LABS TXMAX GABS
0 dBm0 = -5dBm @ 600 3.17 dBm0 for -Law 3.14 dBm0 for A-Law 0 dBm0 @ 1020 Hz; TA=+25C
0.616 0.436 0.8873 0.8843 0
-------0.20
VPK VRMS VPK VPK dB
GABST
TA=0C to TA=+70C TA=-40C to TA=+85C
0
-0.05 -0.10
+0.05 +0.10 -40 -30 -26 -0.4 +0.2 +0.2 +0.1 0 -14 -32 +0.3 +0.6 +1.6
-0.05 -0.10 -0.5 -0.5 -0.5 -0.5 -0.20 -0.4 -0.8 -------0.2 -0.4 -1.6
+0.05 +0.10 0 0 0 0 +0.2 +0.15 0 0 -14 -30 +0.2 +0.4 +1.6
dB
GRTV
15 Hz 50 Hz 60 Hz 200 Hz 300 to 3000 Hz 3300 Hz 3400 Hz 3600 Hz 4000 Hz 4600 Hz to 100 kHz
---------------------------
-------1.4 -0.15 -0.35 -0.8 -------0.3 -0.6 -1.6
dB
Gain Variation vs. Level Tone (1020 Hz relative to -10 dBm0)
GLT
+3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0
dB
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W681310
10.3. ANALOG DISTORTION AND NOISE PARAMETERS
VDD=2.7V to 3.6V; VSS=0V; TA=-40C to +85C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz FST=FSR=8kHz Synchronous operation.
PARAMETER Total Distortion vs. Level Tone (1020 Hz, -Law, C-Message Weighted) Total Distortion vs. Level Tone (1020 Hz, A-Law, Psophometric Weighted)
SYM. DLT
CONDITION +3 dBm0 0 dBm0 to -30 dBm0 -40 dBm0 -45 dBm0
TRANSMIT (A/D) MIN. 34 33.5 30 25 30 35 34.5 28.5 13.5 -----------------------47 TYP. ----------------MAX. -----------------
RECEIVE (D/A) MIN. 34 36 30 25 30 36 34.2 30 15 -----------------30 -40 -30 -47 TYP. ----------------MAX. -----------------
UNIT dBC
DLTA
-3 dBm0 -6 dBm0 to -27 dBm0 -34 dBm0 -40 dBm0 -55 dBm0
dBp
Spurious Out-Of-Band at RO- (300 Hz to 3400 Hz @ 0dBm0) Spurious In-Band (700 Hz to 1100 Hz @ 0dBm0) Intermodulation Distortion (300 Hz to 3400 Hz -4 to -21 dBm0 Crosstalk (1020 Hz @ 0dBm0) Absolute Group Delay Group Delay Distortion (relative to group delay @ 1200 Hz)
DSPO
4600 Hz to 7600 Hz 7600 Hz to 8400 Hz 8400 Hz to 100000 Hz
dB
DSPI
300 to 3000 Hz
dB
DIM
Two tones
---
---
-41
---
---
-41
dB
DXT
--1200Hz 500 Hz 600 Hz 1000 Hz 2600 Hz 2800 Hz -----------------
-------------------
-75 360 750 380 130 130 750 19 -68
-------------------
-------------------
-75 240 750 370 120 120 750 15 -75
dBm0 sec sec
ABS D
Idle Channel Noise
NIDL
-Law; C-message A-Law; Psophometric
dBrnc0 dBm0p
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Publication Release Date: September 2005 Revision B13
W681310
10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS
VDD=2.7V to 3.6V; VSS=0V; TA=-40C to +85C; all analog signals referred to VAG; PARAMETER AI Input Offset Voltage AI Input Current AI Input Resistance AI Input Capacitance AI Common Mode Input Voltage Range AI Common Mode Rejection Ratio AI Amp Gain Bandwidth Product AI Amp DC Open Loop Gain AI Amp Equivalent Input Noise AO Output Voltage Range Load Resistance Load Capacitance AO & RO Output Current RO- Output Resistance RO- Output Offset Voltage Analog Ground Voltage VAG Output Resistance Power Supply Rejection Ratio (0 to 100 kHz to VDD, Cmessage) PAI Input Offset Voltage PAI Input Current PAI Input Resistance PAI Amp Gain Bandwidth Product Output Offset Voltage SYM. VOFF,AI IIN,AI RIN,AI CIN,AI VCM,AI CMRRTI GBWTI GTI NTI VTG RLDTGRO CLDTGRO IOUT1 RROVOFF,ROVAG RVAG PSRR CONDITION AI+, AIAI+, AIAI+, AI- to VAG AI+, AIAI+, AIAI+, AIAO, RLD10k AO, RLD10k C-Message Weighted RLD=2k to VAG AO, RO to VAG AO, RO 0.5 AO,RO- VDD-0.5 RO-, 0 to 3400 Hz RO- to VAG Relative to VSS Within 25mV change Transmit Receive VOFF,PAI IIN,PAI RIN,PAI GBWPI VOFF,PO PAI PAI PAI to VAG PAO- no load PAO+ to PAOMIN. ----10 --1.2 --------0.4 2 --1.0 ----VDD/2-0.1 --40 40 ----10 ----TYP. --0.1 ------60 2150 95 -24 --------1 --VDD/2 12.5 60 60 --0.05 --1000 --MAX. 25 1.0 --10 VDD-1.2 --------VDD-0.4 --200 ----25 VDD/2+0. 1 25 ----25 1.0 ----50 mV A M kHz mV UNIT. mV A M pF V dB kHz dB dBrnC V k pF mA mV V dBC
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W681310
PARAMETER Load Resistance Load Capacitance PAO Output Current PAO Output Resistance PAO Differential Gain PAO Differential Signal to Distortion C-Message weighted PAO Power Supply Rejection Ratio (0 to 25 kHz to VDD, Differential out)
SYM. RLDPO CLDPO IOUTPAO RPAO
CONDITION PAO+, PAOdifferentially PAO+, PAOdifferentially 0.4 PAO+,PAO-- VDD0.4 PAO+ to PAORLD=300, +3dBm0, 1 kHz, PAO+ to PAOZLD=300 ZLD=100nF + 20 ZLD=100nF + 100
MIN. 300 --6.0 ---0.2 45 ----40 ---
TYP. ------1 0 60 40 40 55 40
MAX. --1000 ----+0.2 -----------
UNIT. pF mA dB dBC
GPAO DPAO
PSRRP
AO
0 to 4 kHz 4 to 25 kHz
dB
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Publication Release Date: September 2005 Revision B13
W681310
10.5. DIGITAL I/O 10.5.1. -Law Encode Decode Characteristics
Normalized Encode Decision Levels Digital Code D7 Sign 8159 7903
:
Normalized D6 Chord 0 D5 Chord 0 D4 Chord 0 D3 Step 0 D2 Step 0 D1 Step 0 D0 Step 0 8031 : 1 0 0 0 1 1 1 1 4191 : 1 0 0 1 1 1 1 1 2079 : 1 0 1 0 1 1 1 1 1023 : 1 0 1 1 1 1 1 1 495 : 1 1 0 0 1 1 1 1 231 : 1 1 0 1 1 1 1 1 99 : 1 1 1 0 1 1 1 1 33 : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 2 0 Decode Levels
1
4319 4063
:
2143 2015
:
1055 991
:
511 479
:
239 223
:
103 95
:
35 31
:
3 1 0
Notes: Sign bit = 0 for negative values, sign bit = 1 for positive values
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W681310
10.5.2. A-Law Encode Decode Characteristics
Normalized Encode Decision Levels 4096 3968
:
Digital Code D7 Sign D6 Chord D5 Chord D4 Chord D3 Step D2 Step D1 Step D0 Step
Normalized Decode Levels
1
0
1
0
1
0
1
0
4032 :
2048 2048
:
1
0
1
0
0
1
0
1
2112 :
1088 1024
:
1
0
1
1
0
1
0
1
1056 :
544 512
:
1
0
0
0
0
1
0
1
528 :
272 256
:
1
0
0
1
0
1
0
1
264 :
136 128
:
1
1
1
0
0
1
0
1
132 :
68 64
:
1
1
1
0
0
1
0
1
66 :
2 0
1
1
0
1
0
1
0
1
1
Notes: 1. Sign bit = 0 for negative values, sign bit = 1 for positive values 2. Digital code includes inversion of all even number bits
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Publication Release Date: September 2005 Revision B13
W681310
10.5.3. PCM Codes for Zero and Full Scale
-Law Level + Full Scale + Zero - Zero - Full Scale Sign bit (D7) 1 1 0 0 Chord bits (D6,D5,D4) 000 111 111 000 Step bits (D3,D2,D1,D0) 0000 1111 1111 0000 Sign bit (D7) 1 1 0 0 A-Law Chord bits (D6,D5,D4) 010 101 101 010 Step bits (D3,D2,D1,D0) 1010 0101 0101 1010
10.5.4. PCM Codes for 0dBm0 Output
-Law Sample 1 2 3 4 5 6 7 8 Sign bit (D7) 0 0 0 0 1 1 1 1 Chord bits (D6,D5,D4) 001 000 000 001 001 000 000 001 Step bits (D3,D2,D1,D0) 1110 1011 1011 1110 1110 1011 1011 1110 Sign bit (D7) 0 0 0 0 1 1 1 1 A-Law Chord bits (D6,D5,D4) 011 010 010 011 011 010 010 011 Step bits (D3,D2,D1,D0) 0100 0001 0001 0100 0100 0001 0001 0100
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W681310
11. TYPICAL APPLICATION CIRCUIT
VDD 0.1 uF
DIFFERENTIAL AUDIO IN +
1.0 uF
27K
17 18
AO AIAI+ VAG VREF ROPAI PAO-
VDD
27K
U2
6
1.0 uF
27K
27K
19 20 1 27K 27K 2 3 4 5
FST BCLKT PCMT MCLK PCMR BCLKR FSR
14 12 13 11 8 9 7
8 KHz Frame Sy nc 2.048 MHz Bit Clock PCM OUT PCM IN
0.01 uF
0.1 uF
VSS
DIFFERENTIAL AUDIO OUT RL > 150 ohms +
PAO+ W681310
u/A PUI
16 10
MODE SELECT POWER CONTROL
Figure 11.1 Typical circuit for Differential Analog I/O's
15 VDD 0.1 uF VDD 6
27K 1.0 uF AUDIO IN 1.0 uF 27K 27K 27K
U3 17 18 19 20 1 2 27K 27K 3 4 5 AO AIAI+ VAG VREF ROPAI PAO-
FST BCLKT PCMT MCLK PCMR BCLKR FSR
14 12 13 11 8 9 7
8 KHz Frame Sy nc 2.048 MHz Bit Clock PCM OUT PCM IN
0.01 uF AUDIO OUT RL > 2K ohms AUDIO OUT RL > 150 ohms
0.1 uF
VSS
PAO+ W681310
u/A PUI
16 10
MODE SELECT POWER CONTROL
Figure 11.2 Typical circuit for Single Ended Analog I/O's
15
100 uF
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Publication Release Date: September 2005 Revision B13
W681310
VDD
1.5K 22 uF 62k + 1.0 uF 1.0 uF ELECTRET MICROPHONE 3.9K 3.9K 62K 27K 27K 100pF 100pF
1K
0.1 uF
U4 17 18 19 20 1 2 3 4 5 AO AIAI+ VAG VREF ROPAI PAO-
VDD
6
FST BCLKT PCMT MCLK PCMR BCLKR FSR
14 12 13 11 8 9 7
8 KHz Frame Sy nc 2.048 MHz Bit Clock PCM OUT PCM IN
0.01 uF 0.1 uF 27K
1.5K
VSS
PAO+ W681310
u/A PUI
16 10
MODE SELECT POWER CONTROL
SPEAKER
Figure 11.3 Handset Interface
VDD 0.1 uF
15
27K 1.0 uF
17 18 19 20 1 2 3 4 5
AO AIAI+ VAG VREF ROPAI PAO-
VDD
27K
U5
6
FST BCLKT PCMT MCLK PCMR BCLKR FSR
14 12 13 11 8 9 7
8 KHz Frame Sy nc 4.096 MHz Bit Clock PCM OUT PCM IN B1/B2 SELECT
600 TRANSFORMER 600 OHM 1:1 0.01 uF 0.1 uF
27K
27K
VSS
PAO+ W681310
u/A PUI
16 10
MODE SELECT POWER CONTROL
Figure 11.4 Transformer Interface Circuit in GCI mode
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15
W681310
12. PACKAGE SPECIFICATION
12.1. 20L SOG (SOP)-300MIL
SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS
2
1
c
EH E
L
1
D
1
02
O
A Y SEATING b e A GAUGE
SYMBOL A A1 b c E D e HE Y L 0
DIMENSION (MM) MIN. 2.35 0.10 0.33 0.23 7.40 12.60 10.00 0.40 0 MAX. 2.65 0.30 0.51 0.32 7.60 13.00 10.65 0.10 1.27 8
DIMENSION (INCH) MIN. 0.093 0.004 0.013 0.009 0.291 0.496 0.394 0.016 0 MAX. 0.104 0.012 0.020 0.013 0.299 0.512 0.419 0.004 0.050 8
1.27 BSC
0.050 BSC
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Publication Release Date: September 2005 Revision B13
W681310
12.2. 20L SSOP-209 MIL
SHRINK SMALL OUTLINE PACKAGE
2
DIMENSIONS
D 1
DTEAIL
HE E
1
1
AA
SEATING
b
SEATING
Y
e
b
A
L DETAIL
L
DIMENSION (MM) SYMBOL A A1 A2 b c D E HE e L L1 Y 0 MIN. 0.05 1.65 0.22 0.09 6.90 5.00 7.40 0.55 0 NOM. 1.75 7.20 5.30 7.80 0.65 0.75 1.25 MAX. 2.00 1.85 0.38 0.25 7.50 5.60 8.20 0.95 0.10 8 MIN. 0.002 0.065 0.009 0.004 0.272 0.197 0.291 0.021 0
DIMENSION (INCH) NOM. 0.069 0.283 0.209 0.307 0.0256 0.030 0.050 MAX. 0.079 0.015 0.010 0.295 0.220 0.323 0.037 0.004 8
- 32 -
W681310
12.3. 20L TSSOP - 4.4X6.5MM
PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS
SYMBOL A A1 A2 E HE D L L1 b e c 0 Y
MIN. 0.05 0.80 4.30 6.40 0.50 0.19 0.09 0
DIMENSION (MM) NOM. MAX. 1.20 0.90 4.40 6.40 BSC 6.50 0.60 1.00 REF 0.65 BSC 0.10 BASIC 0.20 8 0.30 6.60 0.75 0.15 1.05 4.50
MIN. 0.002 0.031 0.169 0.252 0.020 0.007 0.004 0
DIMENSION (INCH) NOM. MAX. 0.047 0.035 0.173 .252 BSC 0.256 0.024 0.039 REF 0.026 BSC 0.004 BASIC 0.008 8 0.012 0.260 0.030 0.006 0.041 0.177
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Publication Release Date: September 2005 Revision B13
W681310
13. ORDERING INFORMATION
Winbond Part Number Description
W681310_ _
Product Family W681310 Product
Package Material: Blank G = = Standard Package Pb-free Package
Package Type: S R W = = = 20-Lead Plastic Small Outline Package (SOG/SOP) 20-Lead Plastic Small Outline Package (SSOP) 20-Lead Plastic Thin Small Outline Package (TSSOP)
When ordering W681310 series devices, please refer to the following part numbers.
Part Number
W681310S W681310R W681310W W681310SG W681310RG W681310WG
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W681310
14. VERSION HISTORY
VERSION A1 A2 B11 DATE August 10, 2003 August 22, 2003 November, 2004 2 6 33 34 22 23 PAGE Draft version Update typo errors and parameters Added reference packaging. to TSSOP package and Pb-free DESCRIPTION
Added reference to TSSOP package. Added description of TSSOP package. Added W and G package ordering code. Extended conditions on Table 10.2. Extended conditions on Table 10.3. Corrected Idle Channel Noise min/max and units. Improved Application Diagram Improved Application Diagram
B12 B13
April, 2005 September, 2005
36 29,30 22 Various
Add Important Notice Improved Application Diagram Added Reference to VRMS Capitalized logic HIGH/LOW
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Publication Release Date: September 2005 Revision B13
W681310
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. The information contained in this datasheet may be subject to change without notice. It is the responsibility of the customer to check the Winbond USA website (www.winbond-usa.com) periodically for the latest version of this document, and any Errata Sheets that may be generated between datasheet revisions.
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 http://www.winbond-usa.com/
Winbond Electronics (Shanghai) Ltd.
27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998
Taipei Office
9F, No. 480, Pueiguang Rd. Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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