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W93910 ERMES PAGING DECODER
GENERAL DESCRIPTION
The W93910 is a low-power ERMES (Enhanced Radio MEssage System) paging protocol decoder using a single 100 kHz crystal. The W93910 supports individual call, group call, long message, changing character set and remote programming functions. To enhance the sensitivity of the pager system, a digital filter and DPLL are incorporated to remove noise and lock the signal. For convenient pager programming, the W93910 provides fully software-programmable options and also offers an independent LED frequency output. With built-in flexible RF power saving control, frequency synthesizer enable control, quick charge controls, as well as automatic channel scan algorithm, the W93910 can combine with different RF receivers to construct a high performance, low power dissipation pager system.
FEATURES
* 100 kHz crystal * Built-in digital filter and digital phase lock loop * Built-in two addresses concurrently * One remote programming address * International roaming capability * Automatic channel scan algorithm * Built in de-interleaving circuit * 2-bit random error correction * Individual call, long message, changing character set and remote programming * CTAP group call * Serial interface with C * 2-bit signal input from RF receiver * RF and frequency synthesizer power saving control available * Quick charge-discharge timing control * Provides LED output * 2.5 to 3.5 volts operating voltage range * Packaged in 28-pin SSOP
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Publication Release Date: Auguest 1999 Revision A1
W93910
PIN CONFIGURATION
OSCI OSCO GND TCTL2 D0 D1 QC2 TCTL1 QC1 RFEN PLEN TXCLK TXDATA ON
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD LEDO TEST2 TEST1 ENLED MCLK MDATA MSGVAL ADRDET SYNVAL XCNCG CHRS PTEST XRST
PIN DESCRIPTION
SYMBOL OSCI OSCO GND TCTL2 D0 D1 QC2 TCTL1 QC1 RFEN PLEN PIN 1 2 3 4 5 6 7 8 9 10 11 I/O I O I O I I O O O O O 100 kHz crystal input. 100 kHz crystal output. Ground power. RF control pin. Inversion output of QC2. Demodulated data input bit0(LSB). Demodulated data input bit1(MSB). Receiver quick charge 2 signal enable. Active high/low is dependent on QC2L option bit. RF control pin. Receiver quick charge 1 signal enable. Active high/low is dependent on QC1L option bit. Receiver power control. Active high/low is dependent on RFENL option bit. PLL frequency synthesizer power control. Active high/low depends on PLENL option bit. C must program the freq. synthesizer counter while PLEN inactive. W93910 internal channel will be decided during PLEN active edge. PIN DESCRIPTION
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W93910
Pin Description, continued
SYMBOL TXCLK TXDATA
PIN 12 13
I/O I I/O
PIN DESCRIPTION 192 option bits clock input from C. TXDATA will be latched by W93910 during TXCLK rising edge. 192 option bits serial data input from C. Option bit address will be increased by one after each TXCLK period. After 192 option setting, the TXDATA pin will change to output pin for received OPID information access. Active high to enable W93910 chip operating. Oscillator starts oscillation after ON rising edge. OSCO will always stop while ON is low. Internal pull low, Active high to reset decoder. Internal pull low, Test mode only. Force roaming control pin. Connect to GND for normal operation. Pull high is only for test purpose. During PLEN pin high level, XCNCG (eXternal ChaNnel ChanGe) rising edge will inform C to change channel according to channel scanning rule. Synchronization Indicator (out-of-range indicator output). Output low when synchronized with paging system. Active high while the user IA detected in the address partition. (normally Low) MSGVAL will be active during MCLK, MDATA available period. Active high/low is dependent on MSGI option bit. Serial paging message output to C. Rising/falling edge is dependent on MCKEG option bit. UDI1-0 used to select interval per bytes MDATA. Serial clock output to C for available paging message. MCKI used to select initial state, and MCK1, MCK0 used to select clock rate. Internal pull low, Active high to enable LEDO output. Test only. No connection for normal operation Test only. No connection for normal operation 10/4 kHz or 40/16 kHz CMOS clock output. 3 volts power supply.
ON
14
I
XRST PTEST CHRS XCNCG
15 16 17 18
I I I O
SYNVAL ADRDET MSGVAL MDATA
19 20 21 22
O O O O
MCLK ENLED TEST1 TEST2 LEDO VDD
23 24 25 26 27 28
O I I O O I
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Publication Release Date: Auguest 1999 Revision A1
W93910
BLOCK DIAGRAM
VDD
XRST
GND
PTEST
D0 D1
DATA INPUT FILTER & PLL MAIN CONTROL CIRCUIT & ERROR CORRECTION
TXCLK 128 OPTIONS BITS TXDATA
OSCI OSCO
OSCILLATOR
AIR PROGRAMMING REGISTER
TIME OUT CONTROL
DATA OUTPUT BUFFER & CONTROL
MSGVAL MDATA MCLK ADRDET
RFEN PLEN QC1 QC2
RECEIVEING ENABLE CONTROL
CHANNEL STATUS CONTROL
LEDO LED & ALERT TYPE CONTROL ENLED
TCTL1
TCTL2
ON
SYNVAL CHRS XCNCG
TEST2 TEST1
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W93910
ADDRESS & OPTION LIST
BIT NO. DATA BIT NO. DATA BIT NO. DATA BIT NO. DATA BIT NO. DATA BIT NO. DATA b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31 0 IA17 IA16 IA15 IA14 IA13 IA12 IA11 IA10 IA9 IA8 IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0 BN3 BN2 BN1 BN0 PA5 PA4 PA3 PA2 PA1 PA0 0 0 0 b32 b33 b34 b35 b36 b37 b38 b39 b40 b41 b42 b43 b44 b45 b46 b47 b48 b49 b50 b51 b52 b53 b54 b55 b56 b57 b58 b59 b60 b61 b62 b63 FILT1 GIA17 GIA16 GIA15 GIA14 GIA13 GIA12 GIA11 GIA10 GIA9 GIA8 GIA7 GIA6 GIA5 GIA4 GIA3 GIA2 GIA1 GIA0 CH3 CH2 CH1 CH0 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 LPWR
QCON1
b64 b65 b66 b67 b68 b69 b70 b71 b72 b73 b74 b75 b76 b77 b78 b79 b80 b81 b82 b83 b84 b85 b86 b87 b88 b89 b90 b91 b92 b93 b94 b95
1 ZC2 ZC1 ZC0 CC6 CC5 CC4 CC3 CC2 CC1 CC0 OP2 OP1 OP0 FSN3 FSN2 FSN1 FSN0 0 1 0 1 1 0 0 0 0 0 0 0 0 0
b96 b97 b98 b99 b100 b101 b102 b103 b104 b105 b106 b107 b108 b109 b110 b111 b112 b113 b114 b115 b116 b117 b118 b119 b120 b121 b122 b123 b124 b125 b126 b127
Table 1
SIEN
QCON0
b128 b129 b130 b131 b132 b133 b134 b135 b136 b137 b138 b139 b140 b141 b142 b143 b144 b145 b146 b147 b148 b149 b150 b151 b152 b153 b154 b155 b156 b157 b158 b159
1 RPIA17 RPIA16 RPIA15 RPIA14 RPIA13 RPIA12 RPIA11 RPIA10 RPIA9 RPIA8 RPIA7 RPIA6 RPIA5 RPIA5 RPIA3 RPIA2 RPIA1 RPIA0 RPI RSVD RSVD RSVD RPPA5 RPPA4 RPPA3 RPPA2 RPPA1 RPPA0 RSVD RSVD 0
b160 b161 b162 b163 b164 b165 b166 b167 b168 b169 b170 b171 b172 b173 b174 b175 b176 b177 b178 b179 b180 b181 b182 b183 b184 b185 b186 b187 b188 b189 b190 b191
1 RPZC2 RPZC1 RPZC0 RPCC6 RPCC5 RPCC4 RPCC3 RPCC2 RPCC1 RPCC0 RPOP2 RPOP1 RPOP0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0
RFON PL1 PL0 GIAEN PAEN GPAEN MCKI MDAI MCKEG RFENL PLENL QC1L QC2L D0IV D1IV MCK1 MCK0 LKR1 LKR0 0 LEDF MSGI UDI1 UDI0
QC1WTH
0 0 0 0 0
0
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Publication Release Date: Auguest 1999 Revision A1
W93910
192 OPTION BITS
Detailed description given in Function Description section. RIC format IA17-IA0: Basic RIC initial address BN3-BN0: Basic RIC batch number A(0000)-P(1111) PA5-PA0: Basic RIC paging area code (000000-111111) PAEN: Enable PA5-PA0 while PAEN active GIA17-GIA0: Second RIC initial address CH3-CH0: Home channel initial value from Channel 0 (0000)-Channel F (1111) GPA5-GPA0: Second RIC paging area code (000000-111111) GPAEN: Enable GPA5-GPA0 while GPAEN active GIAEN: Enable GIA17-GIA0 initial address ZC2-ZC0: Receiver zone code CC6-CC0: Receiver country code OP2-OP0: Receiver operator code FSN3-FSN0: Frequency subset number (0000-1111) RPIA17-RPIA0: Remote programming initial address RPPA5-RPPA0: Remote programming paging area code (000000-111111) RPZC2-RPZC0: Remote programming zone code RPCC6-RPCC0: Remote programming country code RPOP2-RPOP0: Remote programming operation code RPI: Remote programming index RF Interface: RFENL: RFEN pin active level option bit PLENL: PLEN pin active level option bit QC1L: QC1 active level option bit QC2L: QC2 active level option bit D0IV: D0 input polarity option bit D1IV: D1 input polarity option bit PL1-0, RFON, QCON1-0, QC1WTH: RFEN, PLEN, QC1 and QC2 active timing control bits. uC Interface: MSGI, MCKI, MDA I: MSGVAL, MCLK, MDATA pin initial state option bit MCKEG: MCLK active edge; MCK1-MCK0: MCLK output clock option bits UDI1-0: MCLK stop clock option LEDF: LED freq. output selection(1:10/40 kHz; 0:4/16 kHz) Others: LKR1-LKR0: SYNC lost hold time option SIEN: System information output enable option LPWR: Power saving option FILT1: Digital filter option
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W93910
FUNCTION DESCRIPTION
The W93910 ERMES paging decoder can be used to easily construct an ERMES pager with RF receiver and C. To initialize the decoder, first, 192 option bits must be programmed through TXCLK, TXDATA pin by C. After the oscillator has been turned on and is stable, the decoder can then receive and decode the 2 bit digital QFSK signal from the RF receiver. With built-in PLEN, RFEN, QC1 and QC2 controls, the decoder can warm up and shut down the frequency synthesizer and IF demodulator for optimum reception in different stages. While starting, the pager will begin to search the home channel. If system synchronization can't occur in the current channel, the pager will change to the next channel according to the channel scan algorithm until synchronization occurs. Once synchronized with the channel, the pager will lock to its own batch, ready to receive paging message. If an address-matched message is received, the de-interleaved data will be transferred to C through MDATA and MCLK pin. With the automatic channel scan algorithm, the decoder will inform C by PLEN and XCNCG to change channel during channel scan and normal mode.
RECEIVING OPERATION FLOW
Power on and XREST
192 options setting
ON
Oscillator stable
CHANNEL SCANNING MODE
IDLE MODE
SYNC MODE
LOCK MODE
NORMAL MODE
Figure 1. Operating Flow Chart
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Publication Release Date: Auguest 1999 Revision A1
W93910
192 OPTION BITS PROGRAMMING
After power on and XRST pin active, the C should send 192 clock inputs to TXCLK pin and 192 options to TXDATA pin. Figure 2 shows the TXCLK and TXDATA programming timing. The data values in TXDATA are latched at TXCLK rising edge. The clock rate of TXCLK should be smaller than 1 MHz.
Txrst XRST Ttdst TXCLK Ttdhd Ttxck TXDATA
b0 b1
......
......
b189 b190 b191
PLEN
Low
Ton
ON OSCO Tosc
Figure 2. 192 option bits programming timing
RECEIVING ENABLE CONTROL
After the W93910 has received the 192 options, it will start the operation if the ON pin is high, or in stand-by mode if ON pin is low. The On pin can be pulled high at any time to activate the oscillator. After oscillator is stable, the decoder will activate the PLEN. RFEN, QC1, QC2, TCTL1, and TCTL2 to control the frequency synthesizer and IF demodulator, based on the option setting as shown in Figure 3. The frequency synthesizer need to be programmed to the right channel (normally home channel) before PLEN active. The PLEN is used to control the frequency synthesizer power, and inform C of the receiving status. The output levels of RFEN, PLEN, QC1 and QC2 are defined by the option bits RFENL, PLENL, QC1L and QC2L as shown in Table 2. TCTL2 is the inversion output of QC2. The TCTL1 active level is fixed. The TCTL1 and TCTL2 output will be activated only when the LEDF option bit is set to 1. Option bit PL1-0, RFON, QCON1-0 and QC1WTH provides different set up time for PLEN, RFEN, QC1, QC2, TCTL1 and TCTL2, as shown in Table 3, to meet different RF receiver requirements.
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W93910
PLEN RFEN
Tqc1w
QC1 TCTL1 QC2 TCTL2
Tplst
Batch n
Trfdy ON
Batch n+1
High
(While RFENL, PLENL, QC1L and QC2L are "0")
Figure 3. PLEN, RFEN, QC1, QC2, TCTL1 and TCTL2 timing
OPTION BIT RFENL, PLEN, QC1L, QC2L 0 1
Table 2. RF interface active option bits
FUNCTION RFEN, PLEN, QC1, and QC2 pin voltage level Active high Active low
OPTION BIT PL1 0 0 1 1 PL0 0 1 0 1
Table 3. PLL enable timing
FUNCTION Tplst setting 9.6 mS 19.2 mS 28.8 mS Reserved
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Publication Release Date: Auguest 1999 Revision A1
W93910
OPTION BIT RFON 0 1
FUNCTION Trfdy 4.8 mS 9.6 mS
Table 4. RF interface timing control option bit
OPTION BIT QC1WTH 0 1
Table 5. Quick-charge duration option bit
FUNCTION Tqc1w 3.8 mS 2.5 mS
OPTION BIT QCON1 1 0 0 QCON0 0 0 1 QC1 duration
FUNCTION QC2 duration Tplst + Trfdy + 9.6ms Trfdy + 9.6ms 9.6 ms Tplst + Trfdy + Tqc1w Trfdy + Tqc1w Tqc1w
Table 6. Quick-charge active timing control option bits
CHANNEL SCAN MODE
In this mode, decoder will enable the receiver to search the available channel in different frequency channels based on the channel scan control algorithm.
...
RFEN
XCNCG CHANNEL NO Home channel Change channel Home channel + 2
...
Change channel
Figure 4. Channel Scan Mode
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W93910
CHANNEL SCAN CONTROL
The channel scanning and switching are controlled by the decoder. Table 7 shows the channel number and frequency. In channel scan mode, the decoder will first search the home channel, defined by the CH3-CH0. Therefore, the synthesizer should be programmed to home channel before the channel scan mode. If the pager can not detect a valid signal in the home channel, the pager will change to the next channel to search until the decoder lock to the signal. The scanning sequence is shown in Figure 5, and needs to be followed to avoid losing signal. OPTION BIT CH3-CH0 0000 0010 0100 0110 1000 1010 1100 1110 1111 1101 1011 1001 0111 0101 0011 0001 FUNCTION Home channel number RF center frequency 0 2 4 6 8 A C E F D B 9 7 5 3 1
Table 7. Channel number and frequency
169.425 MHz 169.475 MHz 169.525 MHz 169.575 MHz 169.625 MHz 169.675 MHz 169.725 MHz 169.775 MHz 169.800 MHz 169.750 MHz 169.700 MHz 169.650 MHz 169.600 MHz 169.550 MHz 169.500 MHz 169.450 MHz
Ch 0
Ch 2
Ch A
Ch C
Ch 3
Ch 1
Figure 5. Channel scan sequence
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Publication Release Date: Auguest 1999 Revision A1
W93910
The frequency channel adjustment is implemented by XCNCG, PLEN, and C. XCNCG is used to output a high pulse to inform C of the frequency channel increment request. C needs to count the XCNCG high pulse during the PLEN active period. Each XCNCG pulse indicates one frequency channel increment. During the PLEN inactive period, the C should program the synthesizer with suitable data based on the previous XCNCG counting result to ensure the receiver can catch the right channel. During the lock mode, the pager will fix at the same channel as shown in Figure 6 and 7. The normal mode operation is described in Figure 8 and 9. The batch number setting is shown in Table 8. OPTION BIT bn3-bn0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Table 8. bn3-bn0 batch number format
FUNCTION Batch Number A B C D E F G H I J K L M N O P
IDLE MODE
If there is no meaningful signal after scanning the channel several times, the decoder will enter idle mode to save power, and will re-enter the channel scan mode after a period of time.
SYNC MODE
While synchronizing with the paging system, the decoder enters sync mode and the SYNVAL pin outputs LOW The decoder will then change to lock mode or normal mode based on the receiving information.
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W93910
LOCK MODE
In lock mode, the decoder will stay at the same channel. If matching addresses appear, all the available paging messages will be received until messages are finished or time out occurs.
PLEN receiving message
Figure 6. Lock Mode
no message
Status ON
Lock mode
Channel scanning mode
Lock mode
Top PLEN XCNCG
due to XCNCG rising uC internal channel 9 7 5 3 9 7 9
Txcncg:XCNCG pulse
7
Tpll:uC change frequency synthesizer counter PLL freq. synthesizer channel Decoder channel 9 7 5 9 9 7
due to PLEN active edge 9 7 7 7 5 9 9 7
The above example shows the home channel of the pager is channel 9 (CH3-CH0 = 1001) and pager locks to channel 7.
Figure 7. Channel Scan mode and lock mode
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Publication Release Date: Auguest 1999 Revision A1
W93910
NORMAL MODE (NON-LOCK) Decoder will enter normal mode while not in the home network or the border area indication condition. In this mode, the decoder will switch and listen to different frequency channel based on the channel scan control algorithm. The PLEN operating timing is shown in Figure 8.
PLEN
Status
Batch A of channel 2 Batch A of channel 4 Batch A of channel 6 Batch A of channel 1 Batch A of channel 0
The batch number is set to batch A
Figure 8. Normal Mode
ON PLEN
High
XCNCG uc internal channel PLL freq. synthesizer channel Decoder channel
Notes:
2
4
6
8
A
C
E
F
D
B
9
2
4
6
A
C
E
B
2
4
6
A
C
E
B
1. uC need to count the number of XCNCG pulse during the PLEN active period, and program the synthesizer with suitable data during the PLEN inactive period. 2. PLEN will be the dash line if there is no paging message.
Figure 9. Channel scan in NORMAL MODE
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W93910
LOST SYNCHCONIZATION
If synchronization is lost for several minutes (pre-defined by option bit LKR1-LKR0 ), the pager will change to the channel scan mode. The SYNVAL pin will keep low during the lock mode and normal mode unless the synchronization lost duration exceeds the hold time condition, then the SYNVAL pin will change to high level and the decoder will go back to the channel scan mode. OPTION BIT LKR1 0 0 1 1 LKR0 0 1 0 1
Table 9. Lock re-try option bits
FUNCTION Synchronization lost hold time 1 min. 2 min. 3 min. 4 min.
RIC (Radio Identify Code) FORMAT
For ERMES system, RIC has 35 bits and is defined by ZC2-ZC0, CC6-CC0, OP2-OP0, IA17-IA0, and BN3-BN0 option bits as shown in Table 10. Radio Identify Code Function OPID LOCAL ADDRESS Paging area PA5-PA0 GPA5-GPA0
Zone Code Country Code Operator Code Initial Address Batch Number OPTION bit ZC2-ZC0 CC6-CC0 OP2-OP0 IA17-IA0 GIA17-GIA0
Table 10. RIC format
BN3-BN0
The W93910 provides two initial addresses with corresponding paging area code, IA17-IA0 with PA5-PA0 and GIA17-GIA0 with GPA5-GPA0, for the same OPID. The first one is dedicated for the basic RIC. Each pager has one unique batch number, defined by BN3-BN0, and will only turn on and listen at that specific batch except where a message continues over one batch. If PAEN option bit is set to "1", the received message must match to the pre--defined paging area code, PA5-PA0. Other than in this situation, the received paging area code doesn't need to match the pre-defined PA5-PA0, but must be consistent throughout the whole message. The second IA, GIA17-GIA0, is enabled by setting the GIAEN option bit to 1. GPAEN has the same function as PAEN, but for GIA17-GIA0 address only. OPTION BIT GIAEN 0 1
Table 11-1. Second initial address setting option bits
FUNCTION Second user address (GPA+GIA) Disable Enable
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Publication Release Date: Auguest 1999 Revision A1
W93910
OPTION PAEN, GPAEN 0 1
Table 11-2. Paging area setting
FUNCTION PA5-PA0, GPA5-GPA0 Don't care Enable
REMOTE PROGRAMMING
The W93910 provides remote programming addresses including initial address, paging area, zone code, and country code to support the remote programming function. These option bits are listed in Table 12. These temporary addresses can be programmed during the initial setting or modified by the air message. While receiving the remote programming address message, W93910 will automatic update the internal remote programming addresses and also pass the programming message to C through MDATA pin. The data should be stored for re-initialization purpose. Please refer to Summary of Data Output Format. If the remote programming data is less than 18 bits, the dummy "0" is filled in the other low bits of rd17-rd0. For the first time initialization, all the option bits should be "0" including the RPI. The RPI is the remote programming index, which can be read out from MDW while receiving the remote programming message.
OPTION BIT RPIA17-RPIA0 RPPA5-RPPA0 RPZC2-RPZC0 RPCC6-RPCC0 RPOP2-RPOP0 RPI
FUNCTION Initial Address Paging Area Zone Code Country Code Operator Code Remote Programming Index
Table 12. Remote programming register
SYSTEM INFORMATION
By setting the SIEN option bit to 1, the system information can also be read out from TXDATA pin. After 192 option bits setting, if the C decides to read out the received system information, the C needs to send 31 clocks to TXCLK pin. The first clock pulse will switch TXDATA pin from input to output, and the last clock pulse will disable this function. At the falling edge of the each clock pulse except the first and last clock one, the system information (batch no, country code, operator code, cycle no., hour) can be read out from the TXDATA pin. The best timing to read out the system information is right after PLEN falling edge. The format and timing are shown in Figure 10. This function is disabled if SIEN is set to 0.
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W93910
TXCLK TXDATA Start Batch3-0 CC6-0 Op2-0 Cycle No5-0 Hour4-0 Reserved Stop
Figure 10. System information read out format
DATA INPUT
The 4 level FSK signal is converted to 2 bit digital signal by IF demodulator, as shown in Figure 11, where fn is the carrier frequency from 169.425 MHz to 169.8 MHz. The 2 bit digital signal should be connected to the D1(MSB), D0(LSB) inputs of W93910. The D1 and D0 inputs could be inverted by setting the D1IV, and D0IV option bits to provide some flexibility. OPTION BIT D1IV, D0IV 0 1
Table 13. D1, D0 relative option bits
FUNCTION D1 input, D0 input Non-inversion Inversion
10 (fn-4687.5Hz) 11 (fn-1562.5Hz) 01 (fn+1562.5Hz) 00 (fn+4687.5Hz) D1 D0 : : 0 1 0 0 1 0 1 1 0 1 1 0
Figure 11. 4 PAM mapping to D1, D0(fn is the channel carrier frequency)
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Publication Release Date: Auguest 1999 Revision A1
W93910
DIGITAL FILTER & POWER SAVING
The W93910 provides different digital filter to remove the noise of the 4FSK signal. The enhanced filtering require higher power consumption. Table 14 shows different combinations of digital filtering and power saving. OPTION BIT FILT1 0 1 LPWR 0 1 FUNCTION Digital filter & power saving Low power consumption, normal filtering Enhanced filtering, high power consumption
Table 14. Digital filter and power saving option
DE-INTERLEAVER AND ERROR CORRECTION
The W93910 performs 2 bits random error correction for system information, address partition as well as message partition, and codeword de-interleaving for message partition.
TIME OUT CONTROL
When the decoder recognizes a valid initial address it will start to search the associated paging message. Time out criteria will stop message searching at once. While the searching is stopped due to time out issue, the "epa" and "etm" in EDW format will be set to indicated the time out situation. At the mean time, the RF control signal will become inactive at once when ending message delimiter (MD) has been detected.
* For Individual calls
Two time out criteria shall apply. The earliest detected shall prevail: 1. If PA5-PA0 in paging message is not consistent throughout the receiving, then the epa flag will be set to "1". 2. If the paging message lasts more than 12 sec, then etm flag will be set to "1".
* For group calls
Individual member shall cease message search if: 1. If PA5-PA0 in paging message is not consistent throughout the receiving, then the epa flag will be set to "1". 2. If the paging message lasts more than 12 sec, then etm flag will be set to "1".
* For long message calls
The time out criteria for each sub-message is the same as for individual call. The time out of the whole long message should be proceeded by the software to meet the ERMES protocol.
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W93910
DATA OUTPUT CONTROL
When the chip detects the proper address, the chip will first activate ADRVAL pin to inform the C and then send the de-interleaved paging message and related system information to the C through MCLK and MDATA pin. The format and timing of the data output is shown in Figure 12. The data output is packed into a 3-byte word format. The function of each word is defined by the Function Code, the first 4 bits of byte3, as shown in Table 15. The format of the rest 20 bits will depend on the function code.
HIGH NIBBLE OF BYTE 3 0000 0010 010x 0110 1110 Others
Table 15. Data Output Function Code
FUNCTION CODE System Information Word (SIW) ComMand Word (CMW) Addition Information Word (AIW) Message data Word (MDW) EnD message Word (EDW) RESERVED
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Publication Release Date: Auguest 1999 Revision A1
W93910
ADRDET Taddt MSGVAL Tint MDATA MCLK Tmsgv Message 1 Message 2
SIW
CMW
AIW
MDW0
EDW
SIW
EDW
Tudi D23-17 MDATA byte3 MCLK (MCKEG=1) byte2 D15-D8
Tudi D7-D0 D23-17
byte 1
Tint
Tunit
MCKI=0 MDATA D23 Tmdst MCLK (MCKEG=1) Tmclk MCLK (MCKEG=0) MCKI=1 MDATA D23 Tmclk MCLK (MCKEG=1) .... .... D22 .... .... .... .... D22 .... D17 D16 D15 .... D8
.... D17 D16 D15
.... D8
Tmclk MCLK (MCKEG=0) .... ....
Figure 12. Data Output Timing
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W93910
Table 16-Table 19 list the active level and timing option bit settings of the data output format. MCLK clock rate is defined by option bit MCK1-0. The duration between each word, Tint, and the duration between each byte, Tudi, are defined by option bit UDI1-UDI0. Option bit MCKEG defines MCLK active edge. MCKI, MSGI and MDAI option bits set MCLK, MSGVAL and MDATA pin initial and active state. The output sequence of MDATA pin is SIW, CMW, MDW0, MDW1...MDWn, EDW for all the message types except long message. For long message, an extra AIW is added between CMW and MDW0. Please refer to Summary of Data Output Format for different paging message format. OPTION BIT MCKEG 0 1
Table 16. Data output pin option
FUNCTION MCLK active edge Falling edge active Rising edge active
OPTION BIT MSGI 0 1
Table 17. Data output pin option
FUNCTION MSGVAL active level active low active high
OPTION BIT MDAI, MCKI 0 1
Table 18. Data output pin option
FUNCTION MDATA, MCKI pin initial state Initial low Initial high
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Publication Release Date: Auguest 1999 Revision A1
W93910
OPTION MCK1, MCK0 00 Tmclk = 80 S UD1, UD0 00 01 10 11 00 01 Tmclk = 40 S 01 10 11 00 10 Tmclk = 20 S 01 10 11 00 11 Tmclk = 5 S 01 10 11 Tudi timing 0 160 S 320 S 640 S 0 160 S 640 S 1 mS 0 160 S 640 S 1.16 mS 0 80 S 640 S 1.275 mS
FUNCTION Tint timing 2.08 mS 1.76 mS 1.44 mS 800 S 3.04 mS 2.72 mS 1.76 mS 1.04 mS 3.52 mS 3.2 mS 2.24 mS 1.2 mS 3.88 mS 3.72 mS 2.66 mS 1.33 mS
Table 19. Tudi and Tint timing option (where Tunit = 4 mS minimum)
SIW Definition
When the W93910 receives a message, the MSGVAL pin will be activated first, and then SIW will be the first word to output from the MDATA pin. System information, such as year, month, date, hour, day and OPID, may resolve from SIW.
SIW byte3 byte2 byte1
b7 0 s13 s5
b6 0 s12 s4
b5 0 s11 s3
b4 0 s10 s2
Table 20. SIW format
b3 fsi s9 s1
b2 sn2 s8 s0
b1 sn1 s7 X
b0 sn0 s6 X
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W93910
SIW Description:
fsi 0 1 s13 z2 w2 s12 z1 w1 s11 z0 w0 s10 h4 mt3 s9 h3 mt2 s8 h2 mt1 s7 h1 mt0 s6 h0 yr6 s5 d4 yr5 s4 d3 yr4 s3 d2 yr3 s2 d1 yr2 s1 d0 yr1 s0 rv yr0
Table 21. s13-s0 format
sn2-sn0 is the subsequence number 0(000) to 4(100) that existed in SI field. fsi is the function bit of s13-s0 that provides all transmitter time base information. 1. fsi = 0 while SSIT is equal "0000" in SSI field z2-z0: RIC zone code from 000-111 h4-h0: Local hour from 0(00000)-23(10111) d4-d0: Local date from 1(00001)-31(11111) rv: reserve bit for future (Note: minute will be shown as cy5-cy0 in EDW) 2. fsi = 1 while SSIT is equal "0001" in SSI field w2-w0: Local day of week from Monday(001)-Sunday(111) mt4-mt0: Month from January(0001)-December(1100) yr6-yr0: Year from 1990(0000000) -2117(1111111)
CMW Definition
The second word is CMW, which indicates the message type, message number, paging category, and alert type of received paging message. CMW byte3 byte2 byte1 b7 0 eb 0 b6 0 g1 0 b5 1 g0 pc1 / f1 b4 0 mn4 pc0 / f0 b3 cm3 mn3 ain3 b2 cm2 mn2 ain2 b1 cm1 mn1 ain1 b0 cm0 mn0 ain0
Table 22. CMW format
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Publication Release Date: Auguest 1999 Revision A1
W93910
CMW Description:
cm3-cm0 0000 1000 1001 1010 1100 1101 1110 1111 Others individual call long message w/o C.S--First submessage. long message w/o C.S--Others submessage. remote programming retransmit latest message no# long message with C.S--Others submessage. long message with C.S--First submessage. Change Character Set (C.S.) Reserved
Table 23. Message type description (cm3-cm0)
message type description
eb 0 1
External flag Home Receiver External receiver
Table 24. External receiver index
g1 g0 00 01 10 11
RIC address index of received message IA17-IA0 available Air Programming RIC GIA17-GIA0 available Group call by CTAP method
Table 25. Received message address index
mn4-mn0 00000
Message number For group calls the reserved dummy value 00000 shall be used. The reserved dummy value may also be used when the message numbering is deactivated, as with remote programming. For individual calls the initial value shall be 00001; then mn4-mn0 will be increased by 1 continuously for the following message.
Table 26. Message number description (mn4-mn0)
Others
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W93910
pc1 pc0 00 01 10 11
Table 27. Paging category index
Paging category Tone only Numeric Alphanumeric transparent data
The ain3-ain0 is used to indicated the alert type of the message, except in the remote programming situation. ain3-ain0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Table 28. Alert type index
Alert type description non-urgent alert type 0 non-urgent alert type 1 non-urgent alert type 2 non-urgent alert type 3 non-urgent alert type 4 non-urgent alert type 5 non-urgent alert type 6 non-urgent alert type 7 urgent alert type 0 urgent alert type 1 urgent alert type 2 urgent alert type 3 urgent alert type 4 urgent alert type 5 urgent alert type 6 urgent alert type 7
CMW for remote programming
When the pager receives the remote programming message, the W93910 will program the internal remote programming addresses automatically, and will also inform the C by sending out the received message. For remote programming, the cm3-cm0 of CMW is equal to 1010, the f1-f0 and ain3-ain0 of CMD, and rd17-rd0 of MDW will send out the received programming message to C as shown below.
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Publication Release Date: Auguest 1999 Revision A1
W93910
ain3- 0 of CMW 0001 0010 0100 1000 0111
rd17-rd0 definition in MDW RIA17-RIA0 RPA5-RPA0 + 12 dummy '"0" RZC3 + RCC7 + ROP3 + 5 dummy "0" SM5 + HNL3 + 12 dummy "0" SM5 + ENL3 + 12 dummy "0"
Programmable function Initial Address Paging Area OPID Home receiver battery saving External receiver battery saving
Table 29. Remote programming MDW format only
f1-f0 00 01 10 11
Function description Add RIA, RPA, ROPID or replace SM Remove RIA, RIA, ROPID Restore SM, ENL, HNL to Table 1 Reserve
Table 30. Remote programming MDW format only
AIW Definition
AIW byte3 byte2 byte1 b7 0 lc15 lc7 b6 1 lc14 lc6 b5 0 lc13 lc5 b4 cs4 lc12 lc4
Table 31. AIW format
b3 cs3 lc11 lc3
b2 cs2 lc10 lc2
b1 cs1 lc9 lc1
b0 cs0 lc8 lc0
The AIW is only available for long message (cm3-cm0 = 1000,1001,1101,1110) or changing character set (cm3-cm0 = 1111), otherwise it's absent. The cs4-0 indicate character set and lc15-lc0 indicate link counter. The different formats of AIW for the four different types of long message and changing character set are listed in Summary of Data Output Format. Each long message is divided into many submessages. The first submessage (cm3-cm0 = 1000 or 1110) must be transmitted first, then other submessages follow in sequence. Each submessage has its own link counter lc15-lc0, which indicates how many message bits remain to be transmitted. The ter flag is defined to indicate the end of the long message as shown in Table 28. When ter flag is 1, it means the long message is completed. Otherwise, it means there are still some other submessages in the coming signal. For a long message, the W93910 will store all the received submessages including the EOM and filler bits in MDW and then send to UC. The filler bits and EOM are the last message part of MDW group, MDW1, MDW2...MDWn, and need to be removed to construct the long message. The following equation shows how many message bits of the previous MDW group need to be truncated. The long message can then be reproduced by connecting all the submessages except the truncated parts.
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W93910
No. of message bits needing to be truncated in previous MDW group = Total message bits of previous MDW group - [ (lc15-lc0)previous - (lc15-lc0)current ] ter flag in EDW ter = 1 ter = 0 Status long message is completed long message is not completed
Table 32. ter flag of EDW for long message
MDW Definition
The received paging message will be output as MDW1, MDW2 ....MDWn format (MDW group). md17-md0 are the actual paging message data resolved from the message partition, including terminator character EOM and any dummy bit such as a filler. For any submessage of a long message, C needs to use AIW's lc15-lc0 to truncate terminator or dummy bit from md17-md0 according to AIW description. While remote programming, rd17-rd0 is used for remote programming data only. RPI is the remote programming index received from system. This bit should be loaded into b147 of option bit during the re-initialization stage if the remote address is programmed. MDW byte3 byte2 byte1 b7 0 md13/ rd13 md5/rd5 b6 1 md12/ rd12 md4/rd4 b5 1 md11/ rd11 md3/rd3 b4 0 md10/ rd10 md2/rd2 b3 md17/ rd17 md9/ rd9 md1/rd1 b2 md16/ rd16 md8/ rd8 md0/rd0 b1 md15/ rd15 md7/ rd7 er1 b0 md14/ rd14 md6/ rd6 RPI
Table 33. MDW format
MDW Description: BIT md17-md0 (normal message) rd17-rd0 (remote programming) er1 rsv Available paging message Remote programming data only set to 1 if the random error can't be corrected in this message word don't care, reserved for future
Table 34. MDW bit description
FUNCTION
Any paging message such as 7 bit alphanumeric, 4 numeric or transparent data will be placed continuously in the 18 bit information field, md17-md0. After the last character (or bit) of message the following message termination procedures shall be used: * Alphanumeric: an EOM character (0010001) shall be appended; * Numeric: no terminating character required; * Transparent data: a single bit set to one shall be appended;
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Publication Release Date: Auguest 1999 Revision A1
W93910
Unused bit in message shall be set as the following default values: * Alphanumeric: EOM character and partial EOM character (MSB used first) shall be repeated to fill the remaining bits; * Numeric: space character and partial space character ( MSB used first ) shall be repeated to fill the remaining bits; * Transparent data: binary zeros shall be used to fill the remaining bits; The bit mapping in MDW unit for numeric and 7 bit alphanumeric are as follows. For numeric format, bit17-14 of MDW0 construct the first numeric, bit13-10 are the second... bit1-0 of MDW0 and bit17-16 of MDW1 are the fifth numeric.... Therefore, two MDWs will construct 9 numeric. For 7 bit alphanumeric format, bit17-11 of MDW0 construct the first character, bit10-4 of MDW0 are the second character, bit 3-0 of MDW0 and bit17-15 of MDW1 are the third character... The alphanumeric definition is depended on Character Set (C.S.). The default C.S. is 00000. EDW Definition The EDW will follow the last MDW while the paging message is completed. Normally, the ter flag is "0" except in a long message completion situation. For any submessage of a long message except the last one, the ter flag of EDW is "0". Only when the long message is completed will the ter flag of EDW be "1". There is some other system information in byte2 of EDW such as eti flag, bai flag and current cycle number, cy5-cy0. The ch3-0 of byte3 indicate which frequency channel the current paging message is caught from and the bn3-bn0 of byte3 indicate which batch the message is completed in. EDW byte3 byte2 byte1 b7 1 eti bn3 b6 1 bai bn2 b5 1 cy5 bn1 b4 0 cy4 bn0
Table 35. EDW format
b3 0 cy3 ch3
b2 ter cy2 ch2
b1 epa cy1 ch1
b0 etm cy0 ch0
EDW description:
BIT ter epa etm cy5-cy0 eti bai FUNCTION set to "1" while current long message is completed, otherwise ter flag is "0" for any individual call or submessage. set to "1" if paging message searching is stopped due to PA inconsistency set to "1" if paging message searching is stopped due to 12 sec time out cycle number from 0(000000) -59(111011) as minute index. External Traffic indicator in SI field Border Area Indicator flag in SI field
Table 36. EDW description
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W93910
Summary of Data Output Format
message type (cm3-0) Individual 0000 3 2 1 0XXX(Reserved) Long w/o C.S. (First submessage) 1000 Long w/o C.S. (Other submessages) 1001 Remote Programming 1010 1011(reserved) Retransmit Latest msg no 1100 Long with C.S. (First submessage) 1101 Long with C.S. (Other submessages) 1110 Change Character Set 1111 3 2 1 3 2 1 3 2 1 3 2 1 0000 fsi sn2-sn0 s13-s6 s5-s0 0 0 0000 fsi sn2-sn0 s13-s6 s5-s0 0 0 0000 fsi sn2-sn0 s13-s6 s5-s0 0 0 0000 fsi sn2-sn0 s13-s6 s5-s0 0 0 0010 cm3-cm0 eb g1 g0 mn4~mn0 0 0 pc1-pc0 ain3-ain0 0010 cm3-cm0 eb g1 g0 mn4-mn0 0 0 pc1-pc0 ain3-ain0 0010 cm3-cm0 eb g1 g0 mn4-mn0 0 0 pc1-pc0 ain3-ain0 0010 cm3-cm0 eb g1 g0 mn4-mn0 0 0 pc1-pc0 ain3-ain0 X X X 010 cs5-cs0 lc15-lc8 lc7~lc0 010 cs5-cs0 lc15-lc8 lc7-lc0 010 cs5-cs0 xxxx xxxx xxxx xxxx 0110 md17-md14 md13-md6 md5-md0 er1 rsv 0110 md17-md14 md13-md6 md5~md0 er1 rsv 0110 md17-md14 md13-md6 md5-md0 er1 rsv 0110 md17-md14 md13-md6 md5-md0 er1 rsv 1110 0 ter epa etm eti bai cy5-cy0 bn3-bn0 ch3-ch0 1110 0 ter epa etm eti bai cy5-cy0 bn3-bn0 ch3-ch0 1110 0 ter epa etm eti bai cy5-cy0 bn3-bn0 ch3-ch0 1110 0 ter epa etm eti bai cy5-cy0 bn3-bn0 ch3-ch0 3 2 1 3 2 1 3 2 1 0000 fsi sn2-sn0 s13-s6 s5-s0 0 0 0000 fsi sn2-sn0 s13-s6 s5-s0 0 0 0000 fsi sn2-sn0 s13-s6 s5-s0 0 0 0010 cm3-cm0 eb g1 g0 mn4-mn0 0 0 pc1-pc0 ain3-ain0 0010 cm3-cm0 eb g1 g0 mn4-mn0 0 0 pc1-pc0 ain3-ain0 0010 cm3-cm0 eb g1 g0 mn4-mn0 0 0 f1-f0 ain3-ain0 010 xxxxx lc15-lc8 lc7-lc0 010 xxxxx lc15-lc8 lc7-lc0 X X X 0110 md17-md14 md13-md6 md5-md0 er1 rsv 0110 md17-md14 md13-md6 md5-md0 er1 rsv 0110 md17-md14 rd13-rd6 rd5-rd0 er1 rsv 1110 0 ter epa etm eti bai cy5-cy0 bn3-bn0 ch3-ch0 1110 0 ter epa etm eti bai cy5-cy0 bn3-bn0 ch3-ch0 1110 0 ter epa etm eti bai cy5-cy0 bn3-bn0 ch3-ch0 byte SIW (D23-D0) 0000 fsi sn2-sn0 s13-s6 s5-s0 0 0 CMW (D23-D0) 0010 cm3-cm0 eb g1 g0 mn4-mn0 0 0 pc1-pc0 ain3-ain0 X X X AIW (D23-D0) MDW (D23-D0) 0110 md17-md14 md13-md6 md5-md0 er1 rsv EDW (D23-D0) 1110 0 ter epa etm eti bai cy5-cy0 bn3-bn0 ch3-ch0
Table 37. MDATA output summary Note: where "x" means don't care
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Publication Release Date: Auguest 1999 Revision A1
W93910
LED CONTROL LEDO will output a frequency while ENLED is in high level. The LEDO output frequency is selected by option bit LEDF and PLEN condition as described in table 38. When the LEDF is set to 1, the TCTL1 and TCTL2 control pin will also be activated to output the control signal. The TCTL1 and TCTL2 timing is shown in figure 3.
PLEN ENLED
LEDO
10 kHZ
.......
40 kHZ
Option bit LEDF = 1
Figure 13. LEDO Timing
OPTION BIT AND PLEN PIN LEDF 0 0 1 1 PLEN Status inactive active inactive active
Table 38. LED option bit
FUNCTION LEDO output frequency 4 kHz 16 kHz 10 kHZ 40 kHZ
RESET CONDITION
The W93910 has two reset conditions. Power on & XRST active * Reset all 192 option bits and all remote programming registers * RFEN, PLEN, QC1, QC2, LOCK, MSGVAL, MCLK, MDATA in non-active state ON pin rising edge is occurred * Oscillator start oscillation * Reset channel number to CH3-CH0 of the 192 option bits * The values of remote programming registers is not changed
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W93910
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage temperature RATING -0.3 to +7.0 -0.3 to +7.0 120 -20 to +70 -55 to +155 UNIT V V mW C C
Note: The device should be operated under the above conditions. Operation beyond these conditions may result in permanent damage to the device.
DC/AC ELECTRONIC CHARACTERISTICS
(VDD = 3 volt, Fosc = 100 kHz, Ta = 25 C )
SYMBOL VDD IOP ISB VOH VOL VIH VIL IOH IOL TCHRS
PARAMETER Operating Voltage Operating Current Stand By current Output high voltage Output Low voltage Input high voltage Input low voltage Output High Current Output Low Current CHRS Active Width
CONDITION VDD = 3 volt ON = 0 volt
MIN. 2.5
TYP 3 25 1
MAX. 3.5 100 2
UNIT V A A V V V V A A S
NOTE
2.4 0.4 2 0.8 VO = 2.1 volt VO = 0.4 volt 500 500 1 4 1 20 20 1 10 1 3 4.5
TXCNCG XCNCG Active Width TTXCK TTDST TTDHD TOSC TXRST TPG TON TXCLK Period TXDATA Setup Time TXDATA Hold Time OSCO Stable Time XRST Active Width Programming setup TXCLK to ON delay
mS S nS nS S S S Txclk
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Publication Release Date: Auguest 1999 Revision A1
W93910
DC/AC Electronic Charac, continued
SYMBOL TOP TADDT TMSGV TMCLK
PARAMETER ON active to PLEN active delay ADRDET active to MCLK active MSGAVL active to MCLK active MCLK Period
CONDITION
MIN.
TYP 4
MAX.
UNIT S mS
NOTE
45 700 MCK1-0 = 00 MCK1-0 = 01 MCK1-0 = 10 MCK1-0 = 11 80 40 20 5 1/4 1/4 9.6 19.2 28.8 38 4.8 9.6 2.5 3.8 4 MCK1-0 = 11 UDI1-0 = 11 MCK1-0 = 00 UDI1-0 = 00 1.2 2 1.3 2.1
S S S S S Tmclk Tmclk mS mS mS mS mS mS mS mS mS mS mS
TMDST TMDHD TPLST
MDATA Setup Time MDATA Hold Time PLEN Pre-Active Time
MCLK active edge MCLK active edge PL1-0 = 00 PL1-0 = 01 PL1-0 = 10 PL1-0 = 11
TRFDY
RFEN Delay to Preamble QC1 Active Width MDATA D23 to Next unit D23 MCLK Stop Clock per byte MDATA D0 Delay to Next D23
RFON = 0 RFON = 1
TQC1W TUNIT TUDI TINT
QC1WTH = 0 QC1WTH = 1
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W93910
TYPICAL APPLICATION CIRCUIT
LCD
c1=20pf VDD OSCI 100khz OSCO W93910 VDD LEDO DO XRS ENLED CHRS TXCLK TXDATA TCTL2 TCTL1 RFEN QC1 RECEIVER QC2 D0 D1 VSS PLEN ON ADRDET SYNVAL XCNCG MDATA MCLK MSGVAL VSS CLK DATA EN VSS M 1.5V DC/DC UC 3V 1.5V VDD
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Publication Release Date: Auguest 1999 Revision A1
W93910
Package Information
D 28
DETAIL A
E E1
1
2
A2 SEATING PLANE 0.10 e b A1
A
e/2
R1 b/2 ODD EVEN DETAIL A
R1 0.25 L L1
O
Symbol Min. A A1 A2 b D E E1 e L L1 R1 O 0.09 0 0.55 0.05 1.65 0.22 9.9 7.40 5.00
Common Dimension (Millimeters) Nom. Max. 2.0 0.002 1.75 10.2 7.80 5.30 0.65 0.75 1.25 0.004 4 8 0 0.95 0.021 1.85 0.38 10.5 8.20 5.60 0.065 0.009 0.390 0.291 0.197 Min.
Common Dimension (Inches) Nom. Max. 0.079 0.069 0.401 0.307 0.209 0.0256 0.030 0.050 4 8 0.037 0.073 0.015 0.413 0.323 0.220
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W93910
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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Publication Release Date: Auguest 1999 Revision A1

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