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DM93L38 8-Bit Multiple Port Register
March 1989 Revised August 2000
DM93L38 8-Bit Multiple Port Register
General Description
The DM93L38 is an 8-bit multiple port register designed for high speed random access memory applications where the ability to simultaneously read and write is desirable. A common use would be as a register bank in a three address computer. Data can be written into any one of the eight bits and read from any two of the eight bits simultaneously. The circuit uses TTL technology and is compatible with all TTL families.
Features
s Master/slave operation permitting simultaneous write/ read without race problems s Simultaneously read two bits and write one bit in any one of eight bit positions s Readily expandable to allow for larger word sizes
Ordering Code:
Order Number DM93L38N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
VCC = Pin 16 GND = Pin 8
Pin Descriptions
Pin Names A0-A2 DA B0-B2 C0-C2 CP SLE ZB ZC Data Input B Read Address Inputs C Read Address Inputs Clock Pulse Input (Active Rising Edge) Slave Enable Input (Active LOW) B Output C Output Description Write Address Inputs
(c) 2000 Fairchild Semiconductor Corporation
DS010202
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DM93L38
Functional Description
The DM93L38 8-bit multiple port register can be considered a 1-bit slice of eight high speed working registers. Data can be written into any one and read from any two of the eight locations simultaneously. Master/slave operation eliminates all race problems associated with simultaneous read/write activity from the same location. When the clock input (CP) is LOW data applied to the data input line (DA) enters the selected master. This selection is accomplished by coding the three write input select lines (A0-A2) appropriately. Data is stored synchronously with the rising edge of the clock pulse. The information for each of the two slaved (output) latches is selected by two sets of read address inputs (B0-B2 and C0-C2). The information enters the slave while the clock is HIGH and is stored while the clock is LOW. If Slave Enable is LOW (SLE), the slave latches are continuously enabled. The signals are available on the output pins (ZB and ZC). The input bit selection and the two output bit selections can be accomplished independently or simultaneously. The data flows into the device, is demultiplexed according to the state of the write address lines and is clocked into the selected latch. The eight latches function as masters and store the input data. The two output latches are slaves and hold the data during the read operation. The state of each slave is determined by the state of the master selected by its associated set of read address inputs. The method of parallel expansion is shown in Figure 1. One DM93L38 is needed for each bit of the required word length. The read and write input lines should be connected in common on all of the devices. This register configuration provides two words of n-bits each at one time, where n devices are connected in parallel.
FIGURE 1. Parallel Expansion
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DM93L38
Logic Diagram
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DM93L38
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
-65C to +150C
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA tS (H) tS (L) tH (H) tH (L) tS (H) tS (L) tH (H) tH (L) tW (H) tW (L) Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW DA to CP Hold Time HIGH or LOW DA to CP Setup Time HIGH or LOW An to CP Hold Time HIGH or LOW An to CP CP Pulse Width HIGH or LOW Min 4.5 2 0.7 Norm 5 Max 5.5 Units V V V
-400
4.8
A
mA
-55
30 22 0
125
C
ns ns ns ns ns
-4.0
0 0 0 0 40 30
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = -10 mA VCC = Min, IOH = Max, VIL = Max, VIH = Min VCC = Min IOL = Max VIH = Min, VIL = Max VCC = Max, VI = 5.5V VCC = Max, VI = 2.4V VCC = Max, VI = 0.3V VCC = Max (Note 3) VCC = Max (Note 4) -2.5 2.4 0.3 1 50 -2 -25 70 Min Typ (Note 2) Max -1.5 Units V V V mA A mA mA mA
Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs OPEN and all input grounded.
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DM93L38
Switching Characteristics
VCC = +5.0V, TA = +25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Bn or Cn or Zn Propagation Delay DA to Zn Propagation Delay CP to Zn Parameter Min CL = 15 pF Max 68 95 70 92 65 57 ns ns ns Units
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DM93L38 8-Bit Multiple Port Register
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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