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User's Manual
PD4992
8-bit Parallel I/O Calendar Clock
Document No. S11812EJ4V0UM00 (4th edition) Date Published May 1998 N CP(K)
(c)
Printed in Japan
1998
[MEMO]
2
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M7 96.5
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[MEMO]
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CONTENTS
CHAPTER 1 OUTLINE OF PD4992 ................................................................................................ 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features .............................................................................................................................. Pin Connections ................................................................................................................ Pin Functions .................................................................................................................... Block Diagram ................................................................................................................... Oscillation Stage and 15-Stage Binary Divider ............................................................ Register Configuration ..................................................................................................... Notes on Use .....................................................................................................................
7 7 8 9 10 11 11 12 13 13 15 17 18 19 20 21
21 22 22 22
CHAPTER 2 OPERATIONS ............................................................................................................... 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Write Timing ....................................................................................................................... Read Timing ....................................................................................................................... Outline of Registers .......................................................................................................... RTC Counter (R/W) ........................................................................................................... 12/24H and AM/PM Flags (R/W) ...................................................................................... Leap Year Control Register and Leap Year Counter (R/W) ......................................... Mode Register (R/W) .........................................................................................................
2.7.1 2.7.2 2.7.3 2.7.4 2.8.1 2.8.2 TP output (1) (continuous pulse output) ................................................................................ TP output (2) (interval pulse output) ...................................................................................... TP output (3) (BUSY output) .................................................................................................. Test mode ................................................................................................................................ Write control register ............................................................................................................... Read control register ..............................................................................................................
2.8 Control Register ................................................................................................................
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24 27
CHAPTER 3 ACCESS PROCEDURE ............................................................................................... 3.1 Time Setting ....................................................................................................................... 3.2 Reading the Time ..............................................................................................................
3.2.1 3.2.2 3.2.3 3.2.4 Using BUSY signal to interrupt CPU (TP: BUSY signal output) ........................................... Polling BUSY flag .................................................................................................................... Reading the time twice ........................................................................................................... Limitations on reading time ....................................................................................................
29 29 30
30 32 33 34
3.3 Setting TP Output ............................................................................................................. 3.4 Setting When OSC Flag Is "0" ........................................................................................
35 36
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE ................................................. 4.1 Crystal Oscillation Circuit ............................................................................................... 4.2 Oscillation Characteristics and Accuracy .....................................................................
4.2.1 4.2.2 Dependency on load capacitance .......................................................................................... Dependency on temperature ..................................................................................................
39 39 40
40 42
4.3 Adjusting Oscillation Frequency .................................................................................... 4.4 Backup Circuit ................................................................................................................... 4.5 Power-Fail Circuit .............................................................................................................
42 43 44
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CHAPTER 1 OUTLINE OF PD4992
The PD4992 is a CMOS IC that inputs or outputs 8-bit parallel real-time clock or calendar data from or to a microprocessor based system. This IC has seven types of internal counters: year, month, day, date, hour, minute, and second. The hour counter can operate in 12-hour or 24-hour mode. This IC can operate at a voltage of 2.4 to 5.5 V, and can use a battery backup. Because a constant-voltage circuit is provided as a reference oscillation source, the current consumption can be kept low and the accuracy can be kept high even if the supply voltage fluctuates. This makes the PD4992 ideal for electronic systems requiring a real-time clock function, such as personal computers, word processors, facsimiles, VCRs, and cameras.
1.1 Features
* * * * * * * *
Internal counters for real-time clock (RTC) (hour, minute, second) and calendar (leap year, year, month, day, date) Super low current consumption (IDD = 2 A MAX. @VDD = 2.4 V) Automatic identification and manual setting of leap year 12-/24-hour mode selectable 3-bit parallel input address bus and 8-bit parallel I/O data bus 12 types of interval timer output (can be used as watchdog timer) Validity of time data can be checked during backup by internal oscillation stop detection circuit High accuracy Basic specifications * Reference frequency (crystal oscillation): 32.768 kHz * Data format: BCD format * Data function Year, month, day, date, hour, minute, and second counters The leap year is automatically identified until 2099 (a year whose low-order 2 digits are a multiple of 4 is identified as a leap year), and can be set manually by the user. A year can be set using the low-order 2 digits. Hours can be indicated in 12- or 24-hour mode. * Data input/output (D0 through D7) 8-bit parallel I/O mode Data writing is enabled by WR signal and reading is enabled by RD signal to input/output data. * Timing pulse output (TP output) One pulse with a duty factor of 50% can be selected from 2048, 1048, 256, or 64 Hz. Or, one interval timer output can be selected from 1/2048, 1/1024, 1/256, 1/64, 1, 10, or 60 s. * Chip select (CS1, CS2) CS1 = "H" or CS2 = "L": Disables all inputs except XIN. CS1 = "L" and CS2 = "H": Selects all inputs.
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CHAPTER 1 OUTLINE OF PD4992
1.2 Pin Connections
PD4992CX/PD4992GS
TP
1
20
VDD
CS1
2
19
XIN
WR
3
18
XOUT
A0
4
17
CS2
A1
5
16
D7
A2
6
15
D6
RD
7
14
D5
D0
8
13
D4
D1
9
12
D3
VSS
10
11
D2
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CHAPTER 1 OUTLINE OF PD4992
1.3 Pin Functions
Pin Symbol CS1 CS2 WR Pin Name Chip select input Chip select input Write signal input 2 17 3 Pin No. Function Access to the internal registers is enabled when CS1 = L, CS2 = H. The contents of the data bus are written to the register selected by inputting an address at the rising edge of this signal. The contents of the register selected by inputting an address are output to the data bus at the falling edge of this signal. Data I/O bus. Input an address to select an internal register. Outputs an interval signal or timing pulse (N-ch open drain output). Connect a crystal resonator and a capacitor.
RD
Read signal input
7
D0 to D7 A0 to A2 TP
Data I/O Address input Timing pulse output
8, 9, 11 to 16 4 to 6 1
XIN XOUT VDD VSS
Crystal resonator connecting pin Crystal resonator connecting pin Power supply pin Ground pin
19 18 20 10
2.4 V to 5.5 V Ground
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CHAPTER 1 OUTLINE OF PD4992
1.4 Block Diagram
OSC Rf XIN RD
15-Stage Binary Divider Time Counter
Minute
Month
Hour
XOUT
Clock Stop
CS1 TP CS2 TP Generator
RD
WR
8 D0-D7
Data Bus Controller
Mode Register Control Register
3 A0-A2
Address Bus Controller
Address Decoder
10
Year
Date
1/215
Second
Day
CHAPTER 1 OUTLINE OF PD4992
1.5 Oscillation Stage and 15-Stage Binary Divider
A reference frequency of 32.768 kHz is obtained by using a 32.768-kHz crystal resonator and a crystal oscillation circuit that uses a CMOS inverter. This reference frequency is divided by 15 to create 1 Hz (1 second) to be input to the time counter.
1.6 Register Configuration
Table 1-2 shows the register configuration. Table 1-2. Register Configuration
Address HEX 0H 1H 2H 3H 4H 5H 6H 7H A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 12/24H b7 b6 b5 Register Contents b4 b3 b2 b1 b0
10-second digit 10-minute digit AM/PM 10-hour digit
1-second digit 1-minute digit 1-hour digit Date digit 1-day digit 1-month digit 1-year digit Control register
Leap year control Leap year counter 10-day digit 10-month digit 10-year digit Mode register
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CHAPTER 1 OUTLINE OF PD4992
1.7 Notes on Use
(1) Be sure to stop the clock (by means of CLK stop) before writing time data. For details, refer to 3.1 Time Setting. (2) To change the hour mode between 12-hour and 24-hour, be sure to rewrite AM/PM and the 10-hour digit, as well as the value of b7. (3) Before changing the setting of the leap year counter, be sure to rewrite the year counter. For details, refer to 2.6 Leap Year Control Register and Leap Year Counter. (4) Adjust the oscillation frequency by using TP output. If XIN and XOUT are used to adjust the oscillation frequency, oscillation may be stopped. (5) While the CPU is in back-up state, keep the CS2 pin low. For details, refer to 4.5 Power-Fail Circuit. (6) Because only the low-order 2 digits of the year code are supported, set the low-order 2 digits of a year. Even when the year changes from 1999 to 2000 (year code: 99 00), the PD4992 correctly counts time. Although leap years are automatically identified until 2099, adjustments such as re-setting the date are necessary in 2100. This is because this IC identifies 2100 as a leap year even though it is not. The other functions of the IC are not affected when the user makes such adjustments. (7) The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. The characteristic examples and the description of the application examples in this document are only for this IC alone, and it is still necessary to confirm that there are no problems when the IC is incorporated in your own system designs.
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CHAPTER 2 OPERATIONS
2.1 Write Timing
Write data to the internal registers in the following procedure. (1) Make CS2 high. (2) Specify an address value at address pins A0 through A2. (3) Make CS1 low. (4) Make WR low, and then high; the values of data pins D0 through D7 will be written to the internal registers at the rising edge of WR. Table 2-1 and Figures 2-1 and 2-2 indicate the definition of write timing. Table 2-1. Switching Characteristics Write cycle (CS2 = H)
Parameter Cycle time CS1-WR reset time Address-WR reset time Address-WR setup time Write pulse width Address hold time Input data setup time Input data hold time WR-output floating time Symbol tWC tCW tAW tAS tWP tWR tDW tDH tWHZ MIN. 150 120 120 0 90 20 50 0 50 TYP. MAX. Unit ns
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CHAPTER 2 OPERATIONS
Figure 2-1. Write Cycle Timing 1
tWC ADDRESS
RD
tAW tCW
CS1 tAS WR tOHZ DOUT tDW DIN tDH tWP tWR
Figure 2-2. Write Cycle Timing 2 (RD = VIL)
tWC ADDRESS tAW tCW CS1
tAS WR
tWP
tWR
tWHZ DOUT
tOW
tDW DIN
tDH
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CHAPTER 2 OPERATIONS
2.2 Read Timing
Read data from the internal registers in the following procedure. (1) Make CS2 high. (2) Specify an address value at address pins A0 through A2. (3) Make CS1 low. (4) Make RD low; the value of an internal register will be read to data pins D0 through D7 at the falling edge of RD. Table 2-2 and Figures 2-3 and 2-4 indicate the definition of read timing. Table 2-2. Switching Characteristics Read cycle (CS2 = H)
Parameter Cycle time Address access time CS1-access time RD-output delay time Symbol tRC tAA tACS tOE tOLZ tOHZ Output hold time CS1-output setup time CS1-output floating time tOH tCLZ tCHZ 15 10 5 5 50 MIN. 150 150 150 75 TYP. MAX. Unit ns
Figure 2-3. Read Cycle Timing 1
CS1
tRC ADDRESS
tAA RD
tOH
tOE DOUT tOLZ Data output
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CHAPTER 2 OPERATIONS
Figure 2-4. Read Cycle Timing 2
ADDRESS
tRC CS1
tACS RD
tCHZ
tCLZ DOUT
tOHZ Data output
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CHAPTER 2 OPERATIONS
2.3 Outline of Registers
The registers of the PD4992 are allocated as shown in Table 2-3. Addresses 0H through 6H are for time data, and address 7H is a mode register and a control register. Bits b7 and b6 of address 2H are a 12/24H and AM/PM flags, and b7 through b4 of address 3H are a leap year control register and a leap year counter. Table 2-3. Correspondence between Registers and Addresses
Address HEX 0H 1H 2H 3H 4H 5H 6H 7H A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 12/24H b7 b6 b5 Register Contents b4 b3 b2 b1 b0
10-second digit 10-minute digit AM/PM 10-hour digit
1-second digit 1-minute digit 1-hour digit Date digit 1-day digit 1-month digit 1-year digit Control register
Leap year control Leap year counter 10-day digit 10-month digit 10-year digit Mode register
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CHAPTER 2 OPERATIONS
2.4 RTC Counter (R/W)
Input or output clock data by writing or reading the RTC counter and calendar counter. The data that can be written are as follows:
Register 1-second digit 10-second digit 1-minute digit 10-minute digit 1-hour digit 10-hour digit (including flag) Date digit 1-day digit 10-day digit 1-month digit 10-month digit 1-year digit 10-year digit 0 through 9 0 through 5 0 through 9 0 through 5 0 through 9 0 through 2 (24-hour mode)/8, 9, C, D (12-hour mode) 0 through 6 0 through 9 0 through 3 (except February)/0 to 2 (February) 0 through 9 0 through 1 0 through 9 0 through 9 Data That Can Be Written
For the counter data of the 1-hour and 10-hour digits, refer to Table 2-4. The date digit can take a value of 0H to 6H and counts up (+1) in synchronization with the 1-day digit. It goes back to 0H after 6H. The date of the week is arbitrarily assigned. Each register is automatically incremented. While it is possible to write data other than the above or a time that does not actually exist, the registers cannot be correctly incremented in that event. Write only time data that is actually feasible and that is correct. Example 23 hours 45 minutes 01 second (in 24-hour mode) on Thursday, October 8, 1998
Register Second counter Minute counter Hour counter Leap year, date counter Day counter Month counter Year counter Data (Hex) 01 45 23 24 08 10 98 b7 0 0 0 0 0 0 1 b6 0 1 0 0 0 0 0 b5 0 0 1 1 0 0 0 b4 0 0 0 0 0 1 1 b3 0 0 0 0 1 0 1 b2 0 1 0 1 0 0 0 b1 0 0 1 0 0 0 0 b0 1 1 1 0 0 0 0
In this example, the date counter is set so that Sunday is "0". For the leap year counter, refer to Table 2-5.
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CHAPTER 2 OPERATIONS
2.5 12/24H and AM/PM Flags (R/W)
The 12/24H flag selects the 12- or 24-hour mode of the hour counter of the PD4992. 12/24H flag = 0: 24-hour mode 12/24H flag = 1: 12-hour mode The AM/PM flag indicates either morning or afternoon in the 12-hour mode (when the 12/24H flag = 1). AM/PM flag = 0: Morning (AM 12 hours 00 minutes 00 seconds to AM11 hours 59 minutes 59 seconds) AM/PM flag = 1: Afternoon (PM 12 hours 00 minutes 00 seconds to AM 11 hours 59 minutes 59 seconds) In the 24-hour mode (12/24H flag = 0), the AM/PM flag is always "0". Table 2-4 shows the time counter data including the 12/24H and AM/PM flags. Table 2-4. Time Counter Data
Time AM 1 AM 2 AM 3 AM 4 AM 5 AM 6 AM 7 AM 8 AM 9 AM 10 AM 11 PM 12 24-Hour Mode 01H 02H 03H 04H 05H 06H 07H 08H 09H 10H 11H 12H 12-Hour Mode 81H 82H 83H 84H 85H 86H 87H 88H 89H 90H 91H D2H Time PM 1 PM 2 PM 3 PM 4 PM 5 PM 6 PM 7 PM 8 PM 9 PM 10 PM 11 AM 12 24-Hour Mode 13H 14H 15H 16H 17H 18H 19H 20H 21H 22H 23H 00H 12-Hour Mode C1H C2H C3H C4H C5H C6H C7H C8H C9H D0H D1H 92H
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CHAPTER 2 OPERATIONS
2.6 Leap Year Control Register and Leap Year Counter (R/W)
The leap year control register turns the identification of leap years on and off, and enables or disables writing to the leap year counter. Table 2-5 shows the allocation of the leap year control register. Because the leap year counter does not have to be written again once it has been written, it is usually set to "x0" (disabling writing the leap year counter). Table 2-5. Leap Year Control Register
b7 0 0 1 1 b6 0 1 0 1 Mode Identifies leap year, writing leap year counter is disabled. Identifies leap year, writing leap year counter is enabled. Ignores leap year, writing leap year counter is disabled. Ignores leap year, writing leap year counter is enabled.
The user does not have to set the leap year counter if the low-order 2 digits of the year have been written to the year counter. The user can write any data to the leap year counter. A leap year is identified when the value of the leap year counter is "00". Be sure to write data to the leap year counter after setting the year counter. If the leap year counter is set after the year counter, the leap year counter is re-set regardless of the setting of the leap year control register. Example The leap year counter is automatically set if the year counter is set. Year 1997 1998 1999 2000 * * * 2015 2016 Year counter "10010111" "10011000" "10011001" "00000000" * * * "00010101" "00010110" (15) (16) (97) (98) (99) (00) Leap year counter "01" "10" "11" "00" * * * "11" "00" (3) (0) (1) (2) (3) (0)
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CHAPTER 2 OPERATIONS
2.7 Mode Register (R/W)
The mode register to specify TP output and the test mode. Table 2-6 lists the functions of the mode register. Table 2-6. Mode Register List
HEX 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH b7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mode TP 2048 Hz output TP 1024 Hz output TP 256 Hz output TP 64 Hz output INT 1/2048 s output INT 1/1024 s output INT 1/256 s output INT 1/64 s output INT 1 s output INT 10 s output INT 60 s output BUSY signal output Test mode
2.7.1 TP output (1) (continuous pulse output) When a value between 0H and 3H is written to the mode register, pulses with a frequency of between 64 and 2048 Hz and a duty factor of 50% are continuously output from the TP pin (refer to Figure 2-5). Figure 2-5. Continuous Pulse Output
1/f
Continuous pulse output with 50% duty
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CHAPTER 2 OPERATIONS
2.7.2 TP output (2) (interval pulse output) Pulses are output from the TP pin at intervals of between 1/2048 and 60 seconds when a value between 4H and AH is written to the mode register. The pulse width is 30.5 s (refer to Figure 2-6). Figure 2-6. Interval Pulse Output
T
T
INT reset
30.5 s
2.7.3 TP output (3) (BUSY output) The BUSY signal is output from the TP pin when BH is written to the mode register. While this BUSY signal is low, reading the counters is disabled and the counters are internally incremented in this period. The BUSY signal is used to read time data at its rising or falling edge. For an example of using the BUSY signal, refer to 3.2.1. 2.7.4 Test mode The test mode is selected when CH to FH is written to the mode register. Do not use this mode for normal operation.
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CHAPTER 2 OPERATIONS
2.8 Control Register
The control register sets the clock (CLK) of the RTC counter and controls the TP pin when data is written to it. When it is read, the register is used to check the TP, OSC, and BUSY flags. Table 2-7 lists the functions of the control register. Table 2-7. Control Register
Access Mode Write b3 0 b2 CLK adjustNote 4 0: NOP 1: CLK adjust 1 TP enableNote 1 0: TP = ENABLE 1: TP = DISABLE Read * (Don't care) TP flag 0: TP = Z 1: TP = L b1 CLK resetNote 4 0: NOP 1: Reset INT resetNote 4 0: NOP 1: Reset OSC flagNote 2 0: Oscillation stop 1: Oscillation CLK stop 0: CLK start 1: CLK stop INT stop 0: INT start 1: INT stop BUSY flagNote 3 0: OFF 1: ON b0
Notes 1. When the TP enable flag is set to "1" (TP = DISABLE), the TP pin forcibly goes into a high-impedance state (actually, goes high because a pull-up resistor is connected to the TP pin). 2. When oscillation is stopped and the OSC flag is reset to "0", the OSC flag remains "0" even if oscillation is later resumed. To set the OSC flag to "1", execute CLK reset. If the OSC flag still remains "0" even after CLK reset has been executed, oscillation remains stopped. If the OSC flag is "0", TP output is disabled. The OSC flag is reset to "0" on the first power application to the PD4992. Be sure to initialize the OSC flag before using it. 3. The BUSY flag is set to "1" while the time counter of the PD4992 is operating (while reading the counter is disabled). 4. Be sure to return the CLK adjust, CLK reset, and INT reset flags to NOP ("0") after setting these flags to "1". Otherwise, adjust and reset remain valid, and unexpected operation may occur when data is subsequently written.
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CHAPTER 2 OPERATIONS
2.8.1 Write control register Data writing to the control register is to select whether CLK or TP pin is to be controlled depending on the status of b3. (1) When b3 = 0 The CLK stop and CLK reset flags are assigned to b0 and b1, respectively. CLK stop : Stops the 1-second pulse signal to the second digits of the RTC counter to prevent the counter from being incremented. CLK reset : Resets the 15-stage binary divider (32.768 kHz 1 Hz). For details of how to use these flags, refer to CHAPTER 3. The CLK adjust flag is assigned to b2. When b2 = 1, an adjustment of 30 seconds is made and the second counter is reset (to 00 second). The BUSY flag is 1 while the CLK adjust operation is performed. Every minute 00 second to 29 seconds Every minute 00 second to 59 seconds CLK adjust CLK adjust 00 second (digits other than second digits are not affected) 00 second + Digits higher than minute digits are incremented. Incrementing affects all the digits. Example 11 hours 59 minutes 45 seconds in the afternoon on December 31, 1995 CLK adjust 0 hour (2) When b3 = 1 The INT stop, INT reset, and TP enable flags are assigned to b0, b1, and b2, respectively. INT stop : Stops the internal clock for interval pulse output and retains the status in which the output goes into a high-impedance state. Allows continuous operation of output by releasing the stop mode. INT reset : Allows the output to go into a high-impedance state regardless of the status of interval pulse output. Also resets the internal clock for interval pulse. The interval pulse operation continues. TP enable : Enables TP output. If this flag is disabled, output forcibly goes into a high-impedance state, regardless of the status of the interval pulse output. However, the TP and BUSY flags are not disabled even in this case. For how to use these flags, refer to Figure 2-7. 0 minute 0 second in the morning on January 1,1996
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CHAPTER 2 OPERATIONS
Figure 2-7. Example of Controlling TP Pin (in INT output mode) (1) Use of INT reset (1)
T
T
INT reset
30.5 s
(2) Use of INT reset (2)
T INT output
T
INT reset
INT reset
(3) Use of INT stop (1)
t1 INT output
t2 T = t1 + t2
INT stop
INT stop cleared
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CHAPTER 2 OPERATIONS
(4) Use of INT stop (2)
30.5 s T INT output
INT stop
INT stop cleared
(5) Use of INT reset and stop
t1 INT output
T
INT stop
INT reset
INT stop cleared
(6) Use of TP enable
T INT output
T
TP DISABLE
TP ENABLE
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CHAPTER 2 OPERATIONS
2.8.2 Read control register When the control register is read, the BUSY, OSC, and TP flags can be read. b3 is don't care. (1) BUSY flag (b0) The BUSY flag is set to ON (b0 = 1) while the internal counter operates (for the ON period, refer to Figure 2-8). By checking (polling) this flag before reading time, therefore, the correct time data can be read. For details, refer to 3.2.2. Even if data is read during the BUSY period, the internal counter is not affected. Figure 2-8. Relation between Internal Counter, BUSY Signal Output, and BUSY Flag
Incrementing 1-s digit Internal carry pulse 1 Hz
Incrementing 1-s digit
BUSY signal output TP output disabled
457.7 s
30.5 s
BUSY flag ON
BUSY flag OFF
BUSY flag ON
(2) OSC flag (b1) The OSC flag is reset to "0" when the 32.768-kHz reference crystal resonator stops oscillating. Once the OSC flag has been reset to "0", it remains "0" even if oscillation has been resumed. This means that, when the operation mode has returned from the backup mode to the operation mode, whether the PD4992 has been correctly backed up can be checked by reading this flag. To set the OSC flag to "1", execute CLK reset. When the OSC flag is reset to "0", TP output is disabled, regardless of the contents of the TP enable flag (in the control register). For details, refer to 3.4. The OSC flag is reset to "0" on the first power application to the PD4992. (3) TP flag (b2) The TP flag is synchronized with the TP output. It is reset to "0" when TP output goes into a high-impedance state, and is set to "1" when TP output goes low. The TP flag is not forcibly reset to "0" even if the TP enable flag is set to "1" (TP = DISABLE).
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[MEMO]
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CHAPTER 3 ACCESS PROCEDURE
3.1 Time Setting
Because the time counter is updated real-time, it may be set to the wrong value if it is incremented while data is being written to it because of the lapse of time. Therefore, the clock input to the time counter must be stopped before setting the time. Figure 3-1 shows a flowchart illustrating how to set the time. Figure 3-1. Setting the Time
Start Note 1 CLK reset Address 7H *2H (*: don't care)
Note 1 CLK reset/stop Address 7H *3H (*: don't care)
Time data write routine
Address 0H to 6H Note 2
Start wait
NO
Start?
YES
CLK start
Address 7H *0H (*: don't care)
End
Notes 1. It is necessary to write the CLK reset/stop flag after writing the CLK reset flag. 2. It is not necessary to write data to the leap year counter if data is written to the low-order 2 digits of the year counter. 3. The usage shown above is on the assumption that it takes 1 second or more to set the time. Make sure that it takes 1 second or more to set the time (from CLK reset/stop to CLK start).
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CHAPTER 3 ACCESS PROCEDURE
3.2 Reading the Time
Because the time counter is updated every second, the wrong time data may be read if the time counter is read while it is being incremented. Therefore, read the time by either of the following two methods. <1> Use the BUSY signal as an interrupt. Or, poll the BUSY flag. Read the time by outputting the BUSY signal to the TP pin or by reading the BUSY flag. <2> Read the time twice and take the read value as valid when the two read values coincide. 3.2.1 Using BUSY signal to interrupt CPU (TP: BUSY signal output) It is possible to read time data every second by outputting the BUSY signal to the TP pin (address 7H B*H where * is don't care) and by using the rising or falling edge of the BUSY signal to interrupt the CPU. If it takes the CPU less than 457.7 s to read the time data of the PD4992 after the interrupt, use the falling edge of the BUSY signal. Use the rising edge of the BUSY signal if it takes 457.7 s or more. Figure 3-2 shows the waveform of the BUSY signal, and Figure 3-3 shows a flowchart illustrating how the BUSY signal is used to interrupt the CPU. Figure 3-2. BUSY Signal Waveform
457.7 s
30.5 s
BUSY
Can be accessed
Can be accessed
Cannot be accessed
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CHAPTER 3 ACCESS PROCEDURE
Figure 3-3. Using BUSY Signal to Interrupt CPU
Main routine
Processing 1
Monitor BUSY signal and issue interrupt every second.
Time read routine
Access to PD4992 (address 0H to 6H)
Processing 2
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CHAPTER 3 ACCESS PROCEDURE
3.2.2 Polling BUSY flag The BUSY signal can be also used by polling the BUSY flag. The BUSY flag is assigned to b0 of address 7H (control register). Check (poll) the BUSY flag before reading the time, confirm that it is "0", and read the time. When the BUSY flag is "1", the chances are that the time counter is being incremented. Wait until the BUSY flag is reset to "0". When polling the BUSY flag, make sure that it takes less than 457.7 s to completely read the time from the start. If it takes 457.7 s or longer, the time may be incremented while it is being read, and the wrong time data may be read. Figure 3-4 shows how to poll the BUSY flag. Figure 3-4. Polling BUSY Flag
Start
Read control register
Read address 7H
BUSY? Yes (b0 = 1) No (b0 = 0)
Read time
Access address 0H to 6H
End of reading? No
Yes
End
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CHAPTER 3 ACCESS PROCEDURE
3.2.3 Reading the time twice Read the time twice and compare the read values. When both the values coincide, it can be assumed that the time value is correct. To ensure the correct operation, make sure that the rated values of the switching characteristics are satisfied when the time is read. If the first time value is read and the second value is read more than 1 second later, the two values do not coincide and therefore, the correct time value can not be determined. Figure 3-5 shows how to read the time value twice. Figure 3-5. Reading Time Twice
Start
First reading of time Memory1
Second reading of time Memory2
No
Memory1 = Memory2?
Yes
End
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CHAPTER 3 ACCESS PROCEDURE
3.2.4 Limitations on reading time With the PD4992, clock stop and clock start, which are two of the methods of reading the time with NEC's 4-bit parallel I/O calendar RTC PD4991A, cannot be used (because the time may be delayed). Therefore, use either of the following methods to read the time of the PD4992. <1> Use the BUSY signal for interrupt, or poll the BUSY flag. <2> Read time twice and assume that the read time value is true only if the two values coincide.
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CHAPTER 3 ACCESS PROCEDURE
3.3 Setting TP Output
TP output is set by using the mode register (address 7H). Because the interval timer is independent of the time counter, it can be independently stopped, resumed, or reset. Figure 3-6 illustrates how to set TP output. Figure 3-6. Setting TP Output
Start
TP output control
Address 7H *FH (TP = DISABLE, INT reset/stop)
TP output select
Address 7H Select 0FH to BFH
TP output control
Address 7H Select 08H to B8H (same value as when TP output is selected) (TP = ENABLE, INT start)
End
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CHAPTER 3 ACCESS PROCEDURE
3.4 Setting When OSC Flag Is "0"
The OSC flag (b1 of address 7H) is reset to "0" on power application or on stopping oscillation. In this case, the internal status is undefined, but TP output is disabled, regardless of the contents of the internal registers (refer to Figure 3-7). To clear this disabled status, execute CLK reset and set TP output, as illustrated by the flowchart in Figure 3-8. Figure 3-7. TP Pin Control Equivalent Circuit
OSC flag 0: Oscillation stops 1: Oscillates TP enable 0: ENABLE 1: DISABLE TP pulse
TP output pin
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CHAPTER 3 ACCESS PROCEDURE
Figure 3-8. Setting when OSC Is "0"
Start
TP output control/ TP output select
Address 7H 0FH to BFH Note (TP = DISABLE, INT reset/stop)
Note 1 CLK reset Address 7H *2H (*: don't care)
NO OSC flag = 1? YES Note 1 CLK reset/stop Address 7H *3H (*: don't care)
TP output control
Address 7H *8H Note 2 (*: don't care) (TP = ENABLE, INT start)
Time data write routine
Address 0H to 6H Note 3
Start wait
NO Start? YES Address 7H *0H (*: don't care)
CLK start
End
Notes 1. It is necessary to write the CLK reset/stop flag after writing the CLK reset flag. 2. This is not necessary when TP output is not used. 3. It is not necessary to write data to the leap year counter if data is written to the low-order 2 digits of the year counter. 4. The usage shown above is on the assumption that it takes 1 second or more to set the time. Make sure that it takes 1 second or more to set the time (from CLK reset/stop to CLK start).
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[MEMO]
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE
4.1 Crystal Oscillation Circuit
The PD4992 uses an oscillation circuit that consists of a single-stage CMOS inverter, feedback resistor Rf, and oscillation stabilization resistor RD. Figure 4-1 shows the equivalent circuit of the oscillation circuit. The oscillation frequency of this circuit is determined by external load capacitances CG and CD, and crystal resonator. Because the stray capacitances of XIN and XOUT must be taken into consideration in addition to CG and CD, either CG or CD must be fine-tuned. Figure 4-1. Crystal Oscillation Circuit of PD4992
Rf VDD
To 15-stage binary divider Constant-voltage circuit RD Internal circuit
XIN External circuit
X
XOUT X : 32.768 kHz
CG
CD
VDD or VSS A
Connect point A in Figure 4-1 to VDD or VSS of the PD4992 (there is not much difference in characteristics regardless of whether this point is connected to VDD or VSS). Keep the wiring of the crystal resonator as short as possible. If the wiring length is too long, oscillation may not be stabilized and the accuracy of the RTC may be affected by external noise.
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE
4.2 Oscillation Characteristics and Accuracy
The accuracy of the RTC function of the PD4992 is determined by the accuracy of the oscillation frequency. The oscillation frequency is affected by the load capacitance and temperature. 4.2.1 Dependency on load capacitance Figure 4-2 shows a circuit to test the dependency of the oscillation frequency on load capacitance under conditions of VDD = +5 V, TA = +25 C. The test results are shown in the following figures. Figure 4-3: Changes in frequency when CG and CD are changed at the same time Figure 4-4: Changes in frequency when CG is changed (CD = 18 pF) Figure 4-5: Changes in frequency when CD is changed (CG = 18 pF) If CG and CD are too high (50 pF or more), the oscillation characteristics are affected. The characteristics are also affected by the crystal resonator actually used and the stray capacitance of the printed circuit board. Figure 4-2. Test Circuit
PD4992
XOUT 18
XIN 19
XOUT
XIN
Resonator: DT-38 (Daishinku Corp.)
CD
CG
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE
Figure 4-3. Changes in Frequency When CG and CD Are Changed at Same Time
40
Changes in frequency (ppm)
30 20 10 0 - 10 - 20 - 30 - 40 - 50 - 60 10 15 20 25 30 CD = CG (pF) 35 40 45
Figure 4-4. Changes in Frequency When CG Is Changed (CD = 18 pF)
Changes in frequency (ppm)
30 20 10 0 - 10 - 20 - 30 10 15 20 25 30 CG (pF) 35 40 45
Figure 4-5. Changes in Frequency When CD Is Changed (CG = 18 pF)
Changes in frequency (ppm)
30 20 10 0 - 10 - 20 10 15 20 25 30 CD (pF) 35 40 45
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE
4.2.2 Dependency on temperature The oscillation frequency changes with ambient temperature. Figure 4-6 shows the ambient temperature vs. oscillation frequency characteristics. As can be seen, the temperature characteristic curve is of the negative second order with its summit at around 25 C. This is the specific temperature characteristic of a tuning fork crystal resonator. Figure 4-6. Temperature Characteristics of Crystal Resonator and PD4992 (CD = CG = 18 pF)
50
Changes in frequency (ppm)
0 - 50 - 100 - 150 - 200 - 250 - 50 Resonator Circuit
0
50
100
Ambient temperature (C)
4.3 Adjusting Oscillation Frequency
The accuracy of the RTC depends on the stability of the oscillation frequency. To improve the accuracy, therefore, the oscillation frequency must be adjusted. Use CG or CD as a trimmer capacitor. Use the TP output pin for adjustment. Adjust the trimmer capacitor so that the measured value falls within the rated frequency range, while measuring the INT output by using a frequency counter. Be sure to use the TP output pin for measurement. Using a test probe on the XIN or XOUT pin may stop oscillation or makes it impossible to measure an accurate value because the oscillation frequency is affected by the capacitance of the probe.
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE
4.4 Backup Circuit
The PD4992 can be backed up by low-capacity batteries because it is a CMOS IC that operates with low current consumption. Figure 4-7 shows an example of backing up the PD4992 with a Ni-Cd battery, while Figure 4-8 shows an example of using a super capacitor (high-capacity, electric double layer capacitor). Figure 4-7. Backup Circuit Example with Ni-Cd Battery
1SS53 +5 V 15 k VDD 510 1SS53 + C 4.7 k GND C: Electrolytic capacitor (1 to 10 F) 2SC2785 Ni-Cd 3.6 V VSS TP
+5 V
2SA1175 1 k
PD4992
10 k
Figure 4-8. Backup Circuit Example with Super Capacitor
D +5 V
+5 V R VDD
Super capacitor
+ C
PD4992
10 k TP
GND
VSS C: Electrolytic capacitor (1 to 10 F) R: Resistor for inrush current prevention D: Schottky barrier diode
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE
4.5 Power-Fail Circuit
While the PD4992 is backed up, it is necessary to prohibit external access to the IC by fixing the CS2 pin to the low level. The power-fail circuit, therefore, must fix CS2 to the low level if the power supply to the system drops below the operating voltage of the CPU (e.g., 4.5 V or less), and keep CS2 low until the CPU operates again (refer to Figure 4-9). Figure 4-10 shows an example of a circuit that detects a drop in the system power supply and prohibits access to the internal circuits of the PD4992. This circuit consists of a Zener diode and transistors. Figure 4-9. Backup Status and CS2 Pin Voltage
System: 5 V Lower limit of operating voltage of CPU
CS2 pin of PD4992
VIH
Backup voltage x 0.3 or less Backup status
Figure 4-10. Example of Power-Fail Circuit
To VDD of PD4992 10 k
To +5-V power supply of system 10 k 2SC945 10 k RD3.9E 10 k
2SA733
To CS2 of PD4992
10 k
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
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[MEMO]
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[MEMO]
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