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UCC1895 UCC2895 UCC3895
BiCMOS Advanced Phase Shift PWM Controller
FEATURES
* Programmable Output Turn-on Delay * * * * * * *
DESCRIPTION
The UCC3895 is a phase shift PWM controller that implements control of a full-bridge power stage by phase shifting the switching of one half-bridge Adaptive Delay Set with respect to the other. It allows constant frequency pulse-width modulaBidirectional Oscillator Synchronization tion in conjunction with resonant zero-voltage switching to provide high efficiency at high frequencies. The part can be used either as a voltage mode Capability for Voltage Mode or Current or current mode controller. Mode Control While the UCC3895 maintains the functionality of the UC3875/6/7/8 family Programmable Soft Start/Soft Stop and UC3879, it improves on that controller family with additional features and Chip Disable via a Single Pin such as enhanced control logic, adaptive delay set, and shutdown capability. Since it is built in BCDMOS, it operates with dramatically less supply 0% to 100% Duty Cycle Control current than it's bipolar counterparts. The UCC3895 can operate with a 7MHz Error Amplifier maximum clock frequency of 1MHz. Operation to 1MHz The UCC3895 and UCC2895 are offered in the 20 pin SOIC (DW) package, 20 pin PDIP (N) package, 20 pin TSSOP (PW) package, and 20 pin PLCC (Q). The UCC1895 is offered in the 20 pin CDIP (J) package, and 20 pin CLCC package (L).
* Low Active Current Consumption (5mA Typical @ 500kHz) * Very Low Current Consumption During Undervoltage Lock-out (150 A typical)
SIMPLIFIED APPLICATION DIAGRAM
UCC3895 1 EAN EAP 20 7
Q1 VOUT
2
EAOUT
SS/DISB
19
3
RAMP
OUTA
18
4
REF
OUTB
17
A
C
5
GND
PGND
16
VIN VBIAS
6
SYNC
VCC
15
7
CT
OUTC
14 B D
8
RT
OUTD
13
9
DELAB
CS
12
10
DELCD
ADS
11
UDG-98139
SLUS157B - DECEMBER 1999 - REVISED JANUARY 2001
UCC1895 UCC2895 UCC3895 ABSOLUTE MAXIMUM RATINGS
Supply Voltage (IDD < 10mA) . . . . . . . . . . . . . . . . . . . . . . . 17V Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA REF current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA OUT Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Analog inputs (EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB) . . . . . . . . . . . -0.3V to REF+0.3V Power Dissipation at TA=+25C (N Package). . . . . . . . . . . . 1W Power Dissipation at TA=+25C (D Package) . . . . . . . . 650mW Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature (soldering, 10 sec). . . . . . . . . . . . . . +300C
CONNECTION DIAGRAMS
DIL-20,c SOIC-20, TSSOP-20 (TOP VIEW) J or N Package, DW Package, PW Package
EAN EAOUT RAMP REF GND SYNC CT RT 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 EAP SS/DISB OUTA OUTB PGND VDD OUTC OUTD CS ADS
Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of package.
TEMPERATURE & PACKAGE SELECTION TABLE
TEMPERATURE RANGE -55C to +125C -40C to +85C 0C to +70C PACKAGE SUFFIX J, L DW, N, PW, Q DW, N, PW, Q
DELAB DELCD
UCC1895 UCC2895 UCC3895
PLCC-20, CLCC-20 (TOP VIEW) Q Package, L Package
EAN EAOUT RAMP 3 REF GND SYNC CT RT DELAB DELCD 4 5 6 7 8 9 10 11 12 13 OUTD CS ADS 2 1 20 19 18 17 16 15 14 OUTA OUTB PGND VDD OUTC
ORDERING INFORMATION
UCC 895
EAP SS/DISB
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82k , CT=220pF, RDELAB=10k , RDELCD=10k , CREF=0.1 F, CVDD=1.0 F, no load at outputs. TA = TJ. TA = 0C to 70C for UCC3895x, -40C to +85C for UCC2895x, and -55C to +125C for UCC1895x.
PARAMETER UVLO Section Start Threshold Stop Threshold Hysteresis Supply Current Start-up Current IDD Active VDD Clamp Voltage IDD = 10mA 16.5 VDD = 8V 150 5 17.5 250 6 18.5 A mA V 10.2 8.2 1.0 11 9 2.0 11.8 9.8 3.0 V V V TEST CONDITIONS MIN TYP MAX UNITS
2
UCC1895 UCC2895 UCC3895 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82k , CT=220pF, RDELAB=10k , RDELCD=10k , CREF=0.1 F, CVDD=1.0 F, no load at outputs. TA = TJ. TA = 0C to 70C for UCC3895x, -40C to +85C for UCC2895x, and -55C to +125C for UCC1895x.
PARAMETER Voltage Reference Section Output Voltage TJ = 25C 10V < VDD < 17.5V, 0mA < IREF < 5mA, Temperature Short Circuit Current Error Amplifier Section Common Mode Input Voltage Range Offset Voltage Input Bias Current (EAP, EAN) EAOUT VOH EAOUT VOL EAOUT Source Current EAOUT Sink Current Open Loop DC Gain Unity Gain Bandwidth Slew Rate No Load Comparator Turn-Off Threshold No Load Comparator Turn-On Threshold No Load Comparator Hysteresis Oscillator Section Frequency Total Variation SYNC VIH SYNC VIL SYNC VOH SYNC VOL SYNC Output Pulse Width RT Voltage CT Peak Voltage CT Valley Voltage CT Valley Voltage PWM Comparator Section EAOUT to RAMP Input Offset Voltage Minimum Phase Shift (OUTA to OUTC, OUTB to OUTD) RAMP to OUTC/OUTD Delay RAMP Bias Current RAMP Sink Current Current Sense Section CS Bias Current Peak Current Threshold Overcurrent Threshold CS to Output Delay CS from 0 to 2.3V, DELAB = DELCD = REF 0 < CS , 2.5V, 0 < ADS < 2.5V -4.5 1.90 2.4 2.00 2.5 75 20 2.10 2.6 110 A V V ns RAMP = 0V, DELAB = DELCD = REF RAMP = 0V, EAOUT = 650mV (Note 1) RAMP from 0V to 2.5V, EAOUT = 1.2V, DELAB = DELCD = REF (Note 2) RAMP < 5V, CT < 2.2V RAMP = 5V, CT < 2.6V -5 12 19 0.72 0.00 0.85 0.85 70 1.05 1.40 120 5 V % ns A mA UCC2895, UCC3895 UCC1895 ISYNC = -400 A, CT = 2.6V ISYNC = 100 A, CT = 0V SYNC Load = 3.9k and 30pF in parallel 2.9 2.25 0.0 0.0 TJ = 25C Line, Temperature (Note 3) 2.05 1.85 4.1 0.0 473 500 2.5 2.10 1.90 4.5 0.5 85 3 2.35 0.2 0.2 527 5 2.25 1.95 5.0 1.0 135 3.1 2.50 0.4 0.6 kHz % V V V V ns V V V V (Note 3) EAN from 1V to 0V, EAP = 500mV, EAOUT from 0.5V to 3.0V, (Note 3) EAP-EAN = 500mV, IEAOUT= -0.5mA EAP-EAN = -500mV, IEAOUT= 0.5mA EAP-EAN = 500mV, EAOUT= 2.5V EAP-EAN = -500mV, EAOUT= 2.5V, (Note 4) -0.1 -7 -1 4.0 0 1.0 2.5 75 5.0 1.5 0.45 0.55 0.035 4.5 0.2 1.5 4.5 85 7.0 2.2 0.50 0.60 0.100 0.55 0.69 0.165 3.6 7 1 5.0 0.4 V mV A V V mA mA dB MHz V/ s V V V REF = 0V, TJ = 25C 4.94 4.85 10 5.00 5 20 5.06 5.15 V V mA TEST CONDITIONS MIN TYP MAX UNITS
3
UCC1895 UCC2895 UCC3895 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82k , CT=220pF, RDELAB=10k , RDELCD=10k , CREF=0.1 F, CVDD=1.0 F, no load at outputs. TA = TJ. TA = 0C to 70C for UCC3895x, -40C to +85C for UCC2895x, and -55C to +125C for UCC1895x.
PARAMETER Soft Start/Shutdown Section Soft Start Source Current Soft Start Sink Current Soft Start/Disable Comparator Threshold Delay Set Section DELAB/DELCD Output Voltage Output Delay ADS Bias Current Output Section VOH (all outputs) VOL (all outputs) Rise Time Fall Time IOUT = -10mA, VDD to Output IOUT = 10mA CLOAD = 100pF, (Note 3) CLOAD = 100pF, (Note 3) 250 150 20 20 400 250 35 35 mV mV ns ns ADS = CS = 0V ADS = 0V, CS = 2.0V ADS = CS = 0V (Notes 2 and 3) 0V < ADS < 2.5V, 0V < CS < 2.5V 0.45 1.9 450 -20 0.50 2.0 525 0.55 2.1 600 20 V V ns A SS/DISB = 3.0V, CS < 1.9V SS/DISB = 3.0V, CS > 2.6V -40 325 0.44 -35 350 0.50 -30 375 0.56 A A V TEST CONDITIONS MIN TYP MAX UNITS
Note 1: Minimum phase shift is defined as followed:
= 200 *
tf (OUTA ) - tf (OUTC ) tPERIOD tf (OUTB ) - tf (OUTD ) tPERIOD
tPERIOD
Or
= 200 *
where
tDELAY = tf(OUTA) - tf(OUTC)
OUTA
tf(OUTA) = falling edge of OUTA signal tf(OUTB) = falling edge of OUTB signal tf(OUTC) = falling edge of OUTC signal tf(OUTD) = falling edge of OUTD signal t(PERIOD) = period of OUTA or OUTB signal Same applies to OUTB and OUTD
OUTC
Note 2. Output delay is measured between OUTA/OUTB or OUTC/OUTD. Output delay is defined as shown below, where: tf(OUTA) = falling edge of OUTA signal tr(OUTB) = rising edge of OUTB signal Note 3: Ensured by design. Not 100% tested in production. Note 4: For UCC1895, MIN limit is 2.2 mA at -55C
OUTA tDELAY = tf(OUTA) - tr(OUTB) OUTB
Same applies to OUTC and OUTD
4
UCC1895 UCC2895 UCC3895 PIN DESCRIPTIONS
ADS: Adaptive Delay Set. This function sets the ratio between the maximum and minimum programmed output delay dead time. When the ADS pin is directly connected to the CS pin, no delay modulation occurs. The maximum delay modulation occurs when ADS is grounded. In this case, delay time is four times longer when CS = 0 than when CS = 2.0V (the Peak Current threshold), ADS changes the output voltage on the delay pins DELAB and DELCD by the following formula: DELAB, DELCD: Delay Programming Between Complementary Outputs. DELAB programs the dead time between switching of OUTA and OUTB, and DELCD programs the dead time between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the external bridge. The UCC3895 allows the user to select the delay, in which the resonant switching of the external power stages takes place. Separate delays are provided for the two half-bridges to accommodate differences in resonant capacitor charging currents. The delay in each stage is set according to the following formula:
VDEL = [0 .75 * (VCS - V ADS )] + 0 .5V
where VCS and VADS are in Volts. ADS must be limited to between 0V and 2.5V and must be less than or equal to CS. DELAB and DELCD also will be clamped to a minimum of 0.5V. EAOUT: Error Amplifier Output. It is also connected internally to the non-inverting input of the PWM comparator and the no-load comparator. EAOUT is internally clamped to the soft start voltage. The no-load comparator shuts down the output stages when EAOUT falls below 500mV, and allows the outputs to turn-on again when EAOUT rises above 600mV. CT: Oscillator Timing Capacitor. (Refer to Fig. 1, Oscillator Block Diagram) The UCC3895's oscillator charges CT via a programmed current. The waveform on CT is a sawtooth, with a peak voltage of 2.35V. The approximate oscillator period is calculated by the following formula:
t DELAY =
( 25 * 10 -12 ) * RDEL
VDEL
+ 25 ns
where VDEL is in Volts, and RDEL is in Ohms and tDELAY is in seconds. DELAB and DELCD can source about 1mA maximum. Choose the delay resistors so that this maximum is not exceeded. Programmable output delay can be defeated by tying DELAB and/or DELCD to REF. For an optimum performance keep stray capacitance on these pins at <10pF. EAP: The non-inverting input to the error amplifier. EAN: The inverting input to the error amplifier. GND: Chip ground for all circuits except the output stages. OUTA, OUTB, OUTC, OUTD: The 4 outputs are 100mA complementary MOS drivers, and are optimized to drive FET driver circuits. OUTA and OUTB are fully complementary, (assuming no programmed delay). They operate near 50% duty cycle and one-half the oscillating frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external power stage. OUTC and OUTD will drive the other half-bridge and will have the same characteristics as OUTA and OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB. Note that changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB requires other than the nominal 50% duty ratio on OUTC and OUTD during those transients. PGND: Output Stage Ground. To keep output switching noise from critical analog circuits, the UCC3895 has 2 different ground connections. PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically tied together closely near the IC. Also, since PGND carries high current, board traces must be low impedance.
t OSC =
5 * RT * CT + 120 ns 48
where CT is in Farads, and RT is in Ohms and tOSC is in seconds. CT can range from 100pF to 880pF. Please note that a large CT and a small RT combination will result in extended fall times on the CT waveform. The increased fall time will increase the SYNC pulse width, hence limiting the maximum phase shift between OUTA, OUTB and OUTC, OUTD outputs, which limits the maximum duty cycle of the converter. CS: Current Sense. This is the inverting input of the Current Sense comparator and the non-inverting input of the Over-current comparator, and the ADS amplifier. The current sense signal is used for cycle-by-cycle current limiting in peak current mode control, and for overcurrent protection in all cases with a secondary threshold for output shutdown. An output disable initiated by an overcurrent fault also results in a restart cycle, called "soft stop", with full soft start.
5
PIN DESCRIPTIONS (cont.)
RAMP: The Inverting Input of the PWM Comparator. This pin receives either the CT waveform in voltage and average current mode controls, or the current signal (plus slope compensation) in peak current mode control. An internal discharge transistor is provided on RAMP, which is triggered during the oscillator dead time. RT: Oscillator Timing Resistor. (Refer to Fig. 1, Oscillator Block Diagram) The oscillator in the UCC3895 operates by charging an external timing capacitor, CT, with a fixed current programmed by RT. RT current is calculated as follows:
UCC1895 UCC2895 UCC3895
Soft Start Mode: After a fault or disable condition has passed, VDD is above the start threshold, and/or SS/DISB falls below 0.5V during a soft stop, SS/DISB will switch to a soft start mode. The pin will now source current, equal to IRT. A user-selected capacitor on SS/DISB determines the soft start (and soft-start) time. In addition, a resistor in parallel with the capacitor may be used, limiting the maximum voltage on SS/DISB. Note that SS/DISB will actively clamp the EAOUT pin voltage to approximately the SS/DISB pin voltage during both soft start, soft stop, and disable conditions.
SYNC: Oscillator Synchronization. (Refer to Fig. 1, Oscillator Block Diagram) This pin is bidirectional. When used as an output, SYNC can be used as a clock, which is the same as the chip's internal clock. When used as an input, SYNC will override the chip's internal oscillator and act as it's clock signal. This bidirectional feature allows synchronization of multiple power supplies. The SYNC signal will also internally discharge the CT capacitor and any filter capacitors that are present on the RAMP pin. The internal SYNC circuitry is level sensitive, with an input low threshold of 1.9V, and an input high threshold of 2.1V. A resistor as small as 3.9k may be tied between SYNC and GND to reduce the sync pulse width. VDD: Power Supply. VDD must be bypassed with a minimum of a 1.0 F low ESR, low ESL capacitor to ground. REF: 5V, 1.2% voltage reference. The reference supplies power to internal circuitry, and can also supply up to 5mA to external loads. The reference is shut down during undervoltage lock-out but is operational during all other disable modes. For best performance, bypass with a 0.1 F low ESR, low ESL capacitor to ground.
IRT =
3.0 V RT
where RT is in Ohms and IRT is in Amperes. RT can range from 40k to 120k Soft start charging and discharging current are also programmed by IRT . SS/DISB: Soft Start/Disable. This pin combines the two independent functions.
Disable Mode: A rapid shutdown of the chip is accomplished by any one of the following: externally forcing SS/DISB below 0.5V, externally forcing REF below 4V, VDD dropping below the UNLO threshold, or an overcurrent fault is sensed (CS = 2.5V).
In the case of REF being pulled below 4V or an UVLO condition, SS/DISB is actively pulled to ground via an internal MOSFET switch. If an overcurrent is sensed, SS/DISB will sink a current of (10 * IRT) until SS/DISB falls below 0.5V. Note that if SS/DISB is externally forced below 0.5V the pin will start to source current equal to IRT. Also note that the only time the part switches into the low IDD current mode is when the part is in undervoltage lockout.
APPLICATION INFORMATION Programming DELAB, DELCD, and the Adaptive Delay Set
The UCC3895 allows the user to set the delay between switch commands within each leg of the full bridge power circuit according to the following formula from the data sheet:
UCC3895 CS 9 RDELAB 10 RDELCD DELCD ADS 11 DELAB 12
t DELAY
( 25 * 10 -12 ) * RDEL = + 25n sec VDEL
For this equation VDEL is determined in conjunction with the desire to utilize (or not utilize) the adaptive delay set feature from the following formula:
VDEL = [0.75 * (VCS - V ADS )] + 0.5V
The following diagram illustrates the resistors needed to program the delay periods and the adaptive delay set function. 6
Figure 1. Resistors needed in programming.
UCC1895 UCC2895 UCC3895 APPLICATION INFORMATION (CONT.)
The Adaptive Delay Set feature (ADS) allows the user to vary the delay times between switch commands within each of the converter's two legs. The delay time modulation is implemented by connecting ADS (pin 11) to CS, GND, or a resistive divider from CS to GND to set VADS. From the equation for VDEL above, if ADS is tied to GND then VDEL rises in direct proportion to VCS, causing a decrease in tDELAY as the load increases. In this condition the maximum value of VDEL is 2V. If ADS is connected to a resistive divider between CS and GND the term (VCS-VDS) becomes smaller, reducing the level of VDEL. This will decrease the amount of delay modulation. In the limit of ADS tied to CS, VDEL=0.5V and no delay modulation occurs. In the case with maximum delay modulation (ADS=GND), when the circuit goes from light load to heavy load the variation of VDEL is from 0.5V to 2V. This causes the delay times to vary by a 4:1 ratio as the load is changed. The ability to program an adaptive delay is a desirable feature because the optimum delay time is a function of the current flowing in the primary winding of the transformer, and can change by a factor of 10:1 or more as circuit loading changes. Reference [1] delves into the many interrelated factors for choosing the optimum delay times for the most efficient power conversion, and illustrates an external circuit to enable adaptive delay set using the UC3879. Implementing this adaptive feature is simplified in the UCC3895 controller, giving the user the ability to tailor the delay times to suit a particular application with a minimum of external parts.
A = VADS/VCS RDELAY = 10k
500 A=1.0
DELAY TIME (ns)
400 A=0.8 A=0.6 200 A=0.4 A=0.2 A=0.1 2.0 2.5
300
100
0
0.5
1.0
1.5
CURRENT SENSE VOLTAGE (V)
Figure 2. Resistors needed for programming.
[1] L. Balogh, "Design Review: 100W, 400kHz, DC/DC Converter With Current Doubler Synchronous Rectification Achieves 92% Efficiency," Unitrode Power Supply Design Seminar Manual, Unitrode Corporation, 1996, Topic 2.
CLOCK
RAMP & COMP
PWM SIGNAL
OUTPUT A
OUTPUT B
OUTPUT C
OUTPUT D
UDG-98138
Figure 3. UCC3895 timing diagram (no output delay shown). 7
UCC1895 UCC2895 UCC3895 APPLICATION INFORMATION (cont.)
IRT RT 8 8(IRT) CT 7 Q OSC Q R SYNC 6 PWM COMPARATOR RAMP 3 + 0.8 V EAOUT 2 ERROR AMP DSQ NO LOAD COMPARATOR + OUTC DELAY C 14 10 RQ DELAY D 13 DSQ 15 VDD
Q
D SQ
DELAY A
18 9
OUTA
DELAB
RQ
DELAY B
17
OUTB
EAP
20
DELCD OUTD
EAN
1 2V
CURRENT SENSE COMPARATOR
0.5 V / 0.6 V 16 PGND
CS
12 OVER CURRENT COMPARATOR 2.5 V 0.5V ADAPTIVE DELAY SET AMPLIFIER
11
ADS
Q
REF IRT SS HI=ON
S R DISABLE COMPARATOR
UVLO COMPARATOR + 11 V / 9 V REF REFERENCE OK COMPARATOR 4V 5 GND 4 REF
Q
0.5 V
19 HI=ON 10(IRT)
UDG-98140
Figure 4. Block diagram.
8
UCC1895 UCC2895 UCC3895 CIRCUIT DESCRIPTION
REF VREF
RT
8IRT
RT
IRT
CT 2.5 V + CT 0.2 V SYNC + R CLOCK S Q CLOCK
UDG-98141
Figure 5. Oscillator block diagram.
REF
0.5 V TO DELAY A AND DELAY B BLOCKS
100 k CS
75 k +
+
DELAB
100 k ADS 75 k REF
+
TO DELAY C AND DELAY D BLOCKS
DELCD
UDG-98142
Figure 6. Adaptive delay set block diagram.
9
UCC1895 UCC2895 UCC3895 CIRCUIT DESCRIPTION (cont.)
BUSSED CURRENT FROM ADS CIRCUIT VREF
3.5V DELAB/CD FROM PAD 2.5V DELAYED CLOCK SIGNAL
CLOCK
UDG-98143
Figure 7. Delay block diagram (one delay block per output).
TYPICAL CHARACTERISTIC
Vcs=0V 2000 1800
100 80
Vcs=2V
GAIN (dB)
PHASE MARGIN (C)
200 160 120 80 40 0
OUTPUT DELAY (ns)
1600 1400 1200 1000 800 600 400 200 0 0 10 20 RDEL (k) 30 40
60 40 20 0 1 100 10000 FREQUENCY (Hz) 1000000
Figure 8. Delay programming: characterizes the output delay between A/B, C/D.
Figure 10. Error amplifier gain/phase margin.
1
RT=47K 1600
RT=62k
RT=82k
RT=100k
EAOUT TO RAMP OFFSET (V)
FREQUENCY (kHz)
0.95
1400 1200 1000 800 600 400 200
0.9
0.85
0.8 -60 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
0 100
CT (pF)
1000
Figure 9. EAOUT to RAMP offset over temperature.
10
Figure 11. Frequency vs. RT/CT (oscillator frequency).
PHASE MARGIN (DEGREES)
GAIN (dB)
UCC1895 UCC2895 UCC3895 TYPICAL CHARACTERISTIC (cont.)
Vdd=10V Vdd=12V Vdd=15V Vdd=17V
Vdd=10V Vdd=12V Vdd=15V Vdd=17V
9 8
Idd (mA)
13 12 11
Idd (mA)
10 9 8 7 6 5 4
7 6 5 4 0 400 800 1200 1600 OSCILLATOR FREQUENCY (kHz)
0
400 800 1200 OSCILLATOR FREQUENCY (kHz)
1600
Figure 12. Idd vs. Vdd / oscillator frequency (no output loading).
Figure 13. Idd vs. Vdd / oscillator frequency (with 0.1nf output loads).
11
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