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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
D Single-Chip RF Transceiver for 868-MHz D D D D D D
and 915-MHz Industrial, Scientific, and Medical (ISM) Bands 1.8-V to 3.6-V Operation 860-MHz to 930-MHz Operation Low Power Consumption FSK/OOK Operation Integer-N Synthesizer With Fully Integrated Voltage Controlled Oscillator (VCO) On-Chip Reference Oscillator and Phase-Locked Loop (PLL)
D 8-dBm Typical Output Power D Programmable Brownout Detector D Linear Receive Strength Signal Indicator D D D D
(RSSI) Flexible 3-Wire Serial Interface Minimal Number of External Components Required 48-Pin Low-Profile Plastic Quad Flat Package (PQFP) Programmable XTAL Trimming
48 47 46 45 44 43 42 41 40 39 38 37
GND RSSI_OUT DEM_VCC LEARN/HOLD DEM_GND LPF_IN
PQFP PACKAGE (TOP VIEW)
MIX_VCC MIX_OUT MIX_GND DET_OUT IF_IN1 IF_IN2
LNA_IN1 LNA_IN2 LNA_VCC PA_OUT PA_GND1 PA_VCC PA_GND2 VCO_GND1 VCO_VCC VCO_VCC2 VCO VCO_GND2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
LPF_OUT CER_DIS SLC_CAP RX_DATA TX_DATA XTAL_SW XTAL XTAL_VCC DGND CLK_OUT STDBY DC_DC_IN
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
VCO_TUNE CP_GND CP_OUT CP_VCC DVDD CLOCK STROBE DATA MODE DC_DC_OUT C2 C1
Copyright 2004, Texas Instruments Incorporated
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
description
The TRF6901 single-chip solution is an integrated circuit intended for use as a low cost FSK or OOK transceiver to establish a frequency-programmable, half-duplex, bidirectional RF link. The multichannel transceiver is intended for digital (FSK, OOK) modulated applications in the new 868-MHz European band and the North American 915-MHz ISM band. The single-chip transceiver operates down to 1.8 V and is designed for low power consumption. The synthesizer has a typical channel spacing of better than 200 kHz and uses a fully-integrated VCO. Only the PLL loop filter is external to the device. Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings (for example, receive (RX)/transmit (TX); TX_frequency_0/TX_frequency_1; RX_frequency_0/RX_frequency_1; ...) without reprogramming the device. ISM band standards Europe has assigned an unlicensed frequency band of 868 MHz to 870 MHz. This band is specifically defined for short range devices with duty cycles from 0.1% to 100% in several subbands. The existing 433-MHz band for short-range devices in Europe has the great disadvantage of high usage. The new European frequency band, due to the duty cycle assignment, allows a reliable RF link and makes many new applications possible. The North American unlicensed ISM band covers 902 MHz to 928 MHz (center frequency of 915 MHz) and is suitable for short range RF links. transmitter The transmitter consists of an integrated VCO and tank circuit, a complete integer-N synthesizer, and a power amplifier. The divider, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete PLL with a typical frequency resolution of better than 200 kHz. Since the typical RF output power is approximately 9 dBm, no additional external RF power amplifier is necessary in most applications. receiver The integrated receiver is intended to be used as a single-conversion FSK/OOK receiver. It consists of a low noise amplifier, mixer, limiter, FM/FSK demodulator with an external LC tank circuit or ceramic resonator, a LPF amplifier, and a data slicer. The received strength signal indicator (RSSI) can be used for fast carrier sense detection or as an on/off keying, or amplitude shift keying, (OOK/ASK) demodulator. baseband interface The TRF6901 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430 ultralow-power microcontroller (see Figure 1). The TRF6901 serial control registers are programmed by the MSP430 and the MSP430 performs baseband operations in the software.
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
Antenna
RF Section RSSI_OUT TX_DATA RF In LNA_IN1, 2 PA_OUT TRF6901 Transceiver + Discretes RX_DATA LEARN/HOLD MODE STDBY DET_OUT DATA CLOCK STROBE CLK_OUT RSSI Out (Analog Signal) Transmit Data Receive Data Learn/Hold Select Mode Select Standby Brownout Detector Out Serial Control Data Serial Control Clock Serial Control Strobe Clock Buffer Out
Microcontroller Section
MSP430 Family C
RF Out
Programmable Digital I/O Pins
Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
functional block diagram
10.7-MHz Ceramic IF Filter MIX_OUT
Ceramic Discriminator
LEARN/HOLD 39
LPF_OUT
47 Mixer LNA
44, 43 Limiter
35
37
36 LPF Amplifier
LNA_IN1, LNA_IN2 RFIN 1, 2 860 MHz to 930 MHz
SLC_CAP 34
IF_IN1,2
CER_DIS
LPF_IN
33 Quadrature Demodulator Data Slicer 41
RX_DATA
RSSI Band-gap
RSSI_OUT
/ACounter /N 32/33
/Div. CTRL
8 6 Serial Interface
DET_OUT
45
Brownout Detector
/BCounter 8 /L 2..254 5 8 /K 2..62
18 20 19 26 21
CLOCK DATA STROBE STDBY MODE
DC_DC_IN DC_DC_OUT
25 22 DC-DC Converter
27
CLK_OUT
PA_OUT
4
PA VCO
860 MHz to 930 MHz typical 9 dBm
PFD CPs
/Ref 2..255 XTAL XTAL_SW 30 31
32
TX_DATA
VCO_TUNE 13
15 CP_OUT
Loop Filter
Terminal Functions
TERMINAL NAME C1 C2 CER_DIS CLK_OUT CLOCK CP_GND CP_OUT CP_VCC DATA NO. 24 23 35 27 18 14 15 16 20 O I I O I I/O DESCRIPTION Connect to external capacitor for operation of dc-dc converter Connect to external capacitor for operation of dc-dc converter Connect to external ceramic discriminator Clock signal output for connection to external microcontroller Serial interface clock signal input Charge pump ground Charge pump output Charge pump input VCC from dc-dc converter Serial interface data signal input
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TRF6901 SINGLE CHIP RF TRANSCEIVER
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Terminal Functions (continued)
TERMINAL NAME DC_DC_IN DC_DC_OUT DEM_GND DEM_VCC DET_OUT DGND DVDD GND IF_IN1 IF_IN2 LEARN/HOLD LNA_IN1 LNA_IN2 LNA_VCC LPF_IN LPF_OUT MIX_GND MIX_OUT MIX_VCC MODE PA_GND1 PA_GND2 PA_OUT PA_VCC RSSI_OUT RX_DATA SLC_CAP STDBY STROBE TX_DATA VCO VCO_GND1 VCO_GND2 VCO_TUNE VCO_VCC VCO_VCC2 XTAL XTAL_SW XTAL_VCC NO. 25 22 38 40 45 28 17 42 44 43 39 1 2 3 37 36 46 47 48 21 5 7 4 6 41 33 34 26 19 32 11 8 12 13 9 10 30 31 29 I/O I I I I I I O O O I O I O I I I I I O I/O I O Input to dc-dc converter Output from dc-dc converter Demodulator ground Demodulator supply voltage Brownout detector output; active high Digital ground Digital power supply Substrate ground Limiter amplifier noninverting input Limiter amplifier inverting input Data slicer switch. Controls data slicer reference level LNA noninverting input LNA inverting input LNA power supply Low-pass filter amplifier input Low-pass filter amplifier output Mixer ground Mixer output Mixer supply voltage Mode select input Power amplifier ground Power amplifier ground Power amplifier output Power amplifier supply voltage RSSI output signal Demodulated digital RX data External capacitor for data slicer Standby input signal; active low Serial interface strobe signal Buffered TX data input VCO tank circuit connection VCO ground VCO ground Tuning voltage for the integrated VCO VCO supply voltage VCO core supply voltage Connection to an external crystal Connector to external capacitor which sets the frequency deviation of the transmitted signal Oscillator supply voltage DESCRIPTION
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6 to 4.5 Vdc Input voltage, logic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6 to 4.5 Vdc Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C ESD protection, human body model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
PARAMETER Analog supply voltage Digital supply voltage Operating free-air temperature TEST CONDITIONS MIN 1.8 1.8 -40 TYP MAX 3.6 3.6 85 UNIT V V C
dc electrical characteristics over full range of operating conditions, VCC = 2.7 V, TA = 25C
supply current
PARAMETER Standby current RX current 0-dB attenuation TX current 10-dB attenuation 20-dB attenuation TEST CONDITIONS MIN TYP 0.6 18 32 27 26 MAX 4 21 40 mA UNIT A mA
The TX current consumption is dependent upon the external PA matching circuit. The matching network is normally designed to achieve the highest output power at the 0-dB attenuation setting. Changing the external matching components to optimize the output power for other attenuation settings alters the typical current consumption from the typicals noted.
digital interface
PARAMETER VIH VIL VOH VOL High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Digital input leakage current IOH = 0.5 mA IOL = 0.5 mA TEST CONDITIONS MIN VDD-0.4 0 VDD-0.4 0.4 <0.01 TYP MAX VDD 0.4 UNIT V V V V A
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TRF6901 SINGLE CHIP RF TRANSCEIVER
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ac electrical characteristics over full range of operating conditions, VCC = 2.7 V, TA = 25C receiver (LNA, mixer, limiter, demod, LPF amplifier, data slicer, VCO, and PLL)
PARAMETER RX wake-up time 860 MHz to 930 MHz, IF = 10.7 MHz, BW = 280 kHz FSK deviation: 32 kHz Bit rate: 19.2 kbit/s -103 < PRFIN (dBm) < - 30 TEST CONDITIONS MIN TYP MAX 1 UNIT ms
BER
10-3
LNA/mixer
PARAMETER Conversion gain SSB noise figure Input 1-dB compression point Input IP3 Includes external matching network TEST CONDITIONS MIN TYP 18 6.5 -31 -19 MAX UNIT dB dB dBm dBm
IF/limiter amplifier
PARAMETER Frequency Voltage gain Noise figure IF frequency = 10.7 MHz TEST CONDITIONS MIN TYP 10.7 86 4 MAX UNIT MHz dB dB
VCO
PARAMETER Frequency range--Europe Frequency range--US Closed loop phase noise Tuning voltage TEST CONDITIONS High-side injection Low-side injection Frequency offset = 50 kHz Frequency offset = 200 kHz 0.1 MIN 860 890 -77 -90 VCC at terminal 10 dBc/Hz V TYP MAX 890 930 UNIT MHz MHz
RSSI
PARAMETER Dynamic range Rise time Slope RSSI output current RL = 100 k, CL = 10 pF RL = 100 k, CL = 10 pF TEST CONDITIONS MIN TYP 70 2 20 30 3 MAX UNIT dB s mV/dB A
impedances and loads
PARAMETER LNA_IN MIX_OUT{ IF_IN{ PA_OUT Does not include external matching network. TEST CONDITIONS MIN TYP See Figure 3 1400 Differential 2600 See Figure 9 MAX UNIT
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
ac electrical characteristics over full range of operating conditions, VCC = 2.7 V, TA = 25C (continued) transmitter (XTAL, PLL, VCO, and PA)
PARAMETER TX frequency range 0-dB attenuation Output power 10-dB attenuation 20-dB attenuation Off 0-dB attenuation Output power (VCC = 1.8 V) Second harmonic Third harmonic Frequency deviation Power ON-OFF ratio FSK OOK, 0-dB mode 10-dB attenuation 20-dB attenuation TEST CONDITIONS MIN 860 8 0 -10 -50 6 -3 -9 -15 -20 32 50 64 dBc dBc kHz dB kbit/s dBm dBm TYP MAX 930 UNIT MHz
Data rate FSK Matched to 50 using an external matching network. Not selectable with PA attenuation bits A< 7 : 6 >. Measured while the TRF6901 device is in RX mode. Dependant upon external circuitry.
XTAL
PARAMETER Frequency range TEST CONDITIONS MIN 10 TYP MAX 20 UNIT MHz
brownout detector
PARAMETER Voltage threshold, Vdet Voltage steps (V) Number of steps Output level Connected to typical input port of microcontroller TEST CONDITIONS Set by B<2:1> MIN 1.8 200 4 CMOS TYP MAX 2.4 UNIT V mV
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TRF6901 SINGLE CHIP RF TRANSCEIVER
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timing data for serial interface
PARAMETER f(CLOCK) tw(CLKHI) tw(CLKLO) tsu(D) th(D) td(CLKLO) tw(STROBEHI) tw(STROBELO) Data Valid DATA MSB t su(D) t h(D) CLOCK t w(CLKLO) STROBE tf tr Clock Disabled Clock Enabled NOTE: Most significant bit (MSB) clocked in first to the synthesizer. Shift in Data Store Data Strobe Enabled t w(STROBEHI) t w(CLKHI) Clock frequency Clock high-time pulse width, clock high Clock low-time pulse width, clock low Setup time, data valid before CLOCK Hold time, data valid after CLOCK Delay time of CLOCK low before STROBE high STROBE high-time pulse width, STROBE high STROBE low-time pulse width, STROBE low Data Change LSB Start of Next Word MSB -V H -V L 25 25 25 25 25 25 25 MIN MAX 20 UNIT MHz ns ns ns ns ns ns ns
t d(CLKLO)
-V H -V L tw(STROBELO) -V H -V L
Figure 2. Timing Data for Serial Interface
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TRF6901 SINGLE CHIP RF TRANSCEIVER
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detailed description
low-noise amplifier (LNA)/RF mixer The LNA has differential inputs. The off-chip input matching network has the dual task of matching a 50- connector (or antenna, switch, filter, etc.) to the differential inputs and providing a 180-degree phase shift between the inputs at terminals 1 and 2. The differential input impedance of the LNA is approximately 500 in parallel with 0.7 pF. The predicted noise figure of the LNA and input matching circuit is 2.5 dB. The cascaded noise figure for the LNA/mixer is listed in the specifications. The mixer offers good linearity (high IP3). An external matching network is required to transform the output impedance of the mixer (1.4 k) to the input impedance of the IF filter (typically 330 ).
CH1 S11 1 0.5 2 1 U
5
CAL OFS
0
0.2
0.5
1
2
5
10
CPL -5
FIL 1k -0.5 -1 START 850 MHz STOP 1000 MHz -2
Figure 3. Typical LNA Input Impedance (S11) at Device Terminals LNA_IN1,2 IF amplifier/limiter The IF amplifier has differential inputs to its first stage. The limiting amplifier provides 68 dB of gain. An external impedance matching network is required between the IF filter output and the IF amplifier inputs at terminals 43 and 44. RSSI The received signal strength indicator (RSSI) voltage at terminal 41 is proportional to the log of the down-converted RF signal at the IF limiting amplifier input. The RSSI circuit is temperature compensated and is useful for detecting interfering signals, transceiver handshaking, and RF channel selection. In some applications it can be used as a demodulator for amplitude-shift\keying (ASK) or on-off keying (OOK) modulation.
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detailed description (continued)
demodulator The quadrature demodulator decodes digital frequency shift keying (FSK) modulation. An external ceramic discriminator or an equivalent discrete circuit is required at terminal 35. The demodulator is optimized for use with a ceramic discriminator. Thus, the use of a packaged ceramic discriminator is recommended for the best performance. Internal resistors can be programmed with D<14:12> to tune the demodulator center frequency. The recommended default setting for the demodulator tuning bits is D<14:12> = 110. The resonant frequency of the discrete-component discriminator can be calculated from the inductor and capacitor values used in the circuit. A parallel resistor may be added to reduce the quality factor (Q) of the tank circuit, depending on the application. res + 1 2p LC
External Tank 35
L
R
C
Figure 4. Optional External Discrete Demodulator Tank post-detection amplifier/low-pass filter The post-detection amplifier operates as a low-pass transimpedance amplifier. The external low-pass filter circuit must be optimized for the data rate. The 3-dB corner frequency of the low-pass filter should be greater than twice the data rate. Various low-pass filter designs use two to five components and may be first- or second-order designs. Simple 2-element filter component values and 3-dB bandwidths are contained in Table 1.
R2 External Low-Pass Filter 36
C2 37
C1 R1
Internal Low-Pass Amplifier
Figure 5. Post-Detection Amplifier/Low-Pass Filter Table 1. Various Post-Detection Amplifier/Low-Pass Filter 3-dB Bandwidth and Corresponding Component Values
f3dB (kHz) R2 (k) C2 (pF) 10 220 68 20 220 33 30 220 22 60 220 10
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TRF6901 SINGLE CHIP RF TRANSCEIVER
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detailed description (continued)
data slicer The data slicer is a comparator circuit for received digital (FSK) data. The data slicer output voltage depends on the difference between the received signal and a reference voltage (at the sample-and-hold (S&H) capacitor) used as a decision threshold. During the learn mode, the S&H capacitor connected to terminal 34 is charged up to the average dc voltage of a training sequence of alternating ones and zeroes; this establishes the reference voltage to be used as a decision level before a sequence of actual data is received in the hold mode. During long data transmissions, more training sequences may be necessary to recharge the S&H capacitor. If the modulation scheme is dc-free (Manchester coding) or constant-dc, the TRF6901 may be operated continuously in the learn mode, and no training sequence is necessary before the transmission of a data string. However, the S&H capacitor voltage may be incorrect during power up or after long periods of inactivity (no data transmission); a learning sequence before each data transmission is recommended. The comparator is a CMOS circuit that does not load the S&H capacitor, so leaving the transmission gate (learn/hold switch) open during periods of inactivity may be useful in maintaining the capacitor reference voltage; however, it gradually discharges due to leakage current. The time constant for charging the S&H capacitor is determined by its capacitance and an internal 50-k resistor. A slow data rate requires a larger S&H capacitor (longer time constant). The value of the S&H capacitor, Csh, can be calculated with the following equation: T Csh ^ 5 50000 where T is the bit period.
Low-Pass Amplifier LPF Out 33 50 k Comparator 34 Csh{ Learn/Hold {External Sample-and-Hold Capacitor
39
Figure 6. Data Slicer main divider The main divider is composed of a 5-bit A-counter, a 9-bit B-counter, and a prescaler. The A-counter controls the divider ratio of the prescaler, which divides the VCO signal by either 33 or 32. The prescaler divides by 33 until the A-counter reaches its terminal count and then divides by 32 until the B-counter reaches terminal count, whereupon both counters reset and the cycle repeats. The total divide-by-N operation is related to the 32/33 prescaler by: NTOTAL = 33 x A + 32 x (B - A) where 0 A 31 and 31 B 511 or, NTOTAL = A + 32B Thus, the N-divider has a range of 992 NTOTAL 16383.
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detailed description (continued)
PLL The phase-locked loop is the radio frequency synthesizer for the TRF6901. It is used to generate the transmit signal and as the local oscillator for the receive mixer. The signal (FX) from a reference crystal oscillator (XO) is divided by an integer factor R down to FR. The minimum frequency resolution, and thus, the minimum channel spacing, is FR. FR = FX / R, where 1 R 256 The phase-locked loop is an integer-N design. The voltage-controlled oscillator (VCO) signal is divided by an integer factor N to get a frequency at the phase detector input. FPD = FVCO / N, where FVCO = FOUT The phase detector compares the divided VCO signal to the divided crystal frequency and implements an error signal from two charge pumps. The error signal corrects the VCO output to the desired frequency. FN With FR = FPD under locked conditions, FOUT = X = (A + 32B) FR. R As is in any integer-N PLLs, the VCO output has spurs at integer multiples of the reference frequency (nFR). In applications requiring contiguous frequency channels, the reference frequency is often chosen to be equal to the channel spacing, thus, channel spacing = FR = FX / R. oscillator circuit and reference divider The reference divider reduces the frequency of the external crystal (FX) by an 8-bit programmable integer divisor to an internal reference frequency (FR) used for the phase-locked loop. The choice of internal reference frequency also has implications for lock time, maximum data rate, noise floor, and loop-filter design. The crystal frequency can be tuned using the D word to control internal trimming capacitors, which are placed in parallel with the crystal. These offset a small frequency error in the crystal. In an FSK application, an additional capacitor is placed in parallel (through terminal 31) with the external capacitor that is connected in series with the crystal, thus, changing the load capacitance as the transmit data switch (TX_DATA, terminal 32) is toggled. The change in load capacitance pulls the crystal off-frequency by the total frequency deviation. Hence, the 2-FSK frequency set by the level of TX_DATA and the external capacitor, can be represented as follows: out1 + TX_DATA Low out2 + TX_DATA High
Note that the frequencies out1 and out2 are centered about the frequency center = (out1 + out2)/2. When transmitting FSK, center is considered to be the effective carrier frequency and any receiver local oscillator (LO) should be set to the same center frequency the receiver's IF frequency (IF) for proper reception and demodulation. For the case of high-side injection, the receiver LO would be set to LO = center + IF. Using high-side injection, the received data at terminal 33, RX_DATA, would be inverted from the transmitted data applied at terminal 32, TX_DATA. Conversely, for low-side injection, the receiver LO would be set to LO = center - IF. Using low-side injection, the received data would be the same as the transmitted data. In addition, when the TRF6901 is placed in receive mode, it is recommended that the TX_DATA terminal be kept low. In this manner, the actual LO frequency injected into the mixer is out1 = LO. If TX_DATA is set high, the the receiver LO would be offset, resulting in poor receiver sensitivity.
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TRF6901 SINGLE CHIP RF TRANSCEIVER
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detailed description (continued)
/K Clock Divider 27 Clock Buffer VCC 30 Crystal Oscillator Circuit /R Reference Divider FR FPD External Crystal
CLK_OUT
31 External Cap for FSK FX
PhaseFrequency Detector
15
External Loop Filter
13 VCO
FOUT
Charge Pumps
/N Main Divider A, B Counters 32/33
FVCO
Figure 7. TRF6901 PLL and Clock Divider phase detector and charge pumps The phase detector is a phase-frequency design. The phase-frequency detector gain is given by: KP = I(CP)/2 where, I(CP) is the peak charge pump current. The peak charge pump current is programmable with A<3:2> in three steps: 250 A, 500 A, and 1000 A. loop filter The loop filter must be carefully chosen for proper operation of the TRF6901. The loop filter is typically a secondor third-order passive design and in FSK operation should have a bandwidth wide enough to allow the PLL to relock quickly as the external crystal frequency is pulled off-center during modulation. The loop filter should also be wider than the data modulation rate. These requirements should be balanced with making the loop narrow enough in consideration of the reference frequency. In OOK the VCO frequency is not changed during data modulation, so the filter bandwidth may be narrower than the modulation bandwidth. Filters can be calculated using standard formulas in reference literature. Some third-order filter examples are shown in Table 2. 1 ) sC2R2 F(s) + s(C1 ) C2 ) sC1C2R2)
lcp CP_OUT 15 C1 C2 R2 VCO_VCC External-Loop Filter
1 C3R3 s) 1 C3R3
R3 Vtune 13 C3 VCO_TUNE
Figure 8. Third-Order Loop Filter and Transfer Function
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loop filter (continued) Table 2. Various Loop Filter Nat Freq Component Pole Values and Corresponding Bandwidths
3 dB BW (kHz) 10.4 20 10.4 20 20 30 20 30 40 REF Freq (kHz) 100 100 200 200 200 200 400 400 400 Icp (mA) 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 3rd Pole (kHz) 100 100 100 100 200 100 200 200 200 C1 (pF) 1590 440 3200 880 880 390 1740 780 430 R2 (k) 7 13.2 3.5 6.6 6.6 9.9 3.3 5 6.8 C2 (nF) 15.9 4.4 31.8 8.8 8.8 3.9 17.4 7.8 4.2 R3 (k) 10 36 5 18 9 40 4.6 10 18.7 C3 (pF) 159 44 320 88 88 39 170 78 42
VCO The voltage-controlled oscillator (VCO) produces an RF output signal with a frequency that is dependant upon the dc-tuning voltage at terminal 13. The tank circuit is passive and has integrated varactor diodes and inductors. The VCO has an open-loop operating band from approximately 700 MHz to 1 GHz. The open-loop VCO gain is approximately 100 MHz/V. power amplifier The power amplifier has four programmable output states: full power, 10-dB attenuation, 20-dB attenuation, and off (receive mode). The output s-parameters of the amplifier may change slightly as the bias point is changed. During receive, the transmit power amplifier is powered down but the VCO is still operating. During ASK or OOK operation, the TX_DATA signal turns the power amplifier on and off according to the transmit data incident at terminal 32.
CH1 S22 1 0.5 2 1 U
5
CAL OFS
0
0.2
0.5
1
2
5
10
CPL -5
FIL 1k -0.5 -1 START 850 MHz STOP 1000 MHz -2
Figure 9. Typical PA Output Impedance (S22) at Device Terminal PA_OUT
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
detailed description (continued)
dc-dc converter The dc-dc converter provides an adequate voltage to the charge pumps and VCO core in the event the power supply voltage drops down to 1.8 V. The switching frequency is adjustable through a clock divider that reduces the external clock frequency by a C-word programmable factor (L) of 2 to 254 in steps of 2. The dc-dc converter is designed to operate at a switching frequency of around 1 MHz, so a suggested divider ratio to use with a 20-MHz crystal frequency is 16 or 32 (C<6:0>). The power supply to terminals 10 and 16 may be from Vcc (regulated supply or battery) or from the dc converter output at terminal 22, but not both. Operation at a reduced supply voltage is possible without the dc-dc converter if there is adequate VCO tuning voltage overhead at the highest and lowest frequencies of operation. The dc-dc converter makes operation at low supply voltages (around 1.8 V) possible, where there would otherwise be insufficient overhead to operate the VCO core and charge pumps. brownout detector The brownout detector provides an output voltage to indicate a low supply voltage. This may be used to signal the need to change transmit power to conserve battery life, or for system power down. The brownout detector threshold is set with the B word. Four different thresholds are available. During operation, the brownout detector is always enabled. During stand-by, the brownout detector is disabled. clock-output buffer The clock-output buffer is provided to use the TRF6901 crystal oscillator to drive an external microcontroller (MCU) or other baseband device, eliminating the need for a second clock circuit. A divider reduces the external crystal frequency by a C-word programmable integer factor (K) of 2 to 62 in steps of 2. It is recommended that the clock output buffer divider (C<12:8>) be a power of two, i.e., 2, 4, 8, 16, etc. A buffer amplifier provides adequate drive for an external MCU, FPGA, or DSP. When the transmit section of the TRF6901 is operated in FSK, the crystal frequency, internal reference frequency, and the output buffer frequency are modulated by the total frequency deviation as the transmit data switch is toggled. The resulting MCU clock jitter should be acceptable for baseband applications. It is possible to run the TRF6901 from an external clock oscillator circuit by an overdriving signal at terminal 30; however, in FSK the external clock circuit must be modulated. When the TRF6901 is in standby, the clock buffer output at terminal 27 is turned off. serial control interface The TRF6901 is controlled through a serial interface; there are four 24-bit control words (A, B, C, D) which set the device state. The A and B words are almost identical and provide configuration settings for two modes, designated 0 and 1, which are commonly used to configure the transmit and receive states. The transmit and receive states can then be rapidly selected using MODE (terminal 21). The C word sets the various clock dividers. The D word is used to trim the external crystal frequency and tune the demodulator.
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
PRINCIPLES OF OPERATION register description
23 Word A B C D 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 TX/ RX TX/ RX 4 3 2 1 0 Address 0 0 1 1 0 1 0 1 0 0 Main A Divider Coefficient (Mode 0) Main A Divider Coefficient (Mode 1) Reference Divider Coefficient 0 XTAL_Tune PFD reset Main B Divider Coefficient (Mode 0) Main B Divider Coefficient (Mode 1) 0 Dem_Tune Buffer Clock Divider Coefficient 0 0 0 0 0 0 0 0 PA PA 0 FSK/ OOK CP Acc. Buf 0 dc dc 0
Detector Threshold
dc dc Clock Divider Coefficient 0 0 0 0 0
ADDRESS 00 00 00 00 00 00 00 01 01 01 01 01 01 01 10 10 10 11 11 11 21 : 17 16 : 8 7:6 5 3:2 1 0 21 : 17 16 : 8 7:6 5 4 3 2:1 21 : 14 12 : 8 6:0 18 : 16 15 14 : 12
BITS 5 9 2 1 2 1 1 5 9 2 1 1 1 2 8 5 7 3 1 3
DESCRIPTION Main A-divider coefficient (Mode 0) Main B-divider coefficient (Mode 0) Controls the PA attenuation (Mode 0) Enables transmit/receive path (Mode 0) Controls the charge pump peak current Set to 0 Enables the dc-dc converter Main A-divider coefficient (Mode 1) Main B-divider coefficient (Mode 1) Controls the PA attenuation (Mode 1) Enables transmit/receive path (Mode 1) Controls modulation scheme (FSK or OOK) Enables the XTAL output buffer Sets threshold for the brownout detector Reference divider coefficient Buffer clock divider coefficient (K-divider) DC-DC converter clock divider coefficient (L-divider) Tunes the XTAL frequency by using an internal capacitor bank PFD reset Tunes the resonant frequency of the external demodulation tank circuit
At power on/startup, all of the TRF6901 register contents are zero, with the exception of the power amplifier attenuation registers and the phase-frequency detector reset register. The power amplifier attenuation registers are set to zero attenuation, i.e., A<7:6>=10 and B<7:6>=10. The PFD reset register is set to the prescaler setting, i.e., D<15>=1.
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
PRINCIPLES OF OPERATION Address 00 (A-Word)
Terminal 21 (MODE) selects bits A< 21 : 5 > if low, or B< 21 : 5 > if high. Main divider A< 21 : 17 >: 5-bit value for divider ratio of the A-counter Main divider A< 16 : 8 >: 9-bit value for divider ratio of the B-counter PA attenuation A< 7 : 6 >: 2 bits for setting the PA attenuation
A< 7 : 6 > 00 01 10 11 PA ATTENUATION 10 dB 20 dB 0 dB Not defined
A<5 >: 1 bit TX/RX mode select
A< 5 > 0 1 TX/RX MODE RX mode TX mode
A<3: 2 >: 2 bits for setting the charge pump current
A<3 : 2 > 00 01 10 11 CP CURRENT 0.5 mA 1 mA 0.25 mA Not defined
A<1>: Set to 0 A<0 >: Enables or disables the dc-dc converter
A< 0 > 0 1 DC-DC CONVERTER Off On
NOTE: When A<0> is high, at least one bit in C<6:0> must be high to enable the VCO.
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
PRINCIPLES OF OPERATION Address 01 (B-Word)
Terminal 21 (MODE) selects bits A< 21 : 5 > if low, or B< 21 : 5 > if high. Main divider B< 21 : 17 >: 5-bit value for divider ratio of the A-counter Main divider B< 16 : 8 >: 9-bit value for divider ratio of the B-counter PA attenuation B< 7 : 6 >: 2 bits for setting the PA attenuation
B< 7 : 6 > 00 01 10 11 PA ATTENUATION 10 dB 20 dB 0 dB Not defined
B<5 >: 1 bit TX/RX mode select
B< 5 > 0 1 TX/RX MODE RX mode TX mode
B<4 > 1 bit modulation select
B< 4 > 0 1 MODULATION OOK FSK
B<3 >: 1 bit to enable terminal 27 (reference clock buffer)
B< 3 > 0 1 REFERENCE CLOCK BUFFER Off On
NOTE: If C<12:8> are all low, the reference clock buffer is disabled independent of B<3>.
B<2 : 1 >: 2-bit value to set the threshold voltage for the brownout detector
B< 2 : 1 > 00 01 10 11 VOLTAGE 1.8 V 2V 2.2 V 2.4 V
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
PRINCIPLES OF OPERATION Address 10 (C-Word)
Reference divider C < 21 : 14 >: 8-bit value for divider ratio of reference divider. The allowable reference divider range is 2 (C <21:14> = 00000010) through 255 (C <21:14> = 11111111). Buffer clock divider C < 12 : 8 >: 5-bit value for divider (K-divider) for the buffer clock for an external microcontroller.
C<12 :8> 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 BUFFER CLOCK DIVIDE FACTOR Clock output buffer off 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
NOTE: C<12> is the MSB and C<8> is the LSB. The microcontroller clock divider is followed internally by a divide-by-2 stage to achieve a 50% duty cycle. This additional division is not included in the 5-bit setting. The maximum valid divider factor is 62. The minimum valid divider factor is 2. The clock buffer output frequency must be set to an integer multiple of the reference frequency by the buffer clock divide factor.
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
Address 10 (C-Word) (continued)
dc-dc clock divider C < 6 : 0 >: 7-bit value for divider (L-divider) for setting the dc-dc converter clock divider
C<6 :0> 0000000 DC-DC CLOCK DIVIDE FACTOR When A<0> is high and C<6:0> are all low, the VCO shuts off. At least one bit in C<6:0> must be set high to enable the VCO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
Address 10 (C-Word) (continued)
C<6 :0> 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 DC-DC CLOCK DIVIDE FACTOR 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
C<6 :0> 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111
DC-DC CLOCK DIVIDE FACTOR 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254
NOTE: C<6> is the MSB and C<0> is the LSB. The dc-dc clock divider is followed internally by a divide-by-2 stage to achieve a 50% duty cycle. This additional division is not included in the 7-bit setting. The maximum valid divider factor is 254. The minimum valid divider factor is 2.
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
PRINCIPLES OF OPERATION
The dc-dc clock divide factor should be chosen such that the resultant dc-dc converter switching frequency is between 150 kHz and 1000 kHz.
Address 11 (D-Word)
D<18 : 16 >: 3-bit value to fine-tune the XTAL frequency by using an internal capacitor bank
D< 18:16 > 000 001 010 011 100 101 110 111 TYPICAL LOAD CAPACITANCE 13.23 pF 22.57 pF 17.9 pF 27.24 pF 15.56 pF 24.9 pF 20.23 pF 29.57 pF
D<15 >: 1-bit value to select the reset signal for the PFD
D<15 > 0 1 RESET SIGNAL Derived from XTAL Derived from prescaler
NOTE: The default setting for D<15> is 1.
D<14 : 12 >: 3-bit value to tune the resonant frequency of the external demodulator tank circuit. It can be used to optimize the receiver performance. The recommended default setting is 110.
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
PRINCIPLES OF OPERATION operating modes
Controlled with terminal 26, STDBY
STDBY 0 1 OPERATING MODE Power down of all blocks--programming mode Operational mode and programming mode
Controlled with terminal 21, MODE
MODE 0 1 OPERATING MODE Enable A-word Enable B-word
Controlled with terminal 39, LEARN/HOLD
LEARN/HOLD 0 1 OPERATING MODE Selects data slicer decision level to HOLD Selects data slicer decision level to LEARN
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
APPLICATION INFORMATION
BPF1 SFECV10.7 MA 2S-A or SFECF10M7EA00 BW = 330 kHz C4 3 1 C5 82 pF 15 pF C6 82 pF 2 C7 120 pF L1 4.7 H RSSI DEM_VCC
C9 68 pF MIX_VCC DET_OUT
LRN/HOLD
J1
RX_IN+
C13
C12 2.7 pF
L3 4.7 H 48 MIX_OUT 47 46 IF_IN2 43 45 IF_IN1 44 42 RSSI_ OUT 41
R5 220 k
C14 39 40 22 pF J4 C15 L2 10 nH LEARN/ HOLD 38 37
15 pF
DET_OUT
LPF_IN
C16 2.7 pF
1 2 3 LNA
RSSI
LPF_OUT 36 CER_DIS 35 SLC_CAP 34 C20
CDSCB10M7GA119, CDSCA10M7GA119, or CDACV10M7GA001 2200 pF DIS1 10.7 RX_DATA TX_DATA C22 68 pF
J2
TX_OUT
C21
LNA_VCC
4 1.8 pF L6 8.2 nH 5
PA_OUT
Data slicer
RX_DATA 33 TX_DATA 32
PA
6
PA_VCC
XTAL_SW 31 U1 TRF6901 Reference Generator XTAL 30 29 28 27
PA_VCC C23 150 pF 7 8 VCO_VCC 9 10 VCO_VCC
VCO_TANK2 VCO_TANK1
XTAL1 SMI 97SMX(C)- 20 MHZ
C24 15 pF
C26 0.1 F VCO_VCC2 DCDC_OUT 3 2 1 JP1
11 C27 100 pF 12
VCO PLL VCO_TUNE DC-DC Converter CP_VCC
CLKTST_OUT 26 DC_DC_IN 25 XTAL_VCC MCU_CLK STDBY C2 C1 DCDC_VCC C31 0.1 F
C36
13
14
15
CP_OUT 16
17
18
19
20
21
22
23
24 C35
DVDD
CLOCK
DATA
100 pF C44
R14 18 k
STROBE
MODE
0.22 F DCDC_OUT
1000 pF C49 R19 6.8 k JP3 1 2 3 C45 0.1 F C46 10000 pF DCDC_OUT VCO_VCC2
10000 pF
Figure 10. Typical Application Schematic for the 868-MHz to 870-MHz European ISM Band 32-kbps NRZ, 50-kHz Deviation FSK Application
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TRF6901 SINGLE CHIP RF TRANSCEIVER
SLWS110G - SEPTEMBER 2001 - REVISED JUNE 2004
APPLICATION INFORMATION
BPF1 SFECV10.7 MA 2S-A or SFECF10M7EA00 BW = 330 kHz C4 3 1 C5 82 pF 15 pF C6 82 pF 2 C7 120 pF L1 4.7 H RSSI DEM_VCC
C9 68 pF MIX_VCC DET_OUT
LRN/HOLD
J1
RX_IN+
C13
C12 2.7 pF
L3 4.7 H 48 MIX_OUT 47 46 IF_IN2 43 45 IF_IN1 44 42 RSSI_ OUT 41
R5 220 k
C14 39 LEARN/ HOLD 38 22 pF J4 C15 L2 10 nH 40 37
15 pF
DET_OUT
LPF_IN
C16 2.7 pF
1 2 LNA
RSSI
LPF_OUT 36 CER_DIS 35 SLC_CAP 34 C20
CDSCB10M7GA119, CDSCA10M7GA119, or CDACV10M7GA001 2200 pF DIS1 10.7 RX_DATA TX_DATA C22 68 pF
J2
TX_OUT
C21
LNA_VCC
3 4 PA_OUT Data slicer
RX_DATA 33 TX_DATA 32
1.8 pF
L6 8.2 nH
5 PA 6
XTAL_SW 31 U1 TRF6901 Reference Generator XTAL 30 29 28 27
PA_VCC
PA_VCC C23 150 pF 7 8 VCO_VCC 9 10 VCO_VCC
VCO_TANK2 VCO_TANK1
XTAL1 SMI 97SMX(C)- 20 MHZ
C24 15 pF
C26 0.1 F
VCO_VCC2 DCDC_OUT
11 C27 100 pF 12
VCO PLL VCO_TUNE DC-DC Converter CP_VCC
CLKTST_OUT 26 DC_DC_IN 25 XTAL_VCC MCU_CLK STDBY C2 C1 DCDC_VCC C31 0.1 F
3 2 1 JP1 C36 13
14
15
CP_OUT 16
17
18
19
20
21
22
23
24 C35
DVDD
CLOCK
DATA
100 pF C44
R14 18 k
STROBE
MODE
0.22 F R13 100 C37 0.47 F
L7 47 H DCDC_OUT
1000 pF C49 R19 6.8 k JP3 1 2 3 C45 0.1 F C46 10000 pF
C38 1 F
C39 0.47 F
10000 pF
DCDC_OUT VCO_VCC2
Figure 11. Typical Application Schematic for the 902-MHz to 928-MHz North American 32-kbps NRZ, 50-kHz Deviation FSK Application
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MECHANICAL DATA
MTQF003A - OCTOBER 1994 - REVISED DECEMBER 1996
PT (S-PQFP-G48)
0,27 0,17 36 25
PLASTIC QUAD FLATPACK
0,50
0,08 M
37
24
48
13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,25 1,45 1,35 0,05 MIN 0- 7 Gage Plane 12
Seating Plane 1,60 MAX 0,10
0,75 0,45
4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads conected to the die pads.
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