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TLV5627C, TLV5627I 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS232A - JUNE1999 - REVISED JULY 2002
D D D D D D D
Four 8-Bit D/A Converters Programmable Settling Time of 2.5 s or 8.5 s Typ TMS320, (Q)SPI, and Microwire Compatible Serial Interface Low Power Consumption: 7 mW, Slow Mode - 5-V Supply 3 mW, Slow Mode - 3-V Supply Reference Input Buffers Monotonic Over Temperature Dual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies)
D D D D D D D D
Hardware Power Down Software Power Down Simultaneous Update
applications
Battery Powered Test Instruments Digital Offset and Gain Adjustment Industrial Process Controls Machine and Motion Control Devices Arbitrary Waveform Generation
description
The TLV5627 is a four channel, 8-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5627 is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and an 8-bit DAC value.
D OR PW PACKAGE (TOP VIEW)
The device has provision for two supplies: one digital supply for the serial interface (via pins DVDD and DGND), and one for the DACs, reference buffers and output buffers (via pins AVDD and AGND). Each supply is independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins DVDD and DGND), with the DACs operating on a 5-V supply. The digital and analog supplies can be tied together. The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode make it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage than DACs C and D. The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The TLV5627C is characterized for operation from 0C to 70C. The TLV5627I is characterized for operation from - 40C to 85C.
DVDD PD LDAC DIN SCLK CS FS DGND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
AVDD REFINAB OUTA OUTB OUTC OUTD REFINCD AGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
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TLV5627C, TLV5627I 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS232A - JUNE1999 - REVISED JULY 2002
AVAILABLE OPTIONS PACKAGE TA 0C to 70C - 40C to 85C SOIC (D) TLV5627CD TLV5627ID TSSOP (PW) TLV5627CPW TLV5627IPW
functional block diagram
AVDD REFINAB 15 DAC A Power-On Reset + _ x2 14 16 DVDD 1
OUTA
8 10 10-Bit Data and Control Register
DIN
4
Serial Input Register 2
8-Bit DAC Latch
8
2
7 FS 5 SCLK CS 6 DAC Select/ Control Logic
2-Bit Control Data Latch
2 Power Down/ Speed Control
DAC B
13
OUTB
DAC C
12
OUTC
REFINCD
DAC D 3 9 AGND 8 DGND LDAC PD 2
11
OUTD
2
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TLV5627C, TLV5627I 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS232A - JUNE1999 - REVISED JULY 2002
Terminal Functions
TERMINAL NAME AGND AVDD CS DGND DIN DVDD FS PD LDAC REFINAB REFINCD SCLK OUTA OUTB OUTC OUTD NO. 9 16 6 8 4 1 7 2 3 15 10 5 14 13 12 11 I I I I I I O O O O I I I/O Analog ground Analog supply Chip select. This terminal is active low. Digital ground Serial data input Digital supply Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to the TLV5627. Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages. This terminal is active low. Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into the serial interface. The DAC outputs are only updated when LDAC is low. Voltage reference input for DACs A and B. Voltage reference input for DACs C and D. Serial clock input DAC A output DAC B output DAC C output DAC D output DESCRIPTION
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Supply voltage difference, (AVDD to DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.8 V to 2.8 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.3 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V Operating free-air temperature range, TA: TLV5627C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5627I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SLAS232A - JUNE1999 - REVISED JULY 2002
recommended operating conditions
MIN Supply voltage AVDD, DVDD voltage, High-level High level digital input voltage VIH voltage, Low-level Low level digital input voltage, VIL voltage Reference voltage, Vref to REFINAB REFINCD terminal voltage f REFINAB, Load resistance, RL Load capacitance, CL Serial clock rate, SCLK Operating free air temperature free-air TLV5627C TLV5627I 0 -40 5-V supply 3-V supply DVDD = 2.7 V DVDD = 5.5 V DVDD = 2.7 V DVDD = 5.5 V 5-V supply (see Note 1) 3-V supply (see Note 1) 0 0 2 2.048 1.024 10 100 20 70 85 4.5 2.7 2 2.4 0.6 1 AVDD-1.5 AVDD-1.5 NOM 5 3 MAX 5.5 3.3 UNIT V V V V k pF MHz C
NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
static DAC specifications
PARAMETER Resolution Integral nonlinearity (INL), end point adjusted Differential nonlinearity (DNL) EZS Zero scale error (offset error at zero scale) Zero scale error temperature coefficient EG Gain error Gain error temperature coefficient See Note 2 See Note 3 See Note 4 See Note 5 See Note 6 See Note 7 10 10 0.6 TEST CONDITIONS MIN 8 0.3 0.03 0.5 0.5 10 TYP MAX UNIT bits LSB LSB mV ppm/C %of FS voltage ppm/C
NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. 3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref x 106/(Tmax - Tmin). 6. Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 k excluding the effects of the zero-error. 7. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref x 106/(Tmax - Tmin).
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER VO Voltage output Output load regulation accuracy RL = 10 k RL = 2 k vs 10 k TEST CONDITIONS MIN 0 0.1 TYP MAX AVDD-0.4 0.25 UNIT V % of FS voltage
reference input (REFINAB, REFINCD)
PARAMETER VI RI CI Input voltage range Input resistance Input capacitance Reference feed through Reference input bandwidth REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9) REFIN = 0.2 Vpp + 1.024 V dc 02 1 024 Slow Fast See Note 8 TEST CONDITIONS MIN 0 10 5 -75 0.5 1 TYP MAX AVDD-1.5 UNIT V M pF dB MHz
NOTES: 8. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes. 9. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD) input = 1.024 Vdc + 1 Vpp at 1 kHz.
digital inputs (D0-D11, CS, WEB, LDAC, PD)
PARAMETER IIH IIL CI High-level digital input current Low-level digital input current Input capacitance TEST CONDITIONS VI = DVDD VI = 0 V 3 MIN TYP MAX 1 1 UNIT A A pF
power supply
PARAMETER TEST CONDITIONS 5-V supply 5 V supply, No load, Clock running load IDD Power supply current 3 V supply, No load, Clock running load 3-V supply Power down supply current, See Figure 12 PSRR Power supply rejection ratio Zero scale gain Gain See Notes 10 and 11 Slow Fast Slow Fast MIN TYP 1.4 3.5 1 3 1 - 68 - 68 MAX 2.2 5.5 1.5 4.5 UNIT mA mA A dB
10. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the AVDD from 5 0.5 V and 3 0.3 V dc, and measuring the proportion of this signal imposed on the zero-code output voltage. 11. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 0.5 V and 3 0.3 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER SR Output slew rate TEST CONDITIONS CL = 100 pF, RL = 10 k, VO = 10% to 90% 90%, Vref = 2.048 V, 1024 V To 0.1 LSB, CL = 100 pF, , , RL = 10 k, See Notes 12 and 14 To 0.1 LSB, CL = 100 pF, , , RL = 10 k, See Notes 13 and 14 Code transition from 7F0 to 800 Sinewave generated by DAC, DAC Reference voltage = 1.024 at 3 V and 2.048 at 5 V, g , fs = 400 KSPS, fOUT = 1.1 kHz sinewave, RL = 10 k, BW = 20 kHz CL = 100 pF, pF k kH Fast Slow Fast Slow Fast Slow MIN TYP 5 1 2.5 8.5 1 2 10 57 49 -50 60 dB 4 18 MAX UNIT V/s V/s s s nV-sec
ts ts(c) ()
Output settling time Output settling time, code to code time Glitch energy
SNR S/(N+D) THD SFDR
Signal-to-noise ratio Signal to noise + distortion Total harmonic distortion Spurious free dynamic range
NOTES: 12. Settling time is the time for the output signal to remain within 0.1 LSB of the final measured value for a digital input code change of 0x020 to 0xFF0 or 0xFF0 to 0x020. 13. Settling time is the time for the output signal to remain within 0.1 LSB of the final measured value for a digital input code change of one count. 14. Limits are ensured by design and characterization, but are not production tested.
digital input timing requirements
MIN tsu(CS-FS) tsu(FS-CK) tsu(C16-FS) tsu(C16-CS) twH twL tsu(D) th(D) twH(FS) Setup time, CS low before FS Setup time, FS low before first negative SCLK edge Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before rising edge of FS Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS is used instead of the SCLK positive edge to update the DAC, then the setup time is between the FS rising edge and CS rising edge. Pulse duration, SCLK high Pulse duration, SCLK low Setup time, data ready before SCLK falling edge Hold time, data held valid after SCLK falling edge Pulse duration, FS high 10 8 10 NOM MAX UNIT ns ns ns
10 25 25 8 5 20
ns ns ns ns ns ns
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PARAMETER MEASUREMENT INFORMATION
twL SCLK twH
1
2 th(D) D15 D14
3
4
5
15
16
tsu(D)
DIN
D13
D12
D1
D0
tsu(FS-CK)
tsu(CS-FS)
tsu(C16-CS)
CS twH(FS) FS tsu(C16-FS)
Figure 1. Timing Diagram
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III III II II
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IIII IIII IIII IIII
TLV5627C, TLV5627I 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS232A - JUNE1999 - REVISED JULY 2002
TYPICAL CHARACTERISTICS
LOAD REGULATION
0.35 0.30 0.25 5 V Slow Mode, Sink 0.20 5 V Fast Mode, Sink 0.15 VDD = 5 V, VREF = 2 V, VO = Full Scale VO - Output Voltage - V 0.20 0.18 0.16 0.14 3 V Slow Mode, Sink 0.12 0.10 0.08 0.06 0.04 0.05 0.02 0 0 0.02 0.04 0.1 0.2 0.4 0.8 1 2 4 Load Current - mA 0 0 0.01 0.02 0.05 0.1 0.2 0.5 Load Current - mA 0.8 1 2 3 V Fast Mode, Sink VDD = 3 V, VREF = 1 V, VO = Full Scale
LOAD REGULATION
VO - Output Voltage - V
0.10
Figure 2
LOAD REGULATION
4.002 4.00 5 V Slow Mode, Source 3.998 VO - Output Voltage - V 3.996 3.994 5 V Fast Mode, Source 3.992 3.99 3.988 3.986 3.984 0 0.02 0.04 0.1 0.2 0.4 0.8 Load Current - mA 1 2 4 VDD = 5 V, VREF = 2 V, VO = Full Scale VO - Output Voltage - V 2.003 2.0025
Figure 3
LOAD REGULATION
3 V Fast Mode, Source 2.002 2.0015 2.001 2.0005 2 1.9995 1.999 0 VDD = 3 V, VREF = 1 V, VO = Full Scale 0.01 0.02 0.05 0.1 0.2 0.5 Load Current - mA 0.8 1 2 3 V Slow Mode, Source
Figure 4
Figure 5
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs TEMPERATURE
4 3.5 I DD - Supply Current - mA VDD = 3 V, VREF = 1.024 V, VO = Full Scale 4 3.5 Fast Mode I DD - Supply Current - mA 3 2.5 2 Slow Mode
SUPPLY CURRENT vs TEMPERATURE
Fast Mode
3 2.5 2
1.5 Slow Mode 1 0.5 -40
1.5 1 0.5 -40 VDD = 5 V, VREF = 1.024 V, VO = Full Scale -20
-20
0 20 40 60 T - Temperature - C
80
100
0 20 40 60 T - Temperature - C
80
100
Figure 6
TOTAL HARMONIC DISTORTION vs FREQUENCY
0 THD - Total Harmonic Distortion - dB -10 -20 -30 --40 -50 -60 Fast Mode -70 -80 0 5 10 20 30 50 100 f - Frequency - kHz Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale 0 THD - Total Harmonic Distortion - dB -10 -20 -30 --40 -50 -60
Figure 7
TOTAL HARMONIC DISTORTION vs FREQUENCY
Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale
Slow Mode -70 -80 0 5 10 20 30 50 100 f - Frequency - kHz
Figure 8
Figure 9
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY
THD - Total Harmonic Distortion And Noise - dB Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale THD - Total Harmonic Distortion And Noise - dB 0 -10 -20 -30 --40 -50 Fast Mode -60 -70 -80 0 5 10 20 30 50 100 f - Frequency - kHz 0 -10 -20 -30 --40 -50 Slow Mode -60 -70 -80 0 5 10 20 30 50 100 f - Frequency - kHz Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale
TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY
Figure 10
SUPPLY CURRENT vs TIME (WHEN ENTERING POWER-DOWN MODE)
4000 3500 I DD - Supply Current - A 3000 2500 2000 1500 1000 500 0 0 200 400 600 800
Figure 11
1000
t - Time - ns
Figure 12
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TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE
DNL - Differential Nonlinearity - LSB 0.20 0.15 0.10 0.05 -0.00 -0.05 -0.10 -0.15 -0.20 0 64 128 Digital Output Code 192 255
Figure 13
INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE
INL - Integral Nonlinearity - LSB 0.40 0.30 0.20 0.10 -0.00 -0.10 -0.20 -0.30 -0.40 0 64 128 Digital Output Code 192 255
Figure 14
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APPLICATION INFORMATION general function
The TLV5627 is an 8-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by external reference) is given by: 2 REF CODE [V] 2n Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n-1, where n=8 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new level. The serial interface of the TLV5627 can be used in two basic modes:
D D
Four wire (with chip select) Three wire (without chip select)
Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows an example with two TLV5627s connected directly to a TMS320 DSP.
TLV5627 CS FS DIN SCLK TLV5627 CS FS DIN SCLK
TMS320 DSP XF0 XF1 FSX DX CLKX
Figure 15. TMS320 Interface
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APPLICATION INFORMATION serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5627 to a TMS320, SPI, or Microwire port using only three pins.
TMS320 DSP FSX DX CLKX TLV5627 FS DIN SCLK CS SPI SS MOSI SCLK TLV5627 FS DIN SCLK CS Microwire I/O SO SK TLV5627 FS DIN SCLK CS
Figure 16. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5627. After the write operation(s), the DAC output is updated automatically on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by: f SCLKmax
+t
) twL(min) + 20 MHz wH(min)
1 1 16 t
The maximum update rate is: f UPDATEmax
+
wH(min)
) twL(min)
+ 1.25 MHz
The maximum update rate is a theoretical value for the serial interface since the settling time of the TLV5627 has to be considered also.
data format
The 16-bit data word for the TLV5627 consists of two parts:
D D
D15 A1
Control bits New DAC value
D14 A0 D13 PWR D12 SPD
(D15 . . . D12) (D11 . . . D0)
D11 D10 D9 D8 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0
New DAC value (8 bits) 0 slow mode 0 normal operation
SPD: Speed control bit. PWR: Power control bit.
1 fast mode 1 power down
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APPLICATION INFORMATION
In power-down mode, all amplifiers within the TLV5627 are disabled. A particular DAC (A, B, C, D) of the TLV5627 is selected by A1 and A0 within the input word.
A1 0 0 1 1 A0 0 1 0 1 DAC A B C D
TLV5627 interfaced to TMS320C203 DSP
hardware interfacing Figure 17 shows an example of how to connect the TLV5627 to a TMS320C203 DSP. The serial port is configured in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the TLV5627. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose input/output port bits IO0 and IO1 are used to generate the chip select ( CS) and DAC latch update ( LDAC) inputs to the TLV5627. The active low power down ( PD) is pulled high all the time to ensure the DACs are enabled.
TMS320C203 DX CLKX FSX I/O 0 I/O 1 SDIN SCLK FS CS LDAC REFINAB REF REFINCD VOUTA VOUTB VOUTC VOUTD VSS TLV5627 VDD PD
Figure 17. TLV5627 Interfaced with TMS320C203
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APPLICATION INFORMATION TLV5627 interfaced to MCS51 microcontroller
hardware interfacing Figure 18 shows an example of how to connect the TLV5627 to an MCS51 Microcontroller. The serial DAC input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5627. The active low power down pin (PD) of the TLV5627 is pulled high to ensure that the DACs are enabled.
MCS(R)51 RxD TxD P3.3 P3.4 P3.4 SDIN SCLK LDAC CS FS REFINAB REF REFINCD VOUTA VOUTB VOUTC VOUTD VSS TLV5627 VDD PD
Figure 18. TLV5627 Interfaced with MCS51
linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19.
Output Voltage
0V Negative Offset DAC Code
Figure 19. Effect of Negative Offset (single supply)
MCS is a registered trademark of Intel Corporation.
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APPLICATION INFORMATION linearity, offset, and gain error using single ended supplies (continued)
The offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well-managed and there are negligible voltage drops across the ground plane. A 0.1-F ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 20 shows the ground plane layout and bypassing technique.
Analog Ground Plane 1 2 3 4 8 7 6 5 0.1 F
Figure 20. Power-Supply Bypassing
16
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV5627C, TLV5627I 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS232A - JUNE1999 - REVISED JULY 2002
MECHANICAL DATA
D (R-PDSO-G**)
14 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
17
TLV5627C, TLV5627I 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS232A - JUNE1999 - REVISED JULY 2002
MECHANICAL DATA
PW (R-PDSO-G**)
14 PIN SHOWN 0,30 0,19 14 8
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX 8 14 16 20 24 28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60 4040064 / E 08/96
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
18
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright 2002, Texas Instruments Incorporated

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