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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
D D D D D D D D D D D D D D D
Four 8-Bit Voltage Output DACs 3-V Single-Supply Operation Serial Interface High-Impedance Reference Inputs Programmable for 1 or 2 Times Output Range Simultaneous Update Facility Internal Power-On Reset Low-Power Consumption Half-Buffered Output
D OR N PACKAGE (TOP VIEW)
GND REFA REFB REFC REFD DATA CLK
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD LDAC DACA DACB DACC DACD LOAD
applications
Programmable Voltage Sources Digitally Controlled Amplifiers/Attenuators Mobile Communications Automatic Test Equipment Process Monitoring and Control Signal Synthesis
description
The TLV5620C and TLV5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two times the reference voltages and GND; and, the DACs are monotonic. The device is simple to use, because it runs from a single supply of 3 V to 3.6 V. A power-on reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLV5620C and TLV5620I is over a simple three-wire serial bus that is CMOS compatible and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word comprises eight bits of data, two DAC select bits, and a range bit, the latter allowing selection between the times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written to the device, then all DAC outputs update simultaneously through control of LDAC. The digital inputs feature Schmitt triggers for high noise immunity. The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical applications. The TLV5620C is characterized for operation from 0C to 70C. The TLV5620I is characterized for operation from - 40C to 85C. The TLV5620C and TLV5620I do not require external trimming.
AVAILABLE OPTIONS PACKAGE TA 0C to 70C - 40C to 85C SMALL OUTLINE (D) TLV5620CD TLV5620ID PLASTIC DIP (N) TLV5620CN TLV5620IN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
functional block diagram
REFA 2 + - 8 REFB 3 + - 8 REFC 4 + - 8 REFD 5 + - 8 Latch Latch 8 DAC x2 + - 9 DACD Latch Latch 8 Latch Latch 8 Latch Latch 8
DAC
x2
+ -
12
DACA
DAC
x2
+ -
11
DACB
DAC
x2
+ -
10
DACC
CLK DATA LOAD
7 6 8 Serial Interface 13 LDAC Power-On Reset
Terminal Functions
TERMINAL NAME CLK DACA DACB DACC DACD DATA GND LDAC LOAD REFA REFB REFC REFD VDD NO. 7 12 11 10 9 6 1 13 8 2 3 4 5 14 I/O I O O O O I I I I I I I I I DESCRIPTION Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock applied to the CLK terminal. DAC A analog output DAC B analog output DAC C analog output DAC D analog output Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially. Each data bit is clocked into the register on the falling edge of the clock signal. Ground return and reference terminal Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial interface. The DAC outputs are only updated when LDAC is taken from high to low. Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital data into the output latch and immediately produces the analog voltage at the DAC output terminal. Reference voltage input to DAC A. This voltage defines the output analog range. Reference voltage input to DAC B. This voltage defines the analog output range. Reference voltage input to DAC C. This voltage defines the analog output range. Reference voltage input to DAC D. This voltage defines the analog output range. Positive supply voltage
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
detailed description
The TLV5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance of the output buffer. Since the inputs are buffered, the DACs always presents a high-impedance load to the reference source. Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or times 2 gain. On power up, the DACs are reset to CODE 0. Each output voltage is given by: V (DACA|B|C|D) O
+ REF
CODE 256
(1
) RNG bit value)
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word. Table 1. Ideal Output Transfer
D7 0 0 * * 0 1 * * 1 D6 0 0 * * 1 0 * * 1 D5 0 0 * * 1 0 * * 1 D4 0 0 * * 1 0 * * 1 D3 0 0 * * 1 0 * * 1 D2 0 0 * * 1 0 * * 1 D1 0 0 * * 1 0 * * 1 D0 0 1 * * 1 0 * * 1 OUTPUT VOLTAGE GND (1/256) x REF (1+RNG) * * (127/256) x REF (1+RNG) (128/256) x REF (1+RNG) * * (255/256) x REF (1+RNG)
data interface
With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When LDAC is high during serial programming, the new value is stored within the device and can be transferred to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data transfers using two 8-clock-cycle periods are shown in Figures 3 and 4. Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output range. When RNG = low, the output range is between the applied reference voltage and GND, and when RNG = high, the range is between twice the applied reference voltage and GND. Table 2. Serial Input Decode
A1 0 0 1 1 A0 0 1 0 1 DAC UPDATED DACA DACB DACC DACD
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
CLK tsu(DATA-CLK) tv(DATA-CLK) DATA A1 A0 RNG D7 D6 D5 D4 D3 tsu(LOAD-CLK) D2 D1 D0
tsu(CLK-LOAD) LOAD
tw(LOAD)
DAC Update
Figure 1. LOAD-Controlled Update (LDAC = Low)
CLK tsu(DATA-CLK) tv(DATA-CLK) DATA A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0
tsu(LOAD-LDAC) LOAD tw(LDAC) LDAC DAC Update
Figure 2. LDAC-Controlled Update
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CLK Low CLK
DATA
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
LOAD LDAC
Figure 3. Load Controlled Update Using 8-Bit Serial Word (LDAC = Low)
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CLK Low CLK
DATA
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
LOAD LDAC
Figure 4. LDAC Controlled Update Using 8-Bit Serial Word
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
IIIII IIIII
IIII IIII
TLV5620C, TLV5620I QUADRUPLE 8-DIGITAL-TO-ANALOG CONVERTERS
IIII IIII III III
IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
linearity, offset, and gain error using single-end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.
Output Voltage
0V Negative Offset DAC Code
Figure 5. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below ground. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single-supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. The code is calculated from the maximum specification for the negative offset.
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
equivalent inputs and outputs
INPUT CIRCUIT VDD Input from Decoded DAC Register String _ + x1 84 k ISINK 60 A Typical GND DAC Voltage Output OUTPUT CIRCUIT VDD
Vref Input To DAC Resistor String GND
Output Range x 2 Select
84 k
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD - GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3 V to VDD + 0.3 V Reference input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5620C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5620I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Reference voltage, Vref [A|B|C|D], x1 gain Load resistance, RL Setup time, data input, tsu(DATA-CLK) (see Figures 1 and 2) Valid time, data input valid after CLK, tv(DATA-CLK) (see Figures 1 and 2) Setup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) (see Figure 1) Setup time, LOAD to CLK, tsu(LOAD-CLK) (see Figure 1) Pulse duration, LOAD, tw(LOAD) (see Figure 1) Pulse duration, LDAC, tw(LDAC) (see Figure 2) Setup time, LOAD to LDAC, tsu(LOAD-LDAC) (see Figure 2) CLK frequency Operating free-air temperature, TA free air temperature TLV5620C TLV5620I 0 - 40 10 50 50 50 50 250 250 0 1 70 85 2.7 0.8 VDD 0.8 VDD - 1.5 NOM 3.3 MAX 5.25 UNIT V V V V k ns ns ns ns ns ns ns MHz C
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
electrical characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 2 V, x 1 gain output range (unless otherwise noted)
PARAMETER IIH IIL IO(sink) IO(source) Ci IDD Iref EL ED EZS EFS PSRR High-level input current Low-level input current Output sink current Output source current Input capacitance Reference input capacitance Supply current Reference input current Linearity error (end point corrected) Differential linearity error Zero-scale error Zero-scale error temperature coefficient Full-scale error Full-scale error temperature coefficient Power-supply sensitivity VDD = 3.3 V VDD = 3.3 V, Vref = 1.5 V Vref = 1.25 V, x 2 gain, See Note 1 Vref = 1.25 V, x 2 gain, See Note 2 Vref = 1.25 V, x 2 gain, See Note 3 Vref = 1.25 V, x 2 gain, See Note 4 Vref = 1.25 V, x 2 gain, See Note 5 Vref = 1.25 V, x 2 gain, See Note 6 See Notes 7 and 8 0 10 60 25 0.5 VI = VDD VI = 0 V Each DAC output 20 1 15 15 2 10 1 0.9 30 TEST CONDITIONS MIN TYP MAX 10 10 UNIT A A A mA pF mA A LSB LSB mV V/C mV V/C mV/V
NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full-scale errors). 2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) - ZSE(Tmin)]/Vref x 106/(Tmax - Tmin). 5. Full-scale error is the deviation from the ideal full-scale output (Vref - 1 LSB) with an output load of 10 k. 6. Full-scale error temperature coefficient is given by: FSETC = [FSE(Tmax) - FSE (Tmin)]/Vref x 106/(Tmax - Tmin). 7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the effect of this signal on the zero-code output voltage. 8. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD voltage from 3 V to 3.6 V dc and measuring the effect of this signal on the full-scale output voltage.
operating characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 2 V, x 1 gain output range (unless otherwise noted)
TEST CONDITIONS Output slew rate Output settling time Large-signal bandwidth Digital crosstalk Reference feedthrough Channel-to-channel isolation Reference input bandwidth CL = 100 pF To 0.5 LSB, RL = 10 k CL = 100 pF, RL = 10 k, See Note 9 MIN TYP 1 10 100 - 50 - 60 - 60 100 MAX UNIT V/s s kHz dB dB dB kHz
Measured at - 3 dB point CLK = 1-MHz square wave measured at DACA-DACD See Note 10 See Note 11 See Note 12
NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within 0.5 LSB starting from an initial output voltage equal to zero. 10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 VPP at 10 kHz. 11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex with Vref input = 1 V dc + 1 VPP at 10 kHz. 12. Reference bandwidth is the -3 dB bandwidth with an input at Vref = 1.25 V dc + 2 VPP and with a digital input code of full-scale.
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
TLV5620 DACA DACB DACC DACD
10 k
CL = 100 pF
Figure 6. Slew, Settling Time, and Linearity Measurements
TYPICAL CHARACTERISTICS
POSITIVE RISE TIME AND SETTLING TIME
3 2.5 2 1.5 1 0.5 0 - 0.5 -1 0 2 4 6 8 10 12 14 16 18 20 Time - s NOTE A: Rise time = 2.05 s, positive slew rate = 0.96 V/s, settling time = 4.5 s. 3 2.5 2 1.5 1 0.5 0 - 0.5 -1 0 2 4 6 8 10 12 14 16 18 20 Time - s NOTE A: Fall time = 4.25 s, negative slew rate = 0.46 V/s, settling time = 8.5 s. VDD = 3 V TA = 25C Code FF to 00 Hex Range = x2 Vref = 1.25 V (see Note A)
NEGATIVE FALL TIME AND SETTLING TIME
VO - Output Voltage - V
VDD = 3 V TA = 25C Code 00 to FF Hex Range = x2 Vref = 1.25 V (see Note A)
Figure 7
VO - Output Voltage - V
Figure 8
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
TYPICAL CHARACTERISTICS
DAC OUTPUT VOLTAGE vs OUTPUT LOAD
3 2.8 VO - DAC Output Voltage - V 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0 10 20 30 40 50 60 70 80 RL - Output Load - k 90 100 VDD = 3 V, Vref = 1.5 V, Range = 2x VO - DAC Output Voltage - V 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 90 100 RL - Output Load - k VDD = 3 V, Vref = 1.5 V, Range = 1x
DAC OUTPUT VOLTAGE vs OUTPUT LOAD
Figure 9
SUPPLY CURRENT vs TEMPERATURE
1.2 1.15 I DD - Supply Current - mA 1.1 1.05 1 0.95 0.9 0.85 0.8 - 50 Range = x 2 Input Code = 255 VDD = 3 V Vref = 1.25 V
Figure 10
0
50
100
t - Temperature - C
Figure 11
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
APPLICATION INFORMATION
TLV5620 DACA DACB DACC DACD _ + R VO
NOTE A: Resistor R
w 10 k
Figure 12. Output Buffering Scheme
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
MECHANICAL DATA
D (R-PDSO-G**)
14 PIN SHOWN PINS ** DIM 0.020 (0,51) 0.014 (0,35) 14 8 A MIN 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.008 (0,20) NOM 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) 0.010 (0,25) M A MAX
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27)
8 0.197 (5,00)
14 0.344 (8,75)
16 0.394 (10,00)
1 A
7
Gage Plane
0.010 (0,25) 0- 8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) 4040047 / B 10/94 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Four center pins are connected to die mount pad Falls within JEDEC MS-012
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TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B - JANUARY 1995 - REVISED APRIL 1997
MECHANICAL DATA
N (R-PDIP-T**)
16 PIN SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
A 16 9 PINS ** DIM A MAX 0.260 (6,60) 0.240 (6,10) 14 0.775 (19,69) 0.745 (18,92) 16 0.775 (19,69) 0.745 (18,92) 18 0.920 (23.37) 0.850 (21.59) 20 0.975 (24,77) 0.940 (23,88)
A MIN
1
8 0.070 (1,78) MAX
0.035 (0,89) MAX
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM
0- 15
14 Pin Only 4040049 / C 7/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)
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Copyright (c) 1999, Texas Instruments Incorporated

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