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CAN-LDO
Target Data
Features * * * * * * * * * * * * * Standard fault tolerant differential CAN-transceiver Bus failure management Low power mode management CAN data transmission rate up to 125 kBaud Low-dropout voltage 5 V regulator for internal and external supply; tolerance 2% High Side Switche Power on and under-voltage reset generator Window watchdog Programable time base Standard 8 bit SPI-Interface Wide input voltage range Wide temperature range Enhanced power P-DSO-Package Ordering Code on request
TLE 6263 G
P-DSO-28-6 Enhanced Power
Type
w TLE 6263 G w New type
Package P-DSO-28-6 (SMD)
Functional Description The TLE 6263 G is a monolithic integrated circuit in a P-DSO-28-6 package, which incorporates a failure tolerant low speed CAN-transceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5V supply as well as a SPI (serial peripheral interface) to control and monitor the IC. Further there are integrated a high side switch, a wake-up input, a window watchdog circuit as well as a reset and early warning feature. Both, the window watchdog and reset function are referring to a time base that is programmable via an external resistor. The IC is designed to withstand the severe conditions of automotive applications.
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TLE 6263 G
Pin Configuration (not yet fixed) (top view)
CANH RTH RO CANL RTL GND GND GND GND SI SO WK N.C. OUTHS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
TLE 6263
28 27 26 25 24 23 22 21 20 19 18 17 16 15
OSC N.C. TxD RxD VCC GND GND GND GND CLK DI DO CSN VS
AEP02567
Figure 1
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TLE 6263 G
Pin Definitions and Functions Pin No. Symbol CANH RTH RO CANL RTL 6, 7, 8, 9, GND 20, 21, 22, 23 SI Function H Bus Line; HIGH in dominant state Termination Input for CANH Reset Output; integrated pull up L Bus Line; LOW in dominant state Termination Input for CANL Ground; to reduce thermal resistance place cooling areas on PCB close to this pins. Early Warning Input Early Warning Output; internal pull up Wake-Up Input; for wake-up via external contacts not connected High Side Output; controlled via SPI, in sleep mode optionaly controlled by internal autotiming function Power Supply; block to GND directly at the IC with ceramic capacitor SPI Interface Chip Select Not; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs SPI Interface Data Out; this tristate output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN); see Table 2 for Diagnosis protocol SPI Interface Data In; receives serial data from the control device; serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) being transferred first: the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see Table 1 for input data protocol. SPI Interface Clock Input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs
SO WK
N.C. OUTHS
VS
CSN
DO
DI
CLK
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TLE 6263 G
Pin Definitions and Functions (cont'd) Pin No. Symbol Function Output Voltage Regulator; 5 V logic supply, block to GND with an external capacitor CQ 10 F, ESR > 1 Receive Data Output; integrated pull up Transmit Data Input; integrated pull up not connected Oscillator Input; time base for power on reset, watchdog window and stand by timer for HS3, to program connect external resistor to GND
VCC
RxD TxD N.C. OSC
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TLE 6263 G
Functional Block Diagram
VBat
OUTHS
Charge Pump
Drive+ Protection
SPI
CSN CLK DI DQ
VCC
Time Base OSC
+ -
Band Gap
Reset Generator + Watchdog CAN Standby/Sleep Control
RO
SI SO
Early Warning
WK
RTL CANH CANL RTH Filter Receiver H Output Stage L Output Stage Driver Temp Protect Input Stage RxD TxD
CAN Fail Detect GND
AEB02569
Figure 2
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Fail Management
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TLE 6263 G
Circuit Description The TLE 6263 G is a monolithic IC, which incorporates a failure tolerant low speed CANtransceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5 V supply as well as a SPI (serial periperal interface) to control and monitor the IC. Further there are integrated a high side switche, a wake-up input, a window watchdog circuit as well as a reset circuit and early warning function. Both, the window watchdog and reset function are referring to a time base that is programmable via an external resistor. Figure 2 shows a block schematic diagram of the TLE 6263 G. CAN Transceiver Apart from the following deviations the CAN transceiver integrated in the TLE 6263 G is identical to the stand-alone transceiver TLE 6252: A pin NERR for flagging any failure does not exist. The bus failures according to Table 3 can be monitored via the diagnosis protocol of the SPI interface. Therefore it is possible to distinguish 6 CAN bus failures or failure groups on the bits 8 to 13 (see Table 2). When setting the transceiver into sleep mode the internal and external 5 V supplies are automatically disabled. This feature can be masced via the SPI input bit 7. Setting/waking up of the CAN-transceiver into/from sleep mode or stand-by mode is done via the SPI interface (bits 2 and 3, see Table 1). When a reset occurs the transceiver circuit is switched to Vbat-stand-by mode because the SPI input bits are automatically set LOW for this event. Wake-Up Input In addition to a wake-up via the bus lines CANH or CANL it is also possible to wake-up the application via the Wake-up input WK. Low Dropout Voltage Regulator The TLE 6262 is able to drive external 5 V loads up to typ. 100 mA. Its output voltage tolerance is less than 2%. An external reverse current protection is recommended to prevent the output capacitor from being discharged by negative transients or low input voltage. Stability of the output voltage is guaranteed for output capacitors CQ 100 nF. Nevertheless a lot of applications require a much larger output capacitance to buffer the output voltage in case of low input voltage or negative transients. Furthermore the due function of e.g. the reset and early warning circuit circuit is supported by a larger output capacitance because of their reaction times. Therefore a output capacitance CQ 10 F, ESR > 1 is recommended.
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TLE 6263 G
SPI (Serial Peripheral Interface) The 8-bit wide programming word or input word (see Table 1) is read in via the data input DI, and this is synchronised with the clock input CLK supplied by the C. The diagnosis word appears synchronously at the data output DO (see Table 2). The transmision cycle begins when the chip is selected by the chip select not input CSN (H to L). After the CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. For details of the SPI timing please refer to Figure 3 to Figure 6. Oscillator All internal delay times are referring to the internal oscillator frequency, which is set by an external resistor from pin OSC to GND. The oscillator frequency and the resulting internal cycling time can be calculated by the equations:
fOSC = 35.9 x 106 [Hz]/ROSC tCYL = 32/fOSC
Window Watchdog, Reset When the input voltage exceeds the reset threshold voltage the reset output RO is switched HIGH after a delay time of 16 cycles. This is necessary for a defined start of the microcontroller when the application is switched on. As soon as an under-voltage condition of the output voltage (VCC < VRT) appears, the reset output RO is switched LOW again. The LOW signal is guaranteed down to an output voltage VQ 1 V. Please refer to Figure 9, reset timing diagram. After the above described delayed reset (LOW to HIGH transitition of RO) the window watchdog circuit is started. Now the microcontroller has to service a watchdog trigger signal via the SPI interface (input bit 0) after a closed window of 16 cycles. A watchdog trigger is detected as a falling edge by sampling a HIGH followed by a LOW of the SPI input bit 0. If the trigger signals do not meet the open window (16 cycles) following the closed window, the reset output RO is set LOW for a periode of 4 cycles. In addition, the SPI diagnosis bit 1 is set HIGH to monitor a watchdog reset. A correct watchdog service immediately results in starting the next closed window. Please refer to Figure 8, watchdog timing diagram. Both, the undervoltage reset and the watchdog reset are setting all SPI input bits LOW. To avoid a cyclic wake-up of the microcontroller in low power mode (sleep mode) the watchdog circuit can be automatically disabled at low output currents (ICC < ICCWD). To activate this feature the SPI input bit 1 has to be set HIGH. In this under-current mode the low side switches are switched off by the TLE 6261. When the microcontroller returns
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TLE 6263 G
back to normal mode (ICC > ICCWD) the first closed window is transformed to an open window so that the total open window time is 32 cycles. This ensures a simple synchronisation of the watchdog timing to the watchdog services. Early Warning This sense comparator can e.g. be used to supervise the input voltage VS to give the microcontroller a prewarning before an undervoltage reset due to low input voltage occures. The prewarning is indicated by setting the sense out SO low. To activate this featrue, the sense out has to be set high via the SPI input bit 6. High Side Switch The high side output OUTHS is able to switch loads up to 150 mA. Its on-resistance is 1.0 typ. @ 25 C. This switch is controlled via the SPI input bits 4 and 5. In normal mode and stand-by mode the high side output is swiched on resp. off via bit 5. To supply external wake-up circuits in sleep mode the output OUTHS can be periodically switched on by the internal oscillator circuit. For activating this feature the SPI input bits 4 and 5 have be set high. The autotiming period then is 128 internal cycle times; the on-time is 2 cycles. In case of a watchdog reset the autotiming period is shortened. The SPI diagnosis bit 0 flaggs a thermal prewarning. By this the microcontroller is able to reduce the power dissipation of the TLE 6263 G by switching off functions of minor priority until the temperature threshold of the thermal shutdown is reached. Further OUTH1 is protected against short circuit and overload. As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the switch is automatically disabled by the under-voltage lockout circuit. Moreover the switch is disabled when a reset occurs. Table 1 Input Data Protocol (H = ON, L = OFF) BIT 7 6 5 4 3 2 1 0 Mask Inhibit Early Warning Enable OUTHS ON OUTHS Auto Timing Not Standby Enable Transmit Watchdog Control Watchdog Trigger
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Table 2 Diagnosis Data Protocoll (H = ON, L = OFF) Bit 7 6 5 4 3 2 1 0 CAN Failure 2 and 4 CAN Failure 1 and 3a CAN Failure 6 CAN Failure 6a CAN Failure 6a, 5 and 7 CAN Failure 3 Window Watchdog Reset Temperature Prewarning
Table 3 CAN Bus Line Failure Cases (According to ISO 11519-2) Failure # 1 2 3 3a (no ISO failure) 4 5 6 6a (no ISO failure) 7 Failure Description CANL line interrupted CANH line interrupted CANL shorted to Vbat; CANH > 7.2 V CANL shorted to Vbat; 2.2 V < CANH < 7.2 V CANH shorted to GND CANL shorted to GND CANH shorted to Vbat; CANL > 7.2 V CANH shorted to Vbat; 2.2 V < CANL < 7.2 V CANL shorted to CANH
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TLE 6263 G
Absolute Maximum Ratings Parameter Symbol Limit Values min. Voltages Supply voltage Supply voltage Regulator output voltage CAN input voltage (CANH, CANL) CAN input voltage (CANH, CANL) max. Unit Remarks
VS VS VCC VCANH/L VCANH/L
- 0.3 - 0.3 - 0.3 - 10 - 40 - 0.3
28 40 5.5 27 40
V V V V V V V V V V
-
tp< 0.5 s; tp/T < 0.1
- -
Logic input voltages (DI, CLK, VI CSN, OSC, TxD) Logic output voltage (DO, RO, SO, RxD) Termination input voltage (RTH, RTL) Input voltages at WK and SI Input voltages at WK and SI Currents Output current; VCC Output current; OUTHS Temperatures Junction temperature Storage temperature
VCC
+ 0.3
VDRSO,RD - 0.3 VTL /TH VWK/SI VWK/SI
- 0.3 - 0.3 - 0.3
VCC
+ 0.3
VS
+ 0.3 28 40
VS >0 V tp< 0.5 s; tp/T < 0.1 0 V < VS < 24 V 0 V < VCC < 5.5 V 0 V < VS < 24 V 0 V < VCC < 5.5 V 0 V < VS < 24 V 0 V < VCC < 5.5 V
-
tp< 0.5 s; tp/T < 0.1
ICC IOUTH1
- *
- 0.2
A A
internally limited * internally limited
Tj Tstg
- 40 - 50
150 150
C C
- -
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
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TLE 6263 G
Operating Range Parameter Supply voltage Supply voltage slew rate Logic input voltage (DI, CLK, CSN, TxD ) Output capacitor Symbol Limit Values min. max. V V/s V F MHz C After VS rising above VUV ON - - - Unit Remarks
VS
dVS /dt
VUV OFF 28
- 0.5 - 0.3 10 - - - 40 5
VI CCC RESR fCLK Tj
VCC
- 10 1 150
CCC-Series Resistor
SPI clock frequency Junction temperature Thermal Resistances Junction pin Junction ambient
Ta = - 40 C; f = 10 kHz
- -
Rthj-pin Rthj-a
- -
25 65
K/W K/W
measured to pin 7 -
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TLE 6263 G
Electrical Characteristics
9 V < VS < 16 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Quiescent current Pin VS Current consumption Quiescent current ISSB1 = IS - ICC Quiescent current ISSB2 = IS - ICC
IS ISSB1 ISSB2
- - -
5 - -
- 100 3
mA A mA
-
Tj = 25 C
sleep mode; VS = 12 V;
OUTHS active; sleep mode; VS = 12 V; Tj = 25 C
Voltage Regulator; Pin VCC Output voltage Output voltage Line regulation Load regulation Power supply ripple rejection Output current limt Dropvoltage VDR = VS - VCC
VCC VCC
VCC VCC
4.9 4.8 - - tbd 110 -
5.0 5.00 - - 40 - -
5.1 5.5 50 50 - - 0.5
V V mV mV dB mA V
0.1 mA < ICC < 100 mA 0 A < ICC < 100 A 6 V < VS < 16 V; ICC = 1 mA 5 mA < ICC < 100 mA; VS = 6 V
PSRR ICCmax VDR
VS < 1 VSS; CQ 10 F 100 Hz < f < 100 kHz
Note 1 ICC = 80 mA; Note 1
1) measured when the output voltage VCC has dropped 100 mV from the nominal value obtained at 13.5 V input voltage VS
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TLE 6263 G
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Oscillator; Pin OSC Adjust resistor Oscillating frequency Internal cycling time (1/32 x fOSC)-1
ROSC fOSC tCYL
51 52.8
- 70.4
680 88.0
k kHz
-
0.363 0.454 0.606 ms
ROSC = 510 k ROSC = 510 k
Reset Generator; Pin RO Reset threshold voltage Reset low output voltage Reset high output voltage Reset pull up current Reset reaction time Reset delay time (16 cyl.) Early Warning Sense In threshold voltage Sense Out high voltage Sense pull up current Sense reaction time
VRT VRO
4.0 -
4.3 0.2
4.6 0.4
V V
-
IRO = 1 mA (VCC VRT) or VCC 1 V
(IRO = 200 A) -
VRO IRO tRR tRD
4.0 20 1 5.8
- 150 3 7.3
VCC + V
0.1 500 10 10.6 A s ms
VRO = 0 V VCC < VRT to RO = L ROSC = 510 k
VST
- - 4.0 20 -
2.5 0.2 - 150 5
- 0.4 0.1
V V
VS > 3 V ISO = 1 mA (VCC VRT)
-
Sense Out low voltage VSO
VSO IRO tSR
VCC + V
500 - A s
VSO = 0 V VS < VST to SO = low
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TLE 6263 G
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Watchdog Generator Watchdog time (22 cyl.) Closed window time (16 cyl.) Open window time (16 cyl.) Watchdog reset-puls time (4 cyl.) Watchdog activating current Watchdog activating current hysteresis Long open window (32 cyl.)
tWD tCW tOW tWDR ICCWD
8.0 5.8 5.8 1.5 2
10 7.3 7.3 1.8 4
13.3 10.6 10.6 2.4 7
ms ms ms ms mA
ROSC = 510 k ROSC = 510 k ROSC = 510 k ROSC = 510 k Tj < 85 C; Watchdog OFF when ICC < ICCWD
and SPI-bit 1 = H -
ICCWDhys ICCWDhys
- 11.2
0.5 14.6
- 21.2
mA ms
ROSC = 510 k
sleep mode (WD OFF) to normal mode
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TLE 6263 G
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
High Side Output OUTHS; (Controlled by Bit 4 and Bit 5 of SPI Input Word) Static Drain-Source ON-Resistance; IOUTH3 = - 0.15 A
RDSON HS -
1.0 - 2.5 -
1.5 3.0 3.0 5.0 - 1 - 100 100
V V A s s
Tj = 25 C
- 5.2 V VS 9 V Tj = 25 C 5.2 V VS 9 V
Active zener voltage Clamp diode forward voltage Leakage current
VOUTHS VOUTHS
- -
-3 -
IOUTHS = - 0.15 A IOUTHS = 0.15 A VOUTHS = 0 V
CSN high to OUTHS CSN high to OUTHS - - -
IQLHS Switch ON delay time tdONHS Switch OFF delay time tdOFFHS Overcurrent shutdown ISDHS
threshold
- 100 - - - - -
- 0.8 - 0.4 - 0.2 A 10 - 4.50 - 29 - 25 5.35 4.85 0.5 58 1/64 40 6.00 5.20 - 87 - s V V V ms -
tdSDHS IOCLHS Current limit UV-Switch-ON voltage VUV ON VUV OFF UV-Switch-OFF
Shutdown delay time voltage UV-ON/OFFHysteresis Auto time periode (128 cyl.) Auto time ON duty cycle (2 cyl.)
- 1.2 - 0.6 - 0.3 A
VS increasing VS decreasing VUV ON - VUV OFF ROSC = 510 k; SPI-bit
4/5 = H, no WD reset refering to tPHS
VUV HY tPHS
D.C.
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TLE 6263 G
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
SPI-Interface Logic Inputs DI, CLK and CSN H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull up current at pin CSN Pull down current at pin DI and CLK Pull down current at pin CLK Input capacitance at pin CSN, DI or CLK Logic Output DO H-output voltage level L-output voltage level Tri-state leakage current Tri-state input capacitance
VIH VIL VIHY IICSN IICLK/DI IICLK CI
- 0.2 *
- - 200
0.7 *
V V mV A A A pF
- - -
VCC
- 500 -5 100 50 15
VCC
50
- 100 - 25 5 10 - 25 25 10
VCSN = 0.7 x VCC VDI = 0.2 x VCC VCLK = 0.2 x VCC
0 V < VCC < 5.25 V
VDOH VDOL IDOLK CDO
VCC - VCC - -
1.0 - - 10 - 0.7 0.2 - 10 0.4 10 15
V V A pF
IDOH = 1 mA IDOL = - 1.6 mA VCSN = VCC 0 V < VDO < VCC
VCSN = VCC 0 V < VCC < 5.25 V
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TLE 6263 G
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Data Input Timing
tpCLK tCLKH Clock high time tCLKL Clock low time Clock low before CSN tbef
Clock period low CSN setup time CLK setup time Clock low after CSN high DI setup time
1000 - 500 500 500 500 500 500 250 250 - - - - - - - - - - - -
- - - - - - - - - 200 200
ns ns ns ns ns ns ns ns ns ns ns
- - - - - - - - - - -
tlead tlag tbeh
tDISU tDIHO DI hold time Input signal rise time at trIN
pin DI, CLK and CSN Input signal fall time at tfIN pin DI, CLK and CSN Data Output Timing DO rise time DO fall time DO enable time DO disable time DO valid time
trDO tfDO tENDO tDISDO tVADO
- - - - -
50 50 - - 100
100 100 250 250 250
ns ns ns ns ns
CL = 100 pF CL = 100 pF low impedance high impedance
VDO < 0.1 VCC; VDO > 0.9 VCC; CL = 100 pF
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Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Thermal Prewarning and Shutdown (Junction Temperatures) Thermal prewarning ON temperature Thermal prewarning hyst. Thermal shutdown temp. Thermal switch-on temp. Thermal shutdown hyst. Ratio of SD to PW temp.
TjPW
T
120 - 150 120 - 1.05
145 30 175 - 30 1.20
170 - 200 170 - -
C K C C K -
bit 0 of SPI diagnosis word - - - - -
TjSD TjSO
T
TjSD/TjPW
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TLE 6263 G
Timing Diagrams
0.7 VCC CSN 0.2 VCC
t CLKH
0.7 VCC CLK 0.2 VCC
t lead t bef
t DISU
t CLKL t DIHO
Don't Care
t lag t beh
0.7 VCC Valid Don't Care 0.2VCC
AET02178
DI
Don't Care
Valid
Figure 3 SPI-Input Timing
t rIN t fIN
90% CSN 50% 10%
t dOFF
90% Case 1 OUT ON State OFF State 50% 10%
t OFF t dON t ON
90% Case 2 OUT OFF State ON State 50% 10%
AET02179
Figure 4 Turn OFF/ON Time
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TLE 6263 G
t rIN
_ t fIN < 10 ns
0.9 VCC CLK 50% 0.1VCC
t rDO
0.9 VCC DO (low to high) 0.1VCC
t VADO t fDO
0.9 VCC (high to low) 0.1VCC
AET02180
DO
Figure 5 DO Valid Data Delay Time and Valid Time
t fIN
_ t rIN < 10 ns
0.9 VCC CSN 50% 0.1VCC
t ENDO
t DISDO
10 k Pullup to VCC
DO
50%
t ENDO
t DISDO
10 k Pulldown to GND
DO
50%
AET02181
Figure 6 DO Enable and Disable Time
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t WD t CW
Closed Window
t OW
Open Window
Condition: t OSC = 70.4 kHz
8
10
ms
13.3
t
AED02575
Figure 7 Watchdog Timeout Definitions
t OW
WD Trigger
t OW t CW t OW t CW t CW + t OW t CW + t OW t CW
t CW t CW t OW t CW t CW
t OW
t
Reset Out
t WDR
t
Watchdog Timer Reset Normal Operation Timeout (to long) Normal Operation Timeout (to short) Normal Operation
AET02576
Figure 8 Watchdog Timing Diagram
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TLE 6263 G
VCC VRT t < t RR t t OW t CW
WD Trigger
t CW + t OW t RD t CW
t OW t RD
t CW + t OW
t
Reset Out
t WDR
t RR
t
Watchdog Timer Reset Start Up Undervoltage Normal Operation
AET02577
Start Up
Figure 9 Reset Timing Diagram
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Application
Vbat
CAN bus
e.g. C505C, C164C CANH CANL RxD TxD CSN RTH RTL SI 10 k 100 nF OUTHS 1 k 10 k WK + VS 68 F 100 nF GND TLE 6263 CLK DO DI SO RO
1 k 16 k
P
VCC
OSC 510 k
AES02578
22 F
GND
Figure 10 Application Circuit
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Package Outlines P-DSO-28-6 (Plastic Dual Small Outline)
2.65 max
0.35 x 45
+0.09
2.45 -0.2
0.2 -0.1
1.27 0.35 +0.15 2) 0.2 28x 28 15 0.1
0.4 +0.8 10.3 0.3
1 Index Marking
18.1 -0.4 1)
14
1) Does not include plastic or metal protrusions of 0.15 max rer side 2) Does not include dambar protrusion of 0.05 max per side
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 24
0.23
GPS05123
Dimensions in mm 1998-11-01
8 ma
x
7.6 -0.2 1)

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