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ST7LITEUSx
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, TIMERS
PRELIMINARY DATA

Memories - 1K bytes single voltage Flash Program memory with read-out protection, In-Circuit and InApplication Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55C. - 128 bytes RAM. Clock, Reset and Supply Management - 3-level low voltage supervisor (LVD) and auxiliary voltage detector (AVD) for safe poweron/off procedures - Clock sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock - Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow Interrupt Management - 11 interrupt vectors plus TRAP and RESET - 5 external interrupt lines (on 5 vectors) I/O Ports - 5 multifunctional bidirectional I/O lines - 1 additional Output line - 6 alternate function lines - 5 high sink outputs 2 Timers - One 8-bit Lite Timer (LT) with prescaler including: watchdog, 1 realtime base and one 8-bit input capture. - One 12-bit Auto-reload Timer (AT) with output compare function and PWM
DIP8
SO8 150"
DFN8
A/D Converter - 10-bit resolution for 0 to VDD - 5 input channels Instruction Set - 8-bit data manipulation - 63 basic instructions with illegal opcode detection - 17 main addressing modes - 8 x 8 unsigned multiply instruction Development Tools - Full hardware/software development package - Debug Module
Device Summary
Features Program memory - bytes RAM (stack) - bytes Peripherals ADC Operating Supply CPU Frequency Operating Temperature Packages ST7ULTRALITE ST7LITEUS2 ST7LITEUS5 1K 128 (64) LT Timer w/ Wdg, AT Timer w/ 1 PWM 10-bit 2.4V to 3.3V @fCPU=4MHz, 3.3V to 5.5V @fCPU=8MHz up to 8MHz RC -40C to +85C SO8 150", DIP8, DFN8, DIP161)
Note 1: For development or tool prototyping purposes only. Not orderable in production quantities.
Rev. 1
February 2006 1/101
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1
Table of Contents
ST7LITEUSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.5 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.3 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.6 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101. 45 ... 10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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10.1 LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.3 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.1010-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 95 14.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 15 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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1 INTRODUCTION
The ST7ULTRALITE is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7ULTRALITE features FLASH memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming (IAP) capability. Under software control, the ST7ULTRALITE device can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to Figure 1. General Block Diagram
Internal Clock
software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in section 12 on page 68. The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
AWU RC OSC
8 MHz.RC OSC
External Clock LVD VDD VSS PA3 / RESET POWER SUPPLY
ADDRESS AND DATA BUS
LITE TIMER w/ WATCHDOG PORT A 12-BIT AUTORELOAD TIMER
CONTROL 8-BIT CORE ALU 1K Bytes FLASH MEMORY
PA5:0 (6 bits)
10-BIT ADC
RAM (128 Bytes)
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2 PIN DESCRIPTION
Figure 2. 8-pin SO and DIP Package Pinout
VDD PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3 PA3 / RESET
1 2 ei4 3 ei3 4
8 ei0 7 ei1 6 ei2 5
VSS PA0 (HS) / AIN0 / ATPWM / ICCDATA PA1 (HS) / AIN1 / ICCCLK PA2 (HS) / LTIC / AIN2
(HS) : High sink capability eix : associated external interrupt vector
Figure 3. 8-pin DFN Package Pinout
VDD PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3 PA3 / RESET
1 2 ei4 3 ei3 4
8 ei0 7 ei1 6 ei2 5
VSS PA0 (HS) / AIN0 / ATPWM / ICCDATA PA1 (HS) / AIN1 / ICCCLK PA2 (HS) / LTIC / AIN2
(HS) : High sink capability eix : associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Figure 4. 16-Pin Package Pinout (For development or tool prototyping purposes only. Package not orderable in production quantities.)
Reserved 1) VDD RESET ICCCLK PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3
1 2 3 4 5 ei4 6 ei3
16 15 ei0 14 ei1 13 12 11 ei2 10 9
NC VSS PA0 (HS) / AIN0 / ATPWM PA1 (HS) / AIN1 NC ICCDATA PA2 (HS) / LTIC / AIN2 NC
PA3 NC
7 8
Note 1: must be tied to ground
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level:CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = High sink (on N-buffer only) Port and control configuration: - Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog - Output: OD = open drain, PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 1. Device Pin Description
Level float Pin Name Output Input Pin No. 1 2 3 4 5 Type Port / Control Main Input Output Function (after reset) ana OD PP int Main power supply X X X X ei2 X ei4 ei3 X X X X X X X X X X Port A5 Port A4 Port A3 Port A2 Analog input 4 or External Clock Input Analog input 3 RESET 1) Analog input 2 or Lite Timer Input Capture Analog input 1 or In Circuit Communication Clock Caution: During normal operation this pin must be pulled-up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in pull-up Analog input 0 or Auto-Reload Timer PWM or In Circuit Communication Data
VDD PA5/AIN4/ CLKIN PA4/AIN3 PA3/RESET
1)
S I/O CT HS I/O CT HS O
PA2/AIN2/LTIC I/O CT HS
6
PA1/AIN1/ ICCCLK
I/O CT HS
X
wpu
Alternate Function
ei1
X
X
X
Port A1
7 8
PA0/AIN0/ATPI/O CT HS WM/ICCDATA VSS S
X
ei0
X
X
X
Port A0 Ground
Note 1: After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1. For further details, please refer to section 6.4 on page 24.
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3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbytes of user program memory. The RAM space includes up to 64 bytes for the stack from 00C0h to 00FFh. The highest address bytes contain the user reset and interrupt vectors. Figure 5. Memory Map The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (FE00h-FFFFh). The size of Flash Sector 0 and other device options are configurable by Option byte. IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device.
0000h 007Fh 0080h
HW Registers
0080h
(see Table 2)
00C0h
Short Addressing RAM (zero page) 64 Bytes Stack
00FFh
RAM (128 Bytes)
00FFh 0100h
DEE0h DEE1h
RCCRH1 RCCRL1 RCCRH0 RCCRL0
Reserved
DEE2h 1K FLASH PROGRAM MEMORY DEE3h
FBFFh FC00h
see section 6.1 on page 17
FC00h FDFFh FE00h 0.5 kbytes SECTOR 1 0.5 kbytes SECTOR 0
Flash Memory (1K)
FFDFh FFE0h
FFFFh
Interrupt & Reset Vectors
(see Table 7)
FFFFh
1. DEE0h, DEE1h, DEE2h and DEE3h addressesare located in a reserved area butare special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibration values locations) has been erased (after the read out protection removal), then the RC calibration values can still be obtained throughthese addresses.
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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h to 0016h 0017h 0018h 0019h to 002Eh 0002Fh 0030h to 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh to 003Ch 003Dh 003Eh 003Fh 0040h to 0046h ITC AVD Clock controller EICR2 AVDTHCR CKCNTCSR ADC ITC MCC Clock and Reset ADCCSR ADCDRH ADCDRL EICR1 MCCSR RCCR SICSR FLASH FCSR AUTORELOAD TIMER DCR0H DCR0L LITE TIMER LTCSR LTICR ATCSR CNTRH CNTRL ATRH ATRL PWMCR PWM0CSR Block Register Label PADR PADDR PAOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved area (8 bytes) Lite Timer Control/Status Register Lite Timer Input Capture Register Timer Control/Status Register Counter Register High Counter Register Low Auto-Reload Register High Auto-Reload Register Low PWM Output Control Register PWM 0 Control/Status Register Reserved area (3 bytes) PWM 0 Duty Cycle Register High PWM 0 Duty Cycle Register Low Reserved area (22 bytes) Flash Control/Status Register Reserved area (4 bytes) A/D Control Status Register A/D Data Register High A/D Data Register Low External Interrupt Control Register 1 Main Clock Control/Status Register RC oscillator Control Register System Integrity Control/Status Register Reserved area (2 bytes) External Interrupt Control Register 2 AVD Threshold Selection Register Clock Controller Control/Status Register Reserved area (7 bytes) 00h 03h 09h R/W R/W R/W 00h xxh 00h 00h 00h FFh 0000 0x00h R/W Read Only R/W R/W R/W R/W R/W 00h R/W 00h 00h R/W R/W 0xh 00h 00h 00h 00h 00h 00h 00h 00h R/W Read Only R/W Read Only Read Only R/W R/W R/W R/W Reset Status 00h 1) 08h 02h 2) Remarks R/W R/W R/W
Port A
AUTORELOAD TIMER
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Address 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h to 007Fh
Block MuxIOreset AWU
Register Label MUXCR0 MUXCR1 AWUPR AWUCSR DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L
Register Name Mux IO-Reset Control Register 0 Mux IO-Reset Control Register 1 AWU Prescaler Register AWU Control/Status Register DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low Reserved area (47 bytes)
Reset Status 00h 00h FFh 00h 00h 00h 00h 00h 00h 00h
Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DM 3)
Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the DM registers, see the ST7 ICC Reference Manual.
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features

ICP (In-Circuit Programming) IAP (In-Application Programming) ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Sector 0 size configurable by option byte Read-out and write protection
4.3 PROGRAMMING MODES The ST7 can be programmed in three different ways: - Insertion in a programming tool. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased. - In-Circuit Programming. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board. - In-Application Programming. In this mode, sector 1 can be programmed or erased without removing the device from the application board and while the application is running.
4.3.1 In-Circuit Programming (ICP) ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. - Download ICP Driver code in RAM from the ICCDATA pin - Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
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FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC interface ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are: - RESET: device reset - VSS: device power supply ground Figure 6. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 4) APPLICATION BOARD
- ICCCLK: ICC output serial clock pin (see note 5) - ICCDATA: ICC input serial data pin - CLKIN: main clock input for external source - VDD: application board power supply (see Note 3)
(See Note 3)
9 10
7 8
5 6
3 4
1 2
APPLICATION RESET SOURCE 3.3k (See Note 6) APPLICATION POWER SUPPLY See Note 2
See Note 1 and Caution See Note 1 CLKIN RESET ICCDATA ICCCLK VDD
APPLICATION I/O
ST7
Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up re-
sistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the CLKIN pin of the ST7 when ICC mode is selected with option bytes disabled (35-pulse ICC entry mode). 5. When option bytes are enabled (38-pulse ICC entry mode), the internal RC clock (3% RC or AWU RC) is forced. If 3% RC is selected in the option byte, the 3% RC is provided. If AWU RC or external clock is selected, the AWU RC oscillator is provided.
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FLASH PROGRAM MEMORY (Cont'd) 6. A serial resistor must be connected to ICC connector pin 6 in order to prevent contention on PA3/ RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin forces the opposite state in output mode. The resistor value is defined to limit the current below 2mA at 5V. If PA3 is used as output push-pull, then the application must be switched off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to drive the RESET pin below VIL, special care must also be taken when a pull-up is placed on PA3 for application reasons. Caution: During normal operation, ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. 4.5 Memory Protection There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read out Protection Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Program memory is protected. In flash devices, this protection is removed by reprogramming the option. In this case, program memory is automatically erased, and the device can be reprogrammed. Read-out protection selection depends on the device type: - In Flash devices it is enabled and removed through the FMP_R bit in the option byte. - In ROM devices it is enabled by mask option specified in the Option List.
4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.7 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)
7 0 0 0 0 0 OPT LAT 0 PGM
Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations. When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.
Table 3. FLASH Register Map and Reset Values
Address (Hex.) 002Fh Register Label FCSR Reset Value 0 0 0 0 0 7 6 5 4 3 2 OPT 0 1 LAT 0 0 PGM 0
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES

63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
5.3 CPU REGISTERS The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Figure 7. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable
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CPU REGISTERS (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 00 FFh
15 0 7
1 1 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 0 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address. Figure 8. . Stack Manipulation Example
CALL Subroutine @ 00C0h Interrupt event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 00FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 00FFh Stack Lower Address = 00C0h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. Main features Clock Management - 8 MHz internal RC oscillator (enabled by option byte) - External Clock Input (enabled by option byte) Reset Sequence Manager (RSM) System Integrity Management (SI) - Main supply Low voltage detection (LVD) with reset generation (enabled by option byte) - Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply 6.1 INTERNAL RC OSCILLATOR ADJUSTMENT The ST7 contains an internal RC oscillator with an accuracy of 3% for a given device, temperature and voltage. It can be selected as the start up clock through the CKSEL[1:0] option bits (see section 14.1 on page 95). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 8-bit calibration value in the RCCR (RC Control Register) and in the bits [6:5] in the SICSR (SI Control Status Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in Flash memory for 3.0 and 5V VDD supply voltages at 25C, as shown in the following table.
ST7LITEUS2/ ST7LITEUS5 Address DEE0h 1) (CR[9:2] bits) DEE1h 1) (CR[1:0] bits) DEE2h 1) (CR[9:2] bits) DEE3h 1) (CR[1:0] bits)
Notes: - In ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Refer to note 5 in section 4.4 on page 12 for further details. - See "ELECTRICAL CHARACTERISTICS" on page 68. for more information on the frequency and accuracy of the RC oscillator. - To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal. The ST7ULTRALITE also contains an Auto Wake Up RC oscillator. This RC oscillator should be enabled to enter Auto Wake-up from Halt mode. The Auto Wake Up RC oscillator can also be configured as the startup clock through the CKSEL[1:0] option bits (see section 14.1 on page 95). This is recommended for applications where very low power consumption is required. Switching from one startup clock to another can be done in run mode as follows (see Figure 9): Case 1: Switching from 3% RC to AWU: - 1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator - 2. The RC_FLAG is cleared and the clock output is at 1. - 3. Wait 3 AWU RC cycles till the AWU_FLAG is set - 4. The switch to the AWU clock is made at the positive edge of the AWU clock signal - 5. Once the switch is made, the 3% RC is stopped Case 2: Switching from AWU RC to 3% RC: - 1. Reset the RC/AWU bit to enable the 3%RC oscillator - 2. Using a 4-bit counter, wait until 8 3% RC cycles have elapsed. The counter is running on 3% RC clock.
RCCR RCCRH0 RCCRL0 RCCRH1 RCCRL1
Conditions VDD=5V TA=25C fRC=8MHz VDD=3.0V TA=25C fRC=8MHz
1. DEE0h, DEE1h, DEE2h and DEE3h are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the Flash space (including the RC calibration value locations) has been erased (after the read out protection removal), then the RC calibration values can still be obtained through these two address.
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SUPPLY, RESET AND CLOCK MANAGEMENT (Cont'd) - 5. Once the switch is made, the AWU RC is - 3. Wait till the AWU_FLAG is cleared (1AWU RC stopped cycle) and the RC_FLAG is set (2 RC cycles) - 4. The switch to the 3%RC clock is made at the positive edge of the 3% RC clock signal Figure 9. Clock Switching
3% RC Set RC/AWU Poll AWU_FLAG until set AWU RC
AWU RC
Reset RC/AWU Poll RC_FLAG until set
3% RC
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6.2 REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 SMS
00h = maximum available frequency FFh = lowest available frequency Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h. SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0000 0x00 (0xh)
7 0 CR1 CR0 0 0 LVDR F AVD F 0 AVDI E
Bits 7:1 = Reserved, must be kept cleared. Bit 0 = SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32. 0: Normal mode (fCPU = fOSC 1: Slow mode (fCPU = fOSC/32)
Bit 7 = Reserved, must be kept cleared. RC CONTROL REGISTER (RCCR) Read / Write Reset Value: 1111 1111 (FFh)
7 CR9 CR8 CR7 CR6 CR5 CR4 CR3 0 CR2
Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment Bits These bits, as well as CR[1:0] bits in the SICSR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 3%. The application can store the correct value for each voltage range in Flash memory and write it to this register at start-up.
Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 3%. Refer to section 6.1 on page 17. Bits 4:3 = Reserved, must be kept cleared. Bits 2:0 = System Integrity bits. Refer to Section 7.4 SYSTEM INTEGRITY MANAGEMENT (SI).
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REGISTER DESCRIPTION (Cont'd) AVD THRESHOLD SELECTION REGISTER (AVDTHCR) Read/Write Reset Value: 0000 0011 (03h)
7 0 CK1 CK0 0 0 0 0 0 AVD1 AVD0 0 0 0
CLOCK CONTROLLER CONTROL/STATUS REGISTER (CKCNTCSR) Read/Write Reset Value: 0000 1001 (09h)
7 AWU_ FLAG RC_ FLAG 0 0 RC/ AWU
Bit 7:4 = Reserved, must be kept cleared. Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CK[1:0] 3% RC Prescaler Selection These bits are set by software and cleared by hardware after a reset. These bits select the prescaler of the 3% RC oscillator. See Figure 10 and the following table and note: Table 4. 3% RC Prescaler Selection bits
CK1 CK0 0 0 1 1 0 1 0 1 fOSC fRC fRC/2 fRC/4 fRC/8
Bit 3 = AWU_FLAG AWU Selection This bit is set and cleared by hardware 0: No switch from AWU to RC requested 1: AWU clock activated and temporization completed
Bit 2 = RC_FLAG RC Selection This bit is set and cleared by hardware 0: No switch from RC to AWU requested 1: RC clock activated and temporization completed Bit 0 = RC/AWU RC/AWU Selection 0: RC enabled 1: AWU enabled (default value)
Note: If the internal RC is used with a supply operating range below 3.3V, a division ratio of at least 2 must be enabled in the RC prescaler. Bits 4:2 = Reserved, must be kept cleared. Bits 1:0 = AVD Threshold Selection bits. Refer to Section 7.4 SYSTEM INTEGRITY MANAGEMENT (SI). Table 5. Clock Register Map and Reset Values
Address (Hex.) 0038h 0039h 003Ah 003Eh 003Fh Register Label MCCSR Reset Value RCCR Reset Value SICSR Reset Value AVDTHCR Reset Value CKCNTCSR Reset Value 0 CR7 1 0 0 0 0 CR6 1 CR1 CK1 0 0 0 CR5 1 CR0 CK0 0 0 7 6 5
4
3
2
1
0 SMS 0 CR0 1 AVDIE 0 AVD2 1 RC/AWU 1
0 CR4 1 0 0 0
0 CR3 1 0 0
0 CR2 1 LVDRF x 0
0 CR1 1 AVDF 0 AVD1 1 0
AWU_FLAG RC_FLAG 1 0
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Figure 10. Clock Management Block Diagram
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2
RCCR SICSR
CR1
CR0
Tunable 3% RC Oscillator 8MHz(fRC) Prescaler
8MHz 4MHz 2MHz 1MHz
Clock Controller RC OSC AWU CK fOSC Ext Clock
AWU RC
33kHz
CKSEL[1:0] Option bits
CLKIN
fCLKIN
/2 DIVIDER
13-BIT LITE TIMER COUNTER fOSC fOSC 0
fLTIMER (1ms timebase @ 8 MHz fOSC)
fCPU TO CPU AND PERIPHERALS
/32 DIVIDER
fOSC/32
1
SMS MCCSR
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6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 12: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Figure 12. These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. Figure 11. RESET Sequence Phases The basic RESET sequence consists of 3 phases as shown in Figure 11: Active Phase depending on the RESET source 64 CPU clock cycle delay RESET vector fetch The 64 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles.
RESET
Active Phase INTERNAL RESET 64 CLOCK CYCLES FETCH VECTOR
Figure 12. Reset Block Diagram
VDD
RON
RESET
FILTER INTERNAL RESET
WATCHDOG RESET PULSE GENERATOR ILLEGAL OPCODE RESET 1) LVD RESET
Note 1: See "Illegal Opcode Reset" on page 65. for more details on illegal opcode reset conditions.
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RESET SEQUENCE MANAGER (Cont'd) 6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.3.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fCLKIN frequency. Figure 13. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.3.4 Internal Low Voltage Detector (LVD) RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDDLVD RESET
EXTERNAL RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (64 TCPU) VECTOR FETCH
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6.4 REGISTER DESCRIPTION MULTIPLEXED IO RESET CONTROL REGISTER 1 (MUXCR1) Read / Write once only Reset Value: 0000 0000 (00h)
7 MIR1 MIR1 MIR1 MIR1 MIR1 MIR1 MIR 5 4 3 2 1 0 9 0 MIR 8
MULTIPLEXED IO RESET CONTROL REGISTER 0 (MUXCR0) Read / Write once only Reset Value: 0000 0000 (00h)
7 0
MIR7 MIR6 MIR5 MIR4 MIR3 MIR2 MIR1 MIR0
Bits 15:0 = MIR[15:0]
This 16-bit register is read/write by software but can be written only once between two reset events. It is cleared by hardware after a reset; When both MUXCR0 and MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1. These registers are one-time writable only. - To configure PA3 as general purpose output: After power-on / reset, the application program has to configure the I/O port by writing to these registers as described above. Once the pin is configured as an I/O output, it cannot be changed back to a reset pin by the application code. - To configure PA3 as RESET: An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear the two registers and the pin will act again as a reset function. Otherwise, a power-down is required to put the pin back in reset configuration.
Table 6. XIO Register Map and Reset Values
Address (Hex.) 0047h 0048h Register Label MUXCR0 Reset Value MUXCR1 Reset Value 7 MIR7 0 MIR15 0 6 MIR6 0 MIR14 0 5 MIR5 0 MIR13 0 4 MIR4 0 MIR12 0 3 MIR3 0 MIR11 0 2 MIR2 0 MIR10 0 1 MIR1 0 MIR9 0 0 MIR0 0 MIR8 0
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7 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 14. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - The I bit of the CC register is set to prevent additional interrupts. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 7.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 14. 7.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. 7.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: - The I bit of the CC register is cleared. - The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: - Writing "0" to the corresponding bit in the status register or - Access to the status register while the flag is set followed by a read or write of an associated register. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) Figure 14. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N
N
INTERRUPT PENDING? Y
FETCH NEXT INSTRUCTION
N
IRET? Y
STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
Table 7. Interrupt Mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 2) 7 8 9 10 11 12 LITE TIMER ei3 ei4 2) SI AT TIMER AWU ei0 ei1 ei2 Reset Software Interrupt Auto Wakeup Interrupt External Interrupt 0 External Interrupt 1 External Interrupt 2 Not used External Interrupt 3 External Interrupt 4 2) AVD interrupt AT TIMER Output Compare Interrupt AT TIMER Overflow Interrupt LITE TIMER Input Capture Interrupt LITE TIMER RTC1 Interrupt Not used SICSR PWMxCSR or ATCSR ATCSR LTCSR LTCSR Lowest Priority N/A yes no yes no 2) no no yes no yes 3) no no
3)
Description
Register Label N/A AWUCSR
Priority Order Highest Priority
Exit from HALT yes no yes 1)
Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
13 Not used Notes: 1. This interrupt exits the MCU from "Auto Wake-up from HALT" mode only. 2. This interrupt exits the MCU from "WAIT" and "ACTIVE-HALT" modes only. 3. These interrupts exit the MCU from "ACTIVE-HALT" mode only.
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INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER 1 (EICR1) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 IS21 IS20 IS11 IS10 IS01 0 IS00
EXTERNAL INTERRUPT CONTROL REGISTER 2 (EICR2) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 IS41 IS40 IS31 0 IS30
Bits 7:6 = Reserved Bits 5:4 = IS2[1:0] ei2 sensitivity These bits define the interrupt sensitivity for ei2 according to Table 8. Bits 3:2 = IS1[1:0] ei1 sensitivity These bits define the interrupt sensitivity for ei1 according to Table 8. Bits 1:0 = IS0[1:0] ei0 sensitivity These bits define the interrupt sensitivity for ei0 according to Table 8. Note: These 8 bits can be written only when the I bit in the CC register is set. Table 8. Interrupt Sensitivity Bits
ISx1 ISx0 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Bits 7:4 = Reserved Bits 3:2 = IS4[1:0] ei4 sensitivity These bits define the interrupt sensitivity for ei1 according to Table 8. Bits 1:0 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei0 according to Table 8. Note: These 8 bits can be written only when the I bit in the CC register is set.
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7.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 11.2.1 on page 65 for further details. 7.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VIT+(LVD) when VDD is rising - VIT-(LVD) when VDD is falling The LVD function is illustrated in Figure 15. The voltage threshold can be configured by option byte to be low, medium or high. See section 14.1 on page 95. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: Figure 15. Low Voltage Detector vs Reset
VDD
- under full software control - in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD is an optional function which can be selected by option byte. See section 14.1 on page 95. It allows the device to be used without any external RESET circuitry. If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. Note: Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to section 12.3.2 on page 71 and section 12.3.3 on page 71 for more details. Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will clear the watchdog flag.
Vhys VIT+(LVD) VIT-(LVD)
RESET
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Figure 16. Reset and Supply Management Block Diagram
WATCHDOG TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) SICSR 0 7 1 1 0 0 LVD AVD AVD RF F IE 0 AVD Interrupt Request
LOW VOLTAGE VSS VDD DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD) reference value for falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.
7.4.2.1 Monitoring the VDD Main Supply. The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register. If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(LVD) or VIT-(AVD) threshold (AVDF bit is set). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 17. The interrupt on the rising edge is used to inform the application that the VDD warning state is over Note: Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to section 12.3.2 on page 71 and section 12.3.3 on page 71 for more details.
Figure 17. Using the AVD to Monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset)
Vhyst
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
AVDF bit AVD INTERRUPT REQUEST IF AVDIE bit = 1
0
1
RESET
1
0
INTERRUPT Cleared by reset
INTERRUPT Cleared by hardware
LVD RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.4.3 Low Power Modes
Mode WAIT HALT Description No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen. The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode.
set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event AVD event Enable Event Control Flag Bit AVDF AVDIE Exit from Wait Yes Exit from Halt No
7.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0000 0x00 (0xh)
7 0 CR1 CR0 0 0 LVDR F AVD F 0 AVDI E
0: AVD interrupt disabled 1: AVD interrupt enabled AVD THRESHOLD SELECTION REGISTER (AVDTHCR) Read/Write Reset Value: 0000 0011 (03h)
7 0 CK1 CK0 0 0 0 0 AVD1 AVD0
Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 3%. Refer to section 6.1 on page 17. Bits 4:3 = Reserved, must be kept cleared. Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description in Section 10.1 for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bit 1 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit is set. Refer to Figure 17 for additional details 0: VDD over AVD threshold 1: VDD under AVD threshold Bit 0 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine.
Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CK[1:0] 3% RC Prescaler Selection Refer to Section 6.1 INTERNAL RC OSCILLATOR ADJUSTMENT on page 17. Bits 4:2 = Reserved, must be kept cleared. Bits 1:0 = AVD[1:0] AVD Threshold Selection These bits are set and cleared by software and cleared by hardware after a reset. They select the AVD threshold. Table 9. AVD Threshold Selection bits
AVD1 AVD0 0 0 1 1 0 1 0 1 Functionality Low Medium High AVD off
Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
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REGISTER DESCRIPTION (Cont'd) Table 10. System Integrity Register Map and Reset Values
Address (Hex.) 003Ah 003Eh Register Label SICSR Reset Value AVDTHCR Reset Value 7 6 5 4 3 2 LVDRF x 0 1 AVDF 0 AVD1 1 0 AVDIE 0 AVD2 1
0 0
1 CK1 0
1 CK0 0
0 0
0 0
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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 18): Slow Wait (and Slow-Wait) Active Halt Auto Wake up From Halt (AWUFH) Halt After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (fOSC). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 18. Power Saving Mode Transitions
High
fOSC
8.2 SLOW MODE This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode. In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency. Notes: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode. Figure 19. SLOW Mode Clock Transition
fOSC/32 fCPU fOSC
RUN SLOW WAIT SLOW WAIT ACTIVE HALT HALT Low POWER CONSUMPTION
SMS
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 20. Figure 20. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CPU I BIT ON ON OFF 0
WFI INSTRUCTION
N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON 0 Y
64 CPU CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS CPU I BIT
ON ON ON X 1)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the LTCSR/ATCSR register status as shown in the following table:.
ATCSR LTCSR ATCSR ATCSR OVFIE TBIE bit CK1 bit CK0 bit bit 0 0 0 1 x x 0 1 x 1 x x 1 x 0 0 x 1 x 1 ACTIVE-HALT mode enabled HALT INSTRUCTION (Active Halt enabled) ACTIVE-HALT mode disabled Meaning
Figure 21. ACTIVE-HALT Timing Overview
RUN ACTIVE HALT 64 CPU CYCLE DELAY 1) RESET OR INTERRUPT RUN
HALT INSTRUCTION [Active Halt Enabled]
FETCH VECTOR
Figure 22. ACTIVE-HALT Mode Flow-chart
OSCILLATOR ON PERIPHERALS 2) OFF CPU OFF I BIT 0
8.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when active halt mode is enabled. The MCU can exit ACTIVE-HALT mode on reception of a Lite Timer / AT Timer interrupt or a RESET. - When exiting ACTIVE-HALT mode by means of a RESET, a 64 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 22). - When exiting ACTIVE-HALT mode by means of an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see Figure 22). When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). Caution: As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET if the WDGHALT bit is reset. This means that the device cannot spend more than a defined delay in this power saving mode.
N RESET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS 2) OFF CPU ON I BIT X 4) 64 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BITS ON ON ON X 4)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from ACTIVE-HALT mode. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when active halt mode is disabled. The MCU can exit HALT mode on reception of either a specific interrupt (see Table 7, "Interrupt Mapping," on page 26) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 64 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see section 14.1 on page 95 for more details). Figure 23. HALT Timing Overview
64 CPU CYCLE DELAY RESET OR INTERRUPT FETCH VECTOR
Figure 24. HALT Mode Flow-chart
HALT INSTRUCTION (Active Halt disabled) ENABLE WDGHALT 1) 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF I BIT 0 N RESET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON X 4) 0 WATCHDOG DISABLE
64 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BITS ON ON ON X 4)
RUN
HALT
RUN
FETCH RESET VECTOR OR SERVICE INTERRUPT
HALT INSTRUCTION [Active Halt disabled]
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 7, "Interrupt Mapping," on page 26 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 5. Switch the CPU clock to 1MHz (RC/8) or AWU RC before entering HALT mode.
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POWER SAVING MODES (Cont'd) 8.4.2.1 HALT Mode Recommendations - Make sure that an external event is available to wake up the microcontroller from Halt mode. - When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. - For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. - The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. - As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set. Figure 25. AWUFH Mode Block Diagram AWU RC oscillator fAWU_RC to 8-bit Timer input capture
/64 divider
AWUFH prescaler/1 .. 255
AWUFH interrupt (ei0 source
8.5 AUTO WAKE UP FROM HALT MODE Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wake-up (Auto Wake Up from Halt Oscillator). Compared to ACTIVE-HALT mode, AWUFH has lower power consumption (the main clock is not kept running, but there is no accurate realtime clock available.
As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set by hardware and an interrupt wakes-up the MCU from Halt mode. At the same time the main oscillator is immediately turned on and a 64 cycle delay is used to stabilize it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register. To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency fAWU_RC and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects fAWU_RC to the input capture of the 8-bit lite timer, allowing the fAWU_RC to be measured using the main oscillator clock as a reference timebase.
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POWER SAVING MODES (Cont'd) Similarities with Halt mode The following AWUFH mode behaviour is the same as normal Halt mode: - The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a reset (see Section 8.4 ACTIVE-HALT AND HALT MODES). - When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. Figure 26. AWUF Halt Timing Diagram tAWU RUN MODE
fCPU fAWU_RC
- In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator). - The compatibility of Watchdog operation with AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET.
HALT MODE
64 tCPU
RUN MODE
Clear by software
AWUFH interrupt
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Figure 27. AWUFH Mode Flow-chart
HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE WDGHALT 1) 1 WATCHDOG RESET AWU RC OSC ON MAIN OSC OFF PERIPHERALS 2) OFF CPU OFF I[1:0] BITS 10 0 WATCHDOG DISABLE
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 7, "Interrupt Mapping," on page 26 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
N RESET N Y INTERRUPT 3) Y AWU RC OSC OFF MAIN OSC ON PERIPHERALS OFF CPU ON I[1:0] BITS XX 4) 64 CPU CLOCK CYCLE DELAY AWU RC OSC OFF MAIN OSC ON PERIPHERALS ON CPU ON I[1:0] BITS XX 4) FETCH RESET VECTOR OR SERVICE INTERRUPT
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POWER SAVING MODES (Cont'd) 8.5.0.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 AWU AWU AWU F M EN
AWUFH PRESCALER REGISTER (AWUPR) Read/Write Reset Value: 1111 1111 (FFh)
7 0
AWU AWU AWU AWU AWU AWU AWU AWU PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Bits 7:3 = Reserved. Bit 1= AWUF Auto Wake Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value. 0: No AWU interrupt occurred 1: AWU interrupt occurred Bit 1= AWUM Auto Wake Up Measurement This bit enables the AWU RC oscillator and connects its output to the input capture of the 8-bit lite timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPRE register. 0: Measurement disabled 1: Measurement enabled Bit 0 = AWUEN Auto Wake Up From Halt Enabled This bit enables the Auto Wake Up From Halt feature: once HALT mode is entered, the AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software. 0: AWUFH (Auto Wake Up From Halt) mode disabled 1: AWUFH (Auto Wake Up From Halt) mode enabled Note: whatever the clock source, this bit should be set to enable the AWUFH mode once the HALT instruction has been executed. Table 11. AWU Register Map and Reset Values
Address (Hex.) 0049h 004Ah
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler These 8 bits define the AWUPR Dividing factor (as explained below:
AWUPR[7:0] 00h 01h ... FEh FFh Dividing factor Forbidden 1 ... 254 255
In AWU mode, the period that the MCU stays in Halt Mode (tAWU in Figure 26) is defined by
t
AWU
1 = 64 x AWUPR x ------------------------- + t RCSTRT f AWURC
This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically. Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction, or the AWUPR remains unchanged.
Register 7 6 5 4 3 2 1 0 Label AWUPR AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0 Reset Value 1 1 1 1 1 1 1 1 AWUCSR 0 0 0 0 0 AWUF AWUM AWUEN Reset Value
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9 I/O PORTS
9.1 INTRODUCTION The I/O port offers different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - external interrupt generation - alternate signal input/output for the on-chip peripherals. An I/O port contains up to 6 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and one optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 28 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. PA3 cannot be configured as input. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified. 9.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VSS VDD Open-drain Vss Floating
Note: When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming under the following conditions: - When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). - When the signal is going to an on-chip peripheral, the I/O pin must be configured in floating input mode. In this case, the pin state is also digitally readable by addressing the DR register. Notes: - Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. - When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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Figure 28. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 0 ALTERNATE ENABLE DR VDD P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR PULL-UP CONDITION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD
OR
EXTERNAL INTERRUPT SOURCE (eix)
Table 12. I/O Port Mode Options
Configuration Mode Input Output Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) Pull-Up Off On Off P-Buffer Off On Off On On Diodes to VDD to VSS
Legend:NI - not implemented Off - implemented not activated On - implemented and activated
DATA BUS
DR SEL
1 0
ALTERNATE INPUT FROM OTHER BITS
POLARITY SELECTION
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I/O PORTS (Cont'd) Table 13. I/O Port Configurations
Hardware Configuration
VDD RPU PAD PULL-UP CONDITION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONDITION POLARITY SELECTION ANALOG INPUT EXTERNAL INTERRUPT SOURCE (eix)
INPUT 1)
VDD
DR REGISTER ACCESS
OPEN-DRAIN OUTPUT 2)
RPU PAD DR REGISTER R/W DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
VDD
DR REGISTER ACCESS
PUSH-PULL OUTPUT 2)
RPU PAD DR REGISTER R/W DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function Enable Exit Exit Event Interrupt Event Control from from When the pin is used as an ADC input, the I/O Flag Bit Wait Halt must be configured as floating input. The analog External interrupt on multiplexer (controlled by the ADC registers) DDRx selected external Yes Yes switches the analog voltage present on the selectORx event ed pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level 9.6 I/O PORT IMPLEMENTATION or loading on any port pin while conversion is in The hardware implementation on each I/O port deprogress. Furthermore it is recommended not to pends on the settings in the DDR and OR registers have clocking pins located close to a selected anand specific feature of the I/O port such as ADC Inalog pin. put or true open drain. Switching these I/O ports from one state to anothWARNING: The analog input voltage level must er should be done in a sequence that prevents unbe within the limits stated in the absolute maxiwanted side effects. Recommended safe transimum ratings. tions are illustrated in Figure 29. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects 9.3 UNUSED I/O PINS such as spurious interrupt generation. Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.8. Figure 29. Interrupt I/O Port State Transitions 9.4 LOW POWER MODES
Mode WAIT HALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode. 01
INPUT floating/pull-up interrupt
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX
= DDR, OR
9.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in Table 14. Port Configuration
Port Port A Pin name PA0:2, PA4:5 PA3
The I/O port register configurations are summarised as follows.
Input (DDR=0) OR = 0 OR = 1 floating pull-up interrupt -
Output (DDR=1) OR = 0 OR = 1 open drain push-pull open drain push-pull
Note: after reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0 and MUXCR1 registers. See section 6.4 on page 24
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I/O PORTS (Cont'd) Table 15. I/O Port Register Map and Reset Values
Address (Hex.) 0000h 0001h 0002h Register Label PADR Reset Value PADDR Reset Value PAOR Reset Value 7 MSB 0 MSB 0 MSB 0 6 5 4 3 2 1 0 LSB 0 LSB 0 LSB 0
0 0 0
0 0 0
0 0 0
0 1 0
0 0 0
0 0 1
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10 ON-CHIP PERIPHERALS
10.1 LITE TIMER (LT) 10.1.1 Introduction The Lite Timer can be used for general-purpose timing functions. It is based on a free-running 13bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watchdog function. 10.1.2 Main Features Realtime Clock - 13-bit upcounter - 1 ms or 2 ms timebase period (@ 8 MHz fOSC) - Maskable timebase interrupt Input Capture - 8-bit input capture register (LTICR) - Maskable interrupt with wakeup from Halt Mode capability Figure 30. Lite Timer Block Diagram
fLTIMER
To 12-bit AT TImer
Watchdog - Enabled by hardware or software (configurable by option byte) - Optional reset on HALT instruction (configurable by option byte) - Automatically resets the device unless disable bit is refreshed - Software reset (Forced Watchdog reset) - Watchdog reset status flag
fWDG fOSC 13-bit UPCOUNTER /2 fLTIMER 1 0
WATCHDOG
WATCHDOG RESET
Timebase 1 or 2 ms (@ 8MHz fOSC)
LTICR
8 MSB
LTIC
8-bit INPUT CAPTURE REGISTER LTCSR
ICIE 7 ICF TB TBIE TBF WDG RF WDGE WDGD 0
LTTB INTERRUPT REQUEST LTIC INTERRUPT REQUEST
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LITE TIMER (Cont'd) 10.1.3 Functional Description The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of fOSC. A counter overflow event occurs when the counter rolls over from 1F39h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR register. When the timer overflows, the TBF bit is set by hardware and an interrupt request is generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register. 10.1.3.1 Watchdog The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2ms (@ fosc = 8 MHz ), after which it then generates a reset. To prevent this watchdog reset occuring, software must set the WDGD bit. The WDGD bit is cleared by hardware after tWDG. This means that software must write to the WDGD bit at regular intervals to prevent a watchdog reset occurring. Refer to Figure . If the watchdog is not enabled immediately after reset, the first watchdog timeout will be shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms period has already elapsed after the last MCU reset, the watchdog reset will take place as soon as the WDGE bit is set. For these reasons, it is recommended to enable the Watchdog immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog reset will not occur for at least 2ms. Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.
A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the WDGRF bit has to be set. The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the reset. It is automatically cleared after it has been read. Caution: When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or software), the microcontroller will be immediately reset. Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGE bit in the LTCSR is not used. Refer to the Option Byte description in the "device configuration and ordering information" section. Using Halt Mode with the Watchdog (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite Timer stops counting and is no longer able to generate a Watchdog reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 64 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state). If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
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LITE TIMER (Cont'd) Figure 31. Watchdog Timing Diagram
HARDWARE CLEARS WDGD BIT
fWDG WDGD BIT INTERNAL WATCHDOG RESET
tWDG (2ms @ 8MHz fOSC)
SOFTWARE SETS WDGD BIT
WATCHDOG RESET
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LITE TIMER (Cont'd) Input Capture The 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR register contains the MSB of the free-running upcounter. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The LTICR is a read only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set. 10.1.4 Low Power Modes
Mode WAIT ACTIVE-HALT HALT Description No effect on Lite timer No effect on Lite timer Lite timer stops counting
10.1.5 Interrupts
Interrupt Event Timebase Event IC Event Event Flag TBF ICF Enable Control Bit TBIE ICIE Exit Exit from from Wait Halt Yes Yes No No Exit from ActiveHalt Yes No
Note: The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter). They generate an interrupt if the enable bit is set in the LTCSR register and the interrupt mask in the CC register is reset (RIM instruction).
Figure 32. Input Capture Timing Diagram
125ns (@ 8MHz fOSC)
fCPU fOSC CLEARED BY S/W READING LTIC REGISTER
13-bit COUNTER
0001h
0002h
0003h
0004h
0005h
0006h
0007h
LTIC PIN ICF FLAG LTICR REGISTER xxh 04h 07h
t
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LITE TIMER (Cont'd) 10.1.6 Register Description LITE TIMER CONTROL/STATUS REGISTER (LTCSR) Read / Write Reset Value: 0000 0x00 (0xh)
7 ICIE ICF TB TBIE TBF 0 WDG WDG WDGE R D
0: No counter overflow 1: A counter overflow has occurred Bit 2 = WDGRF Force Reset/ Reset Status Flag This bit is used in two ways: it is set by software to force a watchdog reset. It is set by hardware when a watchdog reset occurs and cleared by hardware or by software. It is cleared by hardware only when an LVD reset occurs. It can be cleared by software after a read access to the LTCSR register. 0: No watchdog reset occurred. 1: Force a watchdog reset (write), or, a watchdog reset occurred (read). Bit 1 = WDGE Watchdog Enable This bit is set and cleared by software. 0: Watchdog disabled 1: Watchdog enabled Bit 0 = WDGD Watchdog Reset Delay This bit is set by software. It is cleared by hardware at the end of each tWDG period. 0: Watchdog reset not delayed 1: Watchdog reset delayed LITE TIMER INPUT CAPTURE REGISTER (LTICR) Read only Reset Value: 0000 0000 (00h)
7 0
Bit 7 = ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register Bit 5 = TB Timebase period selection. This bit is set and cleared by software. 0: Timebase period = tOSC * 8000 (1ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2ms @ 8 MHz) Bit 4 = TBIE Timebase Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB) interrupt disabled 1: Timebase (TB) interrupt enabled Bit 3 = TBF Timebase Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect.
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bit 7:0 = ICR[7:0] Input Capture Value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin.
Table 16. Lite Timer Register Map and Reset Values
Address (Hex.) 0B 0C Register Label LTCSR Reset Value LTICR Reset Value 7 ICIE 0 ICR7 0 6 ICF 0 ICR6 0 5 TB 0 ICR5 0 4 TBIE 0 ICR4 0 3 TBF 0 ICR3 0 2 WDGRF x ICR2 0 1 WDGE 0 ICR1 0 0 WDGD 0 ICR0 0
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10.2 12-BIT AUTORELOAD TIMER (AT) 10.2.1 Introduction The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on a freerunning 12-bit upcounter with a PWM output channel. 10.2.2 Main Features 12-bit upcounter with 12-bit autoreload register (ATR) Maskable overflow interrupt Figure 33. Block Diagram
7 ATCSR 0 0 0 CK1 CK0 0 OVF OVFIE CMPIE OVF INTERRUPT REQUEST

PWM signal generator Frequency range 2KHz-4MHz (@ 8 MHz fCPU) - Programmable duty-cycle - Polarity control - Maskable Compare interrupt Output Compare Function
fLTIMER (1 ms timebase @ 8MHz) fCPU
CMPF0 fCOUNTER CNTR 12-BIT UPCOUNTER
CMP INTERRUPT REQUEST
Update on OVF Event
12-BIT AUTORELOAD VALUE
ATR OE0 bit PWM GENERATION OE0 bit CMPF0 bit 0 COMPPARE OP0 bit fPWM POLARITY OUTPUT CONTROL DCR0H DCR0L
Preload
Preload on OVF Event IF OE0=1
PWM0
1
12-BIT DUTY CYCLE VALUE (shadow)
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12-BIT AUTORELOAD TIMER (Cont'd) 10.2.3 Functional Description PWM Mode This mode allows a Pulse Width Modulated signals to be generated on the PWM0 output pin with minimum core processing overhead. The PWM0 output signal can be enabled or disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is configured as output pushpull alternate function. Note: CMPF0 is available in PWM mode (see PWM0CSR description on page 56). PWM Frequency and Duty Cycle The PWM signal frequency (fPWM) is controlled by the counter period and the ATR register value. fPWM = fCOUNTER / (4096 - ATR) Following the above formula, if fCPU is 8 MHz, the maximum value of fPWM is 4 Mhz (ATR register value = 4094), and the minimum value is 2 kHz (ATR register value = 0). Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. At reset, the counter starts counting from 0. Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The DCR0H register must be written first. See caution below.
When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter, the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0 signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register must be greater than the contents of the ATR register. The polarity bit can be used to invert the output signal. The maximum available resolution for the PWM0 duty cycle is: Resolution = 1 / (4096 - ATR) Note: To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by changing the polarity . Caution: As soon as the DCR0H is written, the compare function is disabled and will start only when the DCR0L value is written. If the DCR0H write occurs just before the compare event, the signal on the PWM output may not be set to a low level. In this case, the DCRx register should be updated just after an OVF event. If the DCR and ATR values are close, then the DCRx register shouldbe updated just before an OVF event, in order not to miss a compare event and to have the right signal applied on the PWM output.
Figure 34. PWM Function
4095 DUTY CYCLE REGISTER (DCR0)
COUNTER
AUTO-RELOAD REGISTER (ATR) 000
t
PWM0 OUTPUT
WITH OE0=1 AND OP0=0 WITH OE0=1 AND OP0=1
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12-BIT AUTORELOAD TIMER (Cont'd) Figure 35. PWM Signal Example
fCOUNTER ATR= FFDh PWM0 OUTPUT WITH OE0=1 AND OP0=0 COUNTER FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh
DCR0=FFEh
t
Output Compare Mode To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H and DCR0L registers. This value will be loaded immediately (without waiting for an OVF event). The DCR0H must be written first, the output compare function starts only when the DCR0L value is written. When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is generated if the CMPIE bit is set. Note: The output compare function is only available for DCRx values other than 0 (reset value). Caution: At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value has not yet been written (in this case, the shadow register will contain the new DCR0H value and the old DCR0L value), then: - If OE=1 (PWM mode): the compare is done between the timer counter and the shadow register (and not DCRx) - if OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There is no PWM signal.
The compare between DCRx or the shadow register and the timer counter is locked until DCR0L is written. 10.2.4 Low Power Modes Mode Description The input frequency is divided SLOW by 32 WAIT No effect on AT timer AT timer halted except if CK0=1, ACTIVE-HALT CK1=0 and OVFIE=1 HALT AT timer halted 10.2.5 Interrupts
Interrupt Event 1) Overflow Event CMP Event Enable Exit Exit Event Control from from Flag Wait Halt Bit OVF OVFIE Yes No No Exit from ActiveHalt Yes2) No
CMPFx CMPIE Yes
Note 1: The interrupt events are connected to separate interrupt vectors (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction). Note 2: only if CK0=1and CK1=0
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12-BIT AUTORELOAD TIMER (Cont'd) 10.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 CK1 CK0 OVF 0 OVFIE CMPIE
0: OVF interrupt disabled 1: OVF interrupt enabled
Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and clear by hardware after a reset. It allows to mask the interrupt generation when CMPF bit is set. 0: CMPF interrupt disabled 1: CMPF interrupt enabled
Bit 7:5 = Reserved, must be kept cleared.
Bit 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter.
Counter Clock Selection OFF fLTIMER (1 ms timebase @ 8 MHz) fCPU Reserved CK1 0 0 1 1 CK0 0 1 0 1
COUNTER REGISTER HIGH (CNTRH) Read only Reset Value: 0000 0000 (00h)
15 0 0 0 0 CN11 CN10 CN9 8 CN8
COUNTER REGISTER LOW (CNTRL) Read only Reset Value: 0000 0000 (00h)
7 0 CN6 CN5 CN4 CN3 CN2 CN1 CN0
Bit 2 = OVF Overflow Flag. This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter from FFFh to ATR value. 0: No counter overflow occurred 1: Counter overflow occurred Caution: When set, the OVF bit stays high for 1 fCOUNTER cycle, (up to 1ms depending on the clock selection).
CN7
Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = CNTR[11:0] Counter Value. This 12-bit register is read by software and cleared by hardware after a reset. The counter is incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations, LSB first. When a counter overflow occurs, the counter restarts from the value specified in the ATR register.
Bit 1 = OVFIE Overflow Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset.
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12-BIT AUTORELOAD TIMER (Cont'd) AUTO RELOAD REGISTER (ATRH) Read / Write Reset Value: 0000 0000 (00h)
15 0 0 0 0 ATR11 ATR10 ATR9 8 ATR8
PWM0 DUTY CYCLE REGISTER LOW (DCR0L) Read / Write Reset Value: 0000 0000 (00h)
7 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 0 DCR1 DCR0
AUTO RELOAD REGISTER (ATRL) Read / Write Reset Value: 0000 0000 (00h)
7 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 0 ATR0
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value This 12-bit value is written by software. The high register must be written first. In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWM0 output signal (see Figure 34). In Output Compare mode, (OE0=0 in the PWMCR register) they define the value to be compared with the 12bit upcounter value.
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = ATR[11:0] Autoreload Register. This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the PWM frequency. PWM0 DUTY CYCLE REGISTER HIGH (DCR0H) Read / Write Reset Value: 0000 0000 (00h)
15 0 0 0 0 8
PWM0 CONTROL/STATUS (PWM0CSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0
REGISTER
0 OP0 CMPF0
Bit 7:2= Reserved, must be kept cleared.
DCR11 DCR10 DCR9 DCR8
Bit 1 = OP0 PWM0 Output Polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM0 signal. 0: The PWM0 signal is not inverted. 1: The PWM0 signal is inverted. Bit 0 = CMPF0 PWM0 Compare Flag. This bit is set by hardware and cleared by software by reading the PWM0CSR register. It indicates that the upcounter value matches the DCR0 register value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value.
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12-BIT AUTORELOAD TIMER (Cont'd) PWM OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h)
7
0 0 0 0 0 0 0
Bits 7:1 = Reserved, must be kept cleared. Bit 0 = OE0 PWM0 Output enable. This bit is set and cleared by software. 0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O) 1: PWM0 output enabled
0
OE0
Table 17. Register Map and Reset Values
Address (Hex.) 0D 0E 0F 10 11 12 13 17 18 Register Label ATCSR Reset Value CNTRH Reset Value CNTRL Reset Value ATRH Reset Value ATRL Reset Value PWMCR Reset Value PWM0CSR Reset Value DCR0H Reset Value DCR0L Reset Value 7 6 5 4 CK1 0 0 CN4 0 0 ATR4 0 0 0 0 DCR4 0 3 CK0 0 CN11 0 CN3 0 ATR11 0 ATR3 0 0 0 DCR11 0 DCR3 0 2 OVF 0 CN10 0 CN2 0 ATR10 0 ATR2 0 0 0 DCR10 0 DCR2 0 1 OVFIE 0 CN9 0 CN1 0 ATR9 0 ATR1 0 0 OP 0 DCR9 0 DCR1 0 0 CMPIE 0 CN8 0 CN0 0 ATR8 0 ATR0 0 OE0 0 CMPF0 0 DCR8 0 DCR0 0
0 0 CN7 0 0 ATR7 0 0 0 0 DCR7 0
0 0 CN6 0 0 ATR6 0 0 0 0 DCR6 0
0 0 CN5 0 0 ATR5 0 0 0 0 DCR5 0
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10.3 10-BIT A/D CONVERTER (ADC) 10.3.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources. The result of the conversion is stored in a 10-bit Data Register. The A/D converter is controlled through a Control/Status Register. 10.3.2 Main Features 10-bit conversion Up to 5 channels with multiplexed input Linear successive approximation Figure 36. ADC Block Diagram fCPU
DIV 4 DIV 2 0 0 1 SLOW bit 1
Data register (DR) which contains the results Conversion complete status flag On/off bit (to reduce consumption) The block diagram is shown in Figure 36. 10.3.3 Functional Description 10.3.3.1 Analog Power Supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines.

fADC
EOC SPEED ADON
0
0
CH2
CH1
CH0
ADCCSR
3
AIN0
HOLD CONTROL
AIN1
RADC
ANALOG MUX
ANALOG TO DIGITAL CONVERTER
AINx
CADC
ADCDRH
D9
D8
D7
D6
D5
D4
D3
D2
ADCDRL
0
0
0
0
SLOW
0
D1
D0
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10-BIT A/D CONVERTER (ADC) (Cont'd) 10.3.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VDDA (highlevel voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 10.3.3.3 A/D Conversion Phases The A/D conversion is based on two conversion phases: Sample capacitor loading [duration: tSAMPLE] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor. A/D conversion [duration: tHOLD] During this phase, the A/D conversion is computed (8 successive approximations cycles) and the CADC sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. The total conversion time: tCONV = tSAMPLE + tHOLD While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement.
not affect the ability of the port to be read as a logic input. In the ADCCSR register: - Select the CS[2:0] bits to assign the analog channel to convert. ADC Conversion mode In the ADCCSR register: Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: - The EOC bit is set by hardware. - The result is in the ADCDR registers. A read to the ADCDRH resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRL 3. Read ADCDRH. This clears EOC automatically. To read only 8 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRH. This clears EOC automatically. 10.3.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions.
Mode WAIT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time tSTAB (see Electrical Characteristics) before accurate conversions can be performed.
HALT
10.3.3.4 A/D Conversion The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the "I/O ports" chapter. Using these pins as analog inputs does
10.3.5 Interrupts None.
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10-BIT A/D CONVERTER (ADC) (Cont'd) 10.3.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h)
7 EOC SPEE ADO D N 0 0 CH2 CH1 0 CH0
Note: A write to the ADCCSR register (with ADON set) aborts the current conversion, resets the EOC bit and starts a new conversion. DATA REGISTER HIGH (ADCDRH) Read Only Reset Value: 0000 0000 (00h)
7 D9 D8 D7 D6 D5 D4 D3 0 D2
Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by software reading the ADCDRH register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED ADC clock selection This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit description. Bit 5 = ADON A/D Converter on This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bits 4:3 = Reserved. Must be kept cleared. Bit 2:0 = CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert.
Channel Pin AIN0 AIN1 AIN2 AIN3 AIN4 CH2 0 0 0 0 1 CH1 0 0 1 1 0 CH0 0 1 0 1 0
Bits 7:0 = D[9:2] MSB of Analog Converted Value DATA REGISTER LOW (ADCDRL) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 SLOW 0 D1 0 D0
Bits 7:5 = Reserved. Forced by hardware to 0. Bit 4 = Reserved. Forced by hardware to 0. Bit 3 = SLOW Slow mode This bit is set and cleared by software. It is used together with the SPEED bit to configure the ADC clock speed as shown on the table below.
fADC fCPU/2 fCPU fCPU/4 SLOW 0 0 1 SPEED 0 1 x
Bit 2 = Reserved. Forced by hardware to 0. Bit 1:0 = D[1:0] LSB of Analog Converted Value
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Table 18. ADC Register Map and Reset Values
Address (Hex.) 0034h 0035h 0036h Register Label ADCCSR Reset Value ADCDRH Reset Value ADCDRL Reset Value 7 EOC 0 D9 0 0 0 6 SPEED 0 D8 0 0 0 5 ADON 0 D7 0 0 0 4 0 0 D6 0 0 0 3 0 0 D5 0 SLOW 0 2 CH2 0 D4 0 0 0 1 CH1 0 D3 0 D1 0 0 CH0 0 D2 0 D0 0
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11 INSTRUCTION SET
11.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do Table 19. ST7 Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination/ Source
Pointer Address (Hex.)
Pointer Size (Hex.) +0 +1
Length (Bytes)
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC-128/PC+1271) PC-128/PC+127 00..FF 00..FF 00..FF 00..FF byte 00..FF byte
1)
+1 +2 + 0 (with X register) + 1 (with Y register) +1 +2 00..FF 00..FF 00..FF 00..FF 00..FF byte word byte word byte +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
btjt [$10],#7,skip 00..FF
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7 ADDRESSING MODES (Cont'd) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
11.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 11.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 11.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
11.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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ST7 ADDRESSING MODES (Cont'd) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 20. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Addition/subtraction operations Bit Compare Function
SWAP CALL, JP
Swap Nibbles Call or Jump subroutine
11.1.7 Relative Mode (Direct, Indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.
Available Relative Direct/ Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC Clear
Function Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations
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11.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. 11.2.1 Illegal Opcode Reset In order to provide enhanced robustness to the device against unexpected behaviour, a system of illegal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, combined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset.
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INSTRUCTION GROUPS (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. interrupt = 1 Jump if ext. interrupt = 0 Jump if H = 1 Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) H=1? H=0? I=1? I=0? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > jrf * Pop CC, A, X, PC inc X jp [TBL.w] reg, M H tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 0 I N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst M M M M Src H H H I N N N N N Z Z Z Z Z C C C
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INSTRUCTION GROUPS (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack A=A+M pop reg pop CC PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I=0 C <= Dst <= C C => Dst => C S = Max allowed A=A-M-C C=1 I=1 C <= Dst <= 0 C <= Dst <= 0 0 => Dst => C Dst7 => Dst => C A=A-M reg, M reg, M reg, M reg, M A M 1 N N 0 N N N N 1 0 N Z Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 0 N N Z Z C C push Y C=0 A reg CC M M M M reg, CC 0 H I N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src H I N Z C
Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1 S/W interrupt
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12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 12.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 12.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, VDD=5V (for the 4.5VVDD5.5V voltage range), VDD=3.75V (for the 3VVDD4.5V voltage range) and VDD=2.7V (for the 2.4VVDD3V voltage range). They are given only as design guidelines and are not tested. 12.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 37. Figure 37. Pin loading conditions 12.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 38. Figure 38. Pin input voltage
ST7 PIN
VIN
ST7 PIN
CL
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12.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi12.2.1 Voltage Characteristics
Symbol VDD - VSS VIN VESD(HBM) VESD(MM) Supply voltage Input voltage on any pin 1) & 2) Electrostatic discharge voltage (Human Body Model) Electrostatic discharge voltage (Machine Model) Ratings
tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Maximum value 7.0 VSS-0.3 to VDD+0.3
Unit V
see section 12.7.2 on page 78 see section 12.7.2 on page 78
12.2.2 Current Characteristics
Symbol IVDD IVSS IIO Ratings Total current into VDD power lines (source) 3) Total current out of VSS ground lines (sink) 3) Output current sunk by any standard I/O and control pin Output current sunk by any high sink I/O pin Output current source by any I/Os and control pin IINJ(PIN) 2) & 4) IINJ(PIN) 2) Injected current on RESET pin Injected current on any other pin 5) Total injected current (sum of all I/O and control pins) 5) Maximum value 100 100 6 20 20 5 5 20 mA Unit
12.2.3 Thermal Characteristics
Symbol TSTG TJ Ratings Storage temperature range Value -65 to +150 Unit C
Maximum junction temperature (see Section Figure 67. 16-Pin Plastic Dual In-Line Package, 300-mil Width)
Notes: 1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10k for I/Os). Unused I/ O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN69/101
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12.3 OPERATING CONDITIONS 12.3.1 General Operating Conditions TA = -40 to +85C unless otherwise specified.
Symbol VDD fCPU Parameter Supply voltage CPU clock frequency Conditions fCPU = 4 MHz. max. fCPU= 8 MHz. max. 3.3V VDD5.5V 2.4VVDD<3.3V Min 2.4 3.3 up to 8 up to 4 Max 5.5 5.5 Unit V MHz
Figure 39. fCPU Maximum Operating Frequency Versus VDD Supply Voltage
fCPU [MHz] FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF PARAMETRIC DATA)
8 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 4 2 0 2.0 2.4 2.7 3.3 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE [V]
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12.3.2 Operating Conditions with Low Voltage Detector (LVD) TA = 25 to 85C, unless otherwise specified
Symbol VIT+(LVD) Parameter Reset release threshold (VDD rise) Reset generation threshold (VDD fall) LVD voltage threshold hysteresis VDD rise time rate 2) Filtered glitch delay on VDD LVD/AVD current consumption Conditions 3) High Threshold Med. Threshold Low Threshold High Threshold Med. Threshold Low Threshold VIT+(LVD)-VIT-(LVD) Not detected by the LVD 220 Min 3.70 3.30 2.30 3.50 3.20 2.20 20 Typ 4.20 3.70 2.65 4.00 3.55 2.55 200 Max 4.70 4.20 3.00 4.50 4.10 2.90 Unit
V
VIT-(LVD) Vhys VtPOR tg(VDD) IDD(LVD)
mV s/V ns A
Notes:
1. Not tested in production. 2. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU. 3. LVD and AVD high thresholds must not be selected at the same time.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds TA = 25 to 85C, unless otherwise specified
Symbol VIT+(AVD) Parameter 1=>0 AVDF flag toggle threshold (VDD rise) 0=>1 AVDF flag toggle threshold (VDD fall) AVD voltage threshold hysteresis Voltage drop between AVD flag set and LVD reset activation Conditions 1) High Threshold Med. Threshold Low Threshold High Threshold Med. Threshold Low Threshold VIT+(AVD)-VIT-(AVD) VDD fall Min 3.70 3.50 2.50 3.60 3.40 2.40 Typ 4.20 4.00 2.85 4.10 3.90 2.75 100 0.45 Max 4.70 4.50 3.20 4.60 4.40 3.10 Unit
V
VIT-(AVD) Vhys VIT-
mV V
Note 1: LVD and AVD high thresholds must not be selected at the same time. Note: Refer to section 7.4.2.1 on page 30 12.3.4 Voltage drop between AVD and LVD threshold
Parameter AVD med. Threshold - AVD low. threshold AVD high. Threshold - AVD low. threshold AVD high. Threshold - AVD med. threshold AVD low. Threshold - LVD low. threshold AVD med. Threshold - LVD low. threshold AVD med. Threshold - LVD med. threshold AVD high. Threshold - LVD low. threshold AVD high. Threshold - LVD med. threshold Min 1) 1000 1200 100 75 1100 100 1200 250 Typ 1) 1200 1400 200 150 1300 300 1500 500 Max 1) 1400 1600 300 250 1600 550 1900 800 Unit
mV
Note 1: Not tested in production, guaranteed by characterization.
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OPERATING CONDITIONS (Cont'd) 12.3.5 Internal RC Oscillator The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte).
Symbol Parameter Internal RC Oscillator operating VDD(RC) voltage Internal RC oscillator frequency Conditions Min 2.4 4500 8000 -4 -52) TBD TBD2) TBD2) TBD TBD +4 +52) TBD TBD2) TBD2) % % % % % A s Typ Max 5.5 Unit V kHz
fRC
ACCRC
IDD(RC) tsu(RC)
RCCR = FF (reset value), TA=25C,VDD=5V RCCR = RCCR01 ),TA=25C,VDD=5V TA=25C, VDD=5V Accuracy of Internal RC oscillator TA=25C, VDD=4.5 to 5.5V with TA=0 to +85C, VDD=5V RCCR=RCCR01) TA=0 to +85C, VDD=4.5 to 5.5V TA=0 to +-40C, VDD=4.5 to 5.5V RC oscillator current consumption TA=25C, VDD=5V RC oscillator setup time TA=25C, VDD=5V
Notes: 1. See "INTERNAL RC OSCILLATOR ADJUSTMENT" on page 17 2. Data based on characterization results, not tested in production To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device
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12.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total de12.4.1 Supply Current TA = -40 to +85C unless otherwise specified
Symbol Parameter Supply current in RUN mode 1) VDD=5V Supply current in WAIT mode 2) Supply current in SLOW mode 3) Supply current in SLOW-WAIT mode 4) Supply current in AWUFH mode 5)6) Supply current in HALT mode 7) Supply current in RUN mode 1) VDD=3V Supply current in WAIT mode 2) Supply current in SLOW mode 3) Supply current in SLOW-WAIT mode 4) Supply current in AWUFH mode 5)6) Supply current in HALT mode 7)
vice consumption, the two current values must be added (except for HALT mode for which the clock is stopped).
IDD
Conditions fCPU=4MHz fCPU=8MHz fCPU=4MHz fCPU=8MHz fCPU/32=250kHz fCPU/32=250kHz fCPU/32=250kHz fCPU/32=250kHz fCPU=4MHz fCPU=8MHz fCPU=4MHz fCPU=8MHz fCPU/32=250kHz fCPU/32=250kHz fCPU/32=250kHz fCPU/32=250kHz
Typ 2.5 5.0 1.0 1.5 650 500 250 0 1.5 2.5 0.5 0.7 350 300 120 0
Max 5.0 8) 9.0 2.5 8) 4.0 900 700 TBD 8) TBD 4.0 8) 6.5 8) 2.5 8) 2.5 8) 500 8) 500 8) TBD 8) TBD 8)
Unit
mA
A
mA
A
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 3. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 5. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU max. 6. This consumption refers to the Halt period only and not the associated run period which is software dependent. 7. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results, tested in production at VDD max and fCPU max. 8. Data based on characterization, not tested in production.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) Figure 40. Typical IDD in RUN vs. fCPU
7.00
Figure 43. Typical IDD in SLOW-WAIT vs. fCPU
0.80 0.70
6.00 5.00 4.00 3.00 2.00 2 MHz 4 MHz 8 MHz
0.60 0.50 Idd [mA] 0.40 0.30 0.20
2 MHz 4 MHz 8 MHz
Idd [mA]
1.00
0.10
0.00 2.4 2.6 2.8 3 Vdd [V] 4 5 6
0.00 2.4 2.6 2.8 3 Vdd [V] 4 5 6
Figure 41. Typical IDD in SLOW vs. fCPU
0.90 0.80 0.70 0.60 Idd [mA] 0.50 0.40 0.30 0.20 0.10 0.00 2.4 2.6 2.8 3 Vdd [V] 4 5 6 2 MHz 4 MHz 8 MHz
Figure 44. Typical IDD vs. Temperature at VDD = 5V and fCPU = 8MHz
6.00
5.00
4.00 Idd [mA]
3.00
RUN WAIT SLOW SLOW-WAIT
2.00
1.00
0.00 -45 25 Vdd [V] 90 130
Figure 42. Typical IDD in WAIT vs. fCPU
2.00 1.80 1.60 1.40 1.20 Idd [mA] 1.00 0.80 0.60 0.40 0.20 0.00 2.4 2.6 2.8 3 Vdd [V] 4 5 6 2 MHz 4 MHz 8 MHz
12.4.2 On-chip peripherals
Symbol IDD(AT) IDD(ADC) Parameter 12-bit Auto-Reload Timer supply current 1) ADC supply current when converting 2) Conditions fCPU=4MHz VDD=3.0V VDD=5.0V fCPU=8MHz VDD=3.0V fADC=4MHz VDD=5.0V Typ 150 250 250 1100 Unit A
1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM mode at fcpu=8MHz. 2. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with amplifier off.
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12.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 12.5.1 General Timings
Symbol tc(INST) tv(IT) Parameter 1) Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10
3)
Conditions fCPU=8MHz fCPU=8MHz
Min 2 250 10 1.25
Typ 2) 3 375
Max 12 1500 22 2.75
Unit tCPU ns tCPU s
Notes:
1. Data based on characterization. Not tested in production. 2. Data based on typical application software. 3. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution.
12.5.2 Auto Wakeup from Halt Oscillator (AWU)
Parameter Supply Voltage Range Operating Temperature Range Current Consumption 1) Consumption 1) Output Frequency
1)
Conditions
Min 2.4 -40
Typ 5.0 27 8.0 0 33
Max 5.5 125 14.0 60
Unit V C A A kHz
Without prescaler AWU RC switched off
2.0 20
1. Data based on characterization. Not tested in production.
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12.6 MEMORY CHARACTERISTICS TA = -40C to 85C, unless otherwise specified 12.6.1 RAM and Hardware Registers
Symbol VRM Parameter Data retention mode
1)
Conditions HALT mode (or RESET)
Min 1.6
Typ
Max
Unit V
12.6.2 FLASH Program Memory
Symbol VDD tprog tRET NRW Parameter Operating voltage for Flash write/erase Programming time for 1~32 bytes 2) Programming time for 1 kByte Data retention 4) Write erase cycles Conditions Min 2.4 Typ 5 0.16 Max 5.5 10 0.32 Unit V ms s years cycles mA A A
IDD
Supply current 6)
TA=-40 to +85C TA=+25C TA=+55C 3) 20 TA=+25C 10K 7) Read / Write / Erase modes fCPU = 8MHz, VDD = 5.5V No Read/No Write Mode Power down mode / HALT
2.6 100 0.1
0
Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. Up to 32 bytes can be programmed at a time. 3. The data retention time increases when the TA decreases. 4. Data based on reliability test results and monitored in production. 5. Data based on characterization results, not tested in production. 6. Guaranteed by Design. Not tested in production. 7. Design target value pending full product characterization.
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12.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 12.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. 12.7.1.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It
Symbol VFESD Parameter
should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: - Corrupted program counter - Unexpected reset - Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Conditions Level/ Class 3B
VFFTB
VDD=5V, TA=+25C, fOSC=8MHz, Voltage limits to be applied on any I/O pin to induce a SO8 package, functional disturbance conforms to IEC 1000-4-2 Fast transient voltage burst limits to be applied VDD=5V, TA=+25C, fOSC=8MHz, through 100pF on VDD and VDD pins to induce a func- SO8 package, tional disturbance conforms to IEC 1000-4-4
4B
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EMC CHARACTERISTICS (Cont'd) 12.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin.
Symbol Parameter Conditions Monitored Frequency Band Max vs. [fOSC/fCPU] -/8MHz 22 24 14 3 Unit
SEMI
Peak level
0.1MHz to 30MHz VDD=5V, TA=+25C, 30MHz to 130MHz SO8 package, conforming to SAE J 1752/3 130MHz to 1GHz SAE EMI Level
dBV -
Notes: 1. Data based on characterization results, not tested in production. 12.7.3 Absolute Maximum Ratings (Electrical 12.7.3.1 Electro-Static Discharge (ESD) Sensitivity) Electro-Static Discharges (a positive then a negaBased on three different tests (ESD, LU and DLU) tive pulse separated by 1 second) are applied to using specific measurement methods, the product the pins of each sample according to each pin is stressed in order to determine its performance in combination. The sample size depends on the terms of electrical sensitivity. For more details, renumber of supply pins in the device (3 parts*(n+1) fer to the application note AN1181. supply pin). One model can be simulated: Human Body Model. This test conforms to the JESD22A114A/A115A standard. Absolute Maximum Ratings
Symbol VESD(HBM) Ratings Electro-static discharge voltage (Human Body Model) TA=+25C Conditions Maximum value 1) Unit > 2000 V
Note:
1. Data based on characterization results, not tested in production.
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EMC CHARACTERISTICS (Cont'd) 12.7.3.2 Static and Dynamic Latch-Up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.
Class 1) A A
Electrical Sensitivities
Symbol LU DLU Parameter Static latch-up class Dynamic latch-up class TA=+25C VDD=5.5V, fOSC=4MHz, TA=+25C Conditions
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).
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12.8 I/O PORT PIN CHARACTERISTICS 12.8.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys IL IS RPU CIO tf(IO)out tr(IO)out tw(IT)in Parameter Input low level voltage Input high level voltage Schmitt trigger voltage hysteresis 1) Input leakage current VSSVINVDD 400 50 120 160 5 CL=50pF Between 10% and 90% 1 25 ns 25 tCPU 250 Static current consumption induced by each floating input Floating input mode pin2) Weak pull-up equivalent resistor3) I/O pin capacitance Output high to low level fall time 1) Output low to high level rise time 1) External interrupt pulse time 4) VIN=VSS VDD=5V VDD=3V Conditions -40C to 130C Min 0.7 x VDD 400 1 A mV Typ Max 0.3xVDD Unit V
k pF
Notes:
1. Data based on characterization results, not tested in production. 2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 49). Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in production. This value depends on VDD and temperature values. 3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 46). 4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
Figure 45. Two typical Applications with unused I/O Pin
VDD 10k
ST7XXX
10k UNUSED I/O PORT UNUSED I/O PORT
ST7XXX
Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost.
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Figure 46. Typical IPU vs. VDD with VIN=VSS l
90 80 70 60 Ipu(uA) 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 Vdd(V) 5 5.5 6
Ta=140C
Ta=95C
Ta=25C
Ta=-45 C
TO BE CHARACTERIZED
D B T
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I/O PORT PIN CHARACTERISTICS (Cont'd) 12.8.2 Output Driving Current Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Output low level voltage for PA3/RESET standard I/O pin (see Figure 49) VDD=5V VOL 1) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 52) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 56) Output low level voltage for PA3/RESET standard I/O pin (see Figure 48) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 51) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 54) Output low level voltage for PA3/RESET standard I/O pin (see Figure 47) VDD=2.4V VOL
1)3)
Conditions IIO=+5mA,TA85C IIO=+2mA,TA85C IIO=+20mA,TA85C IIO=+8mA,TA85C IIO=-5mA,TA85C IIO=-2mA,TA85C IIO=+2mA,TA85C VDD=3V IIO=+2mA,TA85C IIO=+8mA,TA85C IIO=-2mA,TA85C IIO=+2mA,TA85C IIO=+2mA,TA85C IIO=+8mA,TA85C IIO=-2mA,TA85C
Min
Max 1000 400 1300 750
Unit
VOH 2)
VDD-1500 VDD-800 250 100 400 VDD-300 500 100 500 VDD-200 mV
VOL
1)3)
VOH 2)3)
Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 50) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 53)
VOH 2)3)
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH. 3. Not tested in production, based on characterization results.
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 47. Typical VOL at VDD=2.4V (standard)
VOL (mV) at VDD=2.4 V (STD) 1000 -45C 800 600 400 200 0 0 2 Ilo (mA) 4 6 25C 90C 130C
Figure 50. Typical VOL at VDD=2.4V (high-sink)
1000 800 600 400 200 0 0 2 4 6 8 10 12 Ilo (mA) 14 16 18 20 -45C 25C 90C 130C
Figure 48. Typical VOL at VDD=3V (standard)
Figure 51. Typical VOL at VDD=3V (high-sink)
1000 VOL (mV) at VDD=3 V(STD) -45C 800 600 400 200 0 0 2 Ilo(mA) 4 6
0 0 2 4 6 8 10 12 Ilo (mA) 14 16 18 20 1200 VOL (mV) at VDD=3 V(HS) 1000 800 600 400 200 -45C 25C 90C 130C
25C 90C 130C
Figure 49. Typical VOL at VDD=5V (standard)
1000 VOL (mV) at VDD= 5 V (STD) -45C 800 600 400 200 0 0 2 Ilo (mA) 4 6 90C 130C
Figure 52. Typical VOL at VDD=5V (high-sink)
VOL (mV) at VDD=5 V(HS)
25C
VOL (mV) at VDD=2.4 V(HS)
700 600 500 400 300 200 100 0 0 2 4 6 8 10 12 Ilo(mA) 14 16 18 20 -45C 25C 90C 130C
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 53. Typical VDD-VOH at VDD=2.4V Figure 55. Typical VDD-VOH at VDD=4V
1400 VDD-VOH (mV) at VDD=2.4 V 1200 1000 800 600 400 200 0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 Ilo (mA) -45C 25C 90C 130C VDD-VOH (mV) at VDD=4 V
1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 -2 -4
-45C 25C 90C 130C
-6
-8 -10 -12 -14 -16 -18 -20 Ilo mA)
Figure 54. Typical VDD-VOH at VDD=3V
Figure 56. Typical VDD-VOH at VDD=5V
1000 VDD-VOH (mV) at VDD=5 V 1800 VDD-VOH (mV) at VDD=3 V 1500 -45C 1200 900 600 300 0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 Ilo(mA) 25C 90C 130C 900 800 700 600 500 400 300 200 100 0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 Ilo (mA) -45C 25C 90C 130C
Figure 57. Typical VOL vs. VDD (standard I/Os)
1000 VOL (mV) at Ilo=2mA (Std) 800 600 400 200 0 2.4 2.6 2.8 Ilo (mA) 3 5 -45C 25C 90C 130C
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 58. Typical VOL vs. VDD (high-sink I/Os)
1000 VOL(mV) at Ilo=12mA (HS) -45C VOL(mV) at Ilo=8mA (HS) 800 25C 90C 600 130C
1000
800
600
400
400 -45C 25C 200 90C 130C
200
D B T
2.6 2.8 Ilo (mA) 3 5
0 2.4 2.6 2.8 Ilo (mA) 3 5
0 2.4
Figure 59. Typical VDD-VOH vs. VDD
200 VDD -Voh (mV) at Ilo=2mA
500
VDD -Voh (mV) at Ilo=6mA
160
400
120
300
80
-45C 25C 90C 130C
200
-45C 25C 90C 130C
40
100
D B T
3 3.5 Ilo (mA) 4 5
0 2.5 3 3.5 Ilo (mA) 4 5
0 2.5
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12.9 CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin TA = -40C to 85C, unless otherwise specified
Symbol VIL VIH Vhys VOL RON Parameter Input low level voltage Input high level voltage Schmitt trigger voltage hysteresis 1) Output low level voltage 2) I =+2mA TA85C VDD=5V IO TA85C VDD=5V VDD=3V Internal reset sources 20 200
4)
Conditions
Min VSS - 0.3 0.7xVDD
Typ
Max 0.3xVDD VDD + 0.3
Unit V V
2 0.2 20 40 30 30 0.4 0.5 80
V k s s ns
Pull-up equivalent resistor 3)
tw(RSTL)out Generated reset pulse duration th(RSTL)in tg(RSTL)in External reset pulse hold time Filtered glitch duration
Notes:
1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in section 12.2.2 on page 69 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax and VDD 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored.
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CONTROL PIN CHARACTERISTICS (Cont'd) Figure 60. RESET pin protection when LVD is enabled.1)2)3)4)
VDD Required
EXTERNAL RESET
0.01F 1M ST72XXX
Optional (note 3)
RON
Filter
INTERNAL RESET
PULSE GENERATOR
WATCHDOG ILLEGAL OPCODE 5) LVD RESET
Figure 61. RESET pin protection when LVD is disabled.1)
VDD
ST72XXX
USER EXTERNAL RESET CIRCUIT 0.01F
RON
Filter
INTERNAL RESET
Required
PULSE GENERATOR
WATCHDOG ILLEGAL OPCODE 5)
Note 1: - The reset network protects the device against parasitic resets. - The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). - Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in section 12.9.1 on page 86. Otherwise the reset will not be taken into account internally. - Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in section 12.2.2 on page 69. Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line. Note 3: In case a capacitive power supply is used, it is recommended to connect a 1M pull-down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5A to the power consumption of the MCU). Note 4: Tips when using the LVD: - 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in Table 1 on page 7 and notes above) - 2. Check that the power supply is properly decoupled (100nF + 10F close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M pull-down on the RESET pin. - 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5F to 20F capacitor." Note 5: Please refer to "Illegal Opcode Reset" on page 65 for more details on illegal opcode reset conditions
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12.10 10-BIT ADC CHARACTERISTICS Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol fADC VAIN RAIN CADC tSTAB tADC Parameter ADC clock frequency
2)
Conditions
Min VSSA
Typ 1)
Max 4 VDDA 10K
4)
Unit MHz V pF s 1/fADC
Conversion voltage range 3) External input resistor Internal sample and hold capacitor Stabilization time after ADC enable Conversion time (Sample+Hold) - Sample capacitor loading time - Hold conversion time Analog Part Digital Part fCPU=8MHz, fADC=4MHz
3 0 5) 3.5 4 10 TBD TBD
IADC
mA
Notes:
1. Unless otherwise specified, typical data are based on TA=25C and VDD-VSS=5V. They are given only as design guidelines and are not tested. 2. The maximum ADC clock frequency allowed within VDD = 2.4V to 2.7V operating range is 1MHz. 3. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS. 4. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 5. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then always valid.
Figure 62. Typical Application with ADC
VDD VT 0.6V RAIN VAIN VT 0.6V IL 1A AINx 10-Bit A/D Conversion CADC
ST72XXX
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ADC CHARACTERISTICS (Cont'd) ADC Accuracy with VDD=3.3V
Symbol |ET| |EO| |EG| |ED| |EL| Offset error Gain Error Differential linearity error Integral linearity error fCPU=8MHz, fADC=4MHz
1)
Parameter Total unadjusted error
Conditions 2
Typ -0.5 -1 1.5 TBD
Max TBD TBD TBD TBD TBD
Unit
LSB
Notes:
1. Data based on characterization results over the whole temperature range, monitored in production.
ADC Accuracy with VDD=5V
Symbol |ET| |EO| |EG| |ED| |EL| Offset error Gain Error Differential linearity error Integral linearity error fCPU=8MHz, fADC=4MHz 1) Parameter Total unadjusted error Conditions 1.5 1 1 1.5 TBD Typ Max TBD TBD TBD TBD TBD LSB Unit
Notes:
1. Data based on characterization results over the whole temperature range, monitored in production.
ADC Accuracy with VDD=2.4V
Symbol |ET| |EO| |EG| |ED| |EL| Offset error Gain Error Differential linearity error Integral linearity error fCPU=8MHz, fADC=4MHz 1) Parameter Total unadjusted error Conditions Typ TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD LSB Unit
Notes:
1. Data based on characterization results over the whole temperature range, monitored in production.
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ADC CHARACTERISTICS (Cont'd) Figure 63. ADC Accuracy Characteristics
Digital Result ADCDR 1023 1022 1021 1LSB IDEAL V -V DD SS = ------------------------------EG
1024
(2) ET 7 6 5 4 3 2 1 0 VSS 1 2 3 4 1 LSBIDEAL EO EL ED (3) (1)
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first
Vin (LSBIDEAL)
5
6
7
1021 1022 1023 1024 VDD
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13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA Figure 64. 8-Lead Very thin Fine pitch Dual Flat No-Lead Package
D
INDEX AREA (D/2 x E/2) E
Dim. A A1 A3
TOP VIEW
mm Min 0.80 0.00 0.25 3.50 1.96 0.30 Typ 0.90 0.02 0.20 0.30 4.50 3.65 3.50 2.11 0.80 0.40 0.50 2.21 3.75 0.35 Max 1.00 0.05 Min
inches Typ Max 0.031 0.035 0.039 0.000 0.001 0.002 0.008 0.010 0.012 0.014 0.177 0.138 0.144 0.148 0.138 0.077 0.083 0.087 0.031 0.012 0.016 0.020 8 Number of Pins
b D D2
A3
A A1
SIDE VIEW
E E2 e L N
e
b
E2
INDEX AREA (D/2 x E/2) D2
BOTTOM VIEW
L
Figure 65. 8-Pin Plastic Small Outline Package, 150-mil Width
D h x 45
Dim. A A1 A2 B C D E e
mm Min 1.35 0.10 1.10 0.33 0.19 4.80 3.80 1.27 5.80 0.25 0d 0.40 6.20 0.228 0.50 0.010 8d 1.27 0.016 Typ Max Min 1.75 0.053 0.25 0.004 1.65 0.043 0.51 0.013 0.25 0.007 5.00 0.189 4.00 0.150
inches Typ Max 0.069 0.010 0.065 0.020 0.010 0.197 0.158 0.050 0.244 0.020 0.050
A2 A A1 B L
C
E
H
H h L
Number of Pins
e
N
8
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Figure 66. 8-Pin Plastic Dual In-Line Package, 300-mil Width
E
Dim.
A2 A1 L b2 b e D1 D D b3 eB
c
mm Min 0.38 2.92 0.36 1.14 0.76 0.20 9.02 0.13 2.54 10.92 7.62 6.10 2.92 7.87 6.35 3.30 3.30 0.46 1.52 0.99 0.25 Typ Max 5.33 0.015 Min
inches Typ Max 0.210
A
A A1 A2 b b2 b3 c D D1 e eB
4.95 0.115 0.130 0.195 0.56 0.014 0.018 0.022 1.78 0.045 0.060 0.070 1.14 0.030 0.039 0.045 0.36 0.008 0.010 0.014 0.005 0.100 0.430 8.26 0.300 0.310 0.325 7.11 0.240 0.250 0.280 3.81 0.115 0.130 0.150 8
9.27 10.16 0.355 0.365 0.400
8
5 E1
E E1 L N
1
4
Number of Pins
Figure 67. 16-Pin Plastic Dual In-Line Package, 300-mil Width
mm Min 0.38 2.92 0.36 1.14 0.76 0.20 0.13 2.54 7.62 6.10 2.92 7.87 6.35 3.30 3.30 0.46 1.52 0.99 0.25 Typ Max 5.33 0.015 4.95 0.115 0.130 0.195 0.56 0.014 0.018 0.022 1.78 0.045 0.060 0.070 1.14 0.030 0.039 0.045 0.36 0.008 0.010 0.014 0.005 0.100 8.26 0.300 0.310 0.325 7.11 0.240 0.250 0.280 3.81 0.115 0.130 0.150 10.92 Number of Pins N 16 0.430 Min inches Typ Max 0.210
Dim.
E
A
A2 A1 A
A1 A2 b
c E1
L
b2 b3 c D D1 e E E1 L eB
b2 D1 b3
b e
eB
D
18.67 19.18 19.69 0.735 0.755 0.775
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Figure 68. THERMAL CHARACTERISTICS
Symbol Ratings DIP8 RthJA Package thermal resistance (junction to ambient) Maximum junction temperature 1) DIP8 PDmax Power dissipation 2) SO8 DFN8 (on 4-layer PCB) DFN8 (on 2-layer PCB) SO8 DFN8 (on 4-layer PCB) DFN8 (on 2-layer PCB) Value TBD TBD 50 106 150 300 180 500 250 mW C C/W Unit
TJmax
Notes:
1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT where PINT is the chip internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the application.
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13.2 SOLDERING INFORMATION In accordance with the RoHS European directive, all STMicroelectronics packages will be converted in 2005 to lead-free technology, named ECOPACKTM (for a detailed roadmap, please refer to PCN CRP/04/744 "Lead-free Conversion Program - Compliance with RoHS", issued November 18th, 2004). TM ECOPACK packages are qualified according to the JEDEC STD-020C compliant soldering profile. Detailed information on the STMicroelectronics ECOPACKTM transition program is available on www.st.com/stonline/leadfree/, with specific technical Application notes covering the main technical aspects related to lead-free conversion (AN2033, AN2034, AN2035, AN2036). Backward and forward compatibility: The main difference between Pb and Pb-free soldering process is the temperature range. - ECOPACKTM TQFP, SDIP, SO and DFN8 packages are fully compatible with Lead (Pb) containing soldering process (see application note AN2034) - TQFP, SDIP and SO Pb-packages are compatible with Lead-free soldering process, nevertheless it's the customer's duty to verify that the Pbpackages maximum temperature (mentioned on the Inner box label) is compatible with their Leadfree soldering temperature.
Table 21. Soldering Compatibility (wave and reflow soldering process)
Package SDIP & PDIP DFN8 TQFP and SO Plating material devices Sn (pure Tin) Sn (pure Tin) NiPdAu (Nickel-palladium-Gold) Pb solder paste Yes Yes Yes Pb-free solder paste Yes * Yes * Yes *
* Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label) is compatible with their Lead-free soldering process.
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14 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). ST7PLITEUS2 and ST7PLITEUS5 devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory-programmed XFlash devices. ST7FLITEUS2 and ST7FLITEUS5 XFlash devices are shipped to customers with a default program memory content (FFh). The FASTROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the FASTROM devices are factory-configured.
14.1 OPTION BYTES The two option bytes allow the hardware configuration of the microcontroller to be selected. The option bytes can be accessed only in programming mode (for example using a standard ST7 programming tool). OPTION BYTE 1 Bit 7:6 = CKSEL[1:0] Start-up clock selection. This bit is used to select the startup frequency. By default, the Internal RC is selected.
Configuration Internal RC as Startup Clock AWU RC as a Startup Clock Reserved External Clock on pin PA5 CKSEL1 CKSEL0 0 0 1 1 0 1 0 1
Bit 0 = WDG HALT Watchdog Reset on Halt This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode OPTION BYTE 0 Bits 7:4 = Reserved, must always be 1. Bit 3 = Reserved, must always be 0. Bit 2 = SEC0 Sector 0 size definition This option bit indicates the size of sector 0 according to the following table.
Sector 0 Size 0.5k SEC0 0 1
Bit 5 = Reserved, must always be 1. Bit 4 = Reserved, must always be 0. Bits 3:2 = LVD[1:0] Low Voltage Detection selection These option bits enable the LVD block with a selected threshold as shown in Table 22. Table 22. LVD Threshold Configuration
Configuration LVD Off Highest Voltage Threshold Medium Voltage Threshold Lowest Voltage Threshold LVD1 LVD0 1 1 0 0 1 0 1 0
1k
Bit 1 = FMP_R Read-out protection Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first, and the device can be reprogrammed. Refer to Section 4.5 and the ST7 Flash Programming Reference Manual for more details. 0: Read-out protection off 1: Read-out protection on Bit 0 = FMP_W FLASH write protection This option indicates if the FLASH program memory is write protected. Warning: When this option is selected, the program memory (and the option bit itself) can never be erased or programmed again. 0: Write protection off 1: Write protection on
Bit 1 = WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software)
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OPTION BYTES (Cont'd)
OPTION BYTE 0 7 Reserved Default Value 1 1 1 1 0 0 7 SEC FMP FMP CKS CKS 0 R W EL1 EL0 0 0 0 0 0
OPTION BYTE 1 0 Res 1 WDG WDG Res LVD1 LVD0 SW HALT 0 1 1 1 1
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14.2 ORDERING INFORMATION Customer code is made up of the FASTROM contents and the list of the selected options (if any). The FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Table 23. Supported part numbers
Part Number ST7FLITEUS2B6 ST7FLITEUS2M6 ST7FLITEUS2U6 ST7FLITEUS5B6 ST7FLITEUS5M6 ST7FLITEUS5U6 ST7FLITEUSICD ST7PLITEUS2B6 ST7PLITEUS2M6 ST7PLITEUS2U6 ST7PLITEUS5B6 ST7PLITEUS5M6 ST7PLITEUS5U6 Contact ST sales office for product availability Note 1: For development or tool prototyping purposes only, not orderable in production quantities. 1K FASTROM 128 1K FASTROM 128 1K FLASH 128 1K FLASH 128 1K FLASH 128 Program Memory (Bytes) RAM (Bytes) ADC 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C Temp. Range Package DIP8 SO8 DFN8 DIP8 SO8 DFN8 DIP16 1) DIP8 SO8 DFN8 DIP8 SO8 DFN8
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ST7LITEUS FASTROM MICROCONTROLLER OPTION LIST (Last update: December 2005) Customer Address .......................................................................... .......................................................................... .......................................................................... Contact .......................................................................... Phone No .......................................................................... Reference FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): --------------------------------- | | ----------------------------------------1K FASTROM FASTROM DEVICE: --------------------------------- | | ----------------------------------------PDIP8: || [] SO8: || [] DFN8: || []
Conditioning (check only one option): [ ] Tape & Reel (SO and DFN packages) [ ] Tube (SO and DIP packages only) [ ] Tray (DFN package only)
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ " Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: PDIP8/SO8/DFN8 (8 char. max) : _ _ _ _ _ _ _ _ Clock Source Selection: [ ] External Clock [ ] AWU RC Oscillator [ ] Internal RC Oscillator [ ] 0.5K [ ] Disabled [ ] Disabled [ ] Disabled [ ] 1K [ ] Enabled [ ] Enabled [ ] Highest threshold [ ] Medium threshold [ ] Lowest threshold
Sector 0 size: Readout Protection: FLASH Write Protection LVD Reset
Watchdog Selection: Watchdog Reset on Halt:
[ ] Software Activation [ ] Disabled
[ ] Hardware Activation [ ] Enabled
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes .......................................................................... Date: .......................................................................... Signature: .......................................................................... Important note: Not all configurations are available. See section 14.1 on page 95 for authorized option byte combinations.
Please download the latest version of this option list from: http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list
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14.3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtained from the STMicroelectronics Internet site: http//www.st.com. Tools from these manufacturers include C compliers, evaluation tools, in-circuit debuggers, emulators and programmers. In-Circuit Debugging Tools Two types of debuggers are available for the ST7LITEUSx family:
ST7FLITE-SK/RAIS Low-cost in-circuit debugging/programming tool from Raisonance.
STXF-INDART/USB Low-cost in-circuit debugging tool from Softec Microsytem. Emulator One type of emulator is available from ST for the ST7LITEUSx family:
ST7 EMU3 high-end emulator is delivered with everything (probes, TEB, adapters etc.) needed to start emulating the ST7LITEUSx. To configure it to emulate other ST7 subfamily devices, the active probe for the ST7EMU3 can be changed and the ST7EMU3 probe is designed for easy interchange of TEBs (Target Emulation Board). See Table 24. Flash Programming tools ST7-STICK ST7 In-circuit Communication Kit, a complete software/hardware package for programming ST7 Flash devices. It connects to a host PC parallel port and to the target board or socket board via ST7 ICC connector. ICC Socket Boards provide an easy to use and flexible means of programming ST7 Flash devices. They can be connected to any tool that supports the ST7 ICC interface, such as ST7 EMU3, inDART, Rlink, ST7-STICK, or many third-party development tools.
Table 24. STMicroelectronics Development Tools
Emulation Supported Products Emulator ST7FLITEUS2 ST7FLITEUS5 ST7MDT10-EMU3 ST7 EMU3 series Active Probe & T.E.B. ST7MDT10-TEB Programming ICC Socket Board ST7SB10-SUO1)
Note 1: Add suffix /EU, /UK, /US for the power supply of your region.
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15 REVISION HISTORY
Date 06-Feb-06 Revision 1 Initial release Main changes
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Notes:
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