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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
D D D D D D D D
Advanced, Integrated Speech Synthesizer for High-Quality Sound Operates up to 12.32 MHz (Performs up to 12 MIPS) Very Low-Power Operation, Ideal for Hand-Held Devices Low-Voltage Operation, Sustainable by Three (3) Batteries Reduced Power Standby Modes, Less Than 10 A in Deep-Sleep Mode Supports High-Quality Synthesis Algorithms such as MELP, CELP, LPC, FM and ADPCM Slave Mode Enables Hours of Speech Using an External Processor and Memory Master Mode Allows 6.8 Mins of Speech Onboard
D D D D D D D D D D
16 General-Purpose I/O Pins (in Master Mode) or 4 General-Purpose I/O Pins (in Slave Mode) Resistor-Trimmed Oscillator or 32.768-kHz Crystal Reference Oscillator Slave Interface Logic Contains 32K-Words On-Board ROM (2K Words Reserved) 640-Word RAM Direct Speaker Drive (32 ) (PDM) One-Bit Comparator with Edge Detection Interrupt Service Serial Scan Port for In-Circuit Emulation, Monitor, and Test Available in Die Form or 64-Pin PM Package An Emulator Board (EPC50C604) is Available for Code Development in Slave Mode
description
The MSP50C604 ('C604) is a low-cost, mixed-signal processor that combines a speech synthesizer with a dedicated slave interface logic, general-purpose I/O, on-board ROM, and direct speaker-drive in a single package. The computational unit uses a powerful new DSP that gives the 'C604 unprecedented speed and computational flexibility compared with previous devices of its type. The 'C604 supports a variety of speech and audio coding algorithms, providing a range of options with respect to speech duration and sound quality. The device consists of a micro-DSP core, embedded program and data memory, and a self-contained clock generation system. General-purpose periphery is comprised of 16 bits of partially configurable I/O. The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block includes a computational unit (CU), data address unit, program address unit, two timers, eight-level interrupt processor, and several system and control registers. The core processor gives the 'C604 break-point capability in emulation. The processor is a Harvard type for efficient DSP algorithm execution, separating program and data memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is configured in 32K 17-bit words. The total ROM space is divided into two areas: 1) The lower 2K words are reserved by Texas Instruments for a built-in self-test 2) The upper 30K is for user program and data space. The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed to consume minimum power at a given system clock and algorithm acquisition frequency. A flexible clock generation system enables the software to control the clock over a wide frequency range. The implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced apart in 65.536-kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to provide different levels of power management.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
description (continued)
The periphery consists of two 8-bit-wide general-purpose I/O ports when operating in master mode, or four general-purpose I/O pins in slave mode. In the master mode, the bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole output. They are controlled via addressable I/O registers. These features make the input port especially useful as a key-scan interface. Slave mode consists of four general-purpose I/O, four control pins, and eight bidirectional data pins. A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register, and its access is shared with two pins in one general-purpose I/O port. Rounding out the 'C604 periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The following block diagram gives an overview of the 'C604 functionality.
functional block diagram
VSS 4 Scan Interface Break Point Emulation OTP Program Serial Comm. Power (EP)ROM Test-Area (reserved) User ROM INT vectors 32k x (16 + 1) bit 0x0000 to 0x07FF 0x0800 to 0x7FEF 0x7FF0 to 0x7FFF VDD 5 PG0 SCANIN G port O Data 0x2C MASTER/SLAVE
SCANOUT SCANCLK
Comparator 1 Bit: PD5 vs PD4 + - PD0 INRDY/PD0
SYNC TEST
SLAVE LOGIC
Core DACP DACM DAC 0x30 Instr. Decoder PCU RESET Initialization Logic CU TIMER1 OSC Reference Resistor Trimmed 32 kHz nominal OSCIN OSCOUT Crystal Referenced 32.768 kHz PLL PLL Filter or or Prog. Counter Unit Computational Unit PD3 PRD1 0x3A PRD2 0x3E TIM1 0x3B TIM2 0x3F 0x3D 0x38 C port I/O Data 0x10 Control 0x14 PA0-7 PC0-7 D port I/O Data 0x18 PD2 32 Ohm PDM
PD1 Int 3
OUTRDY/PD1
Control 0x1C Int 4
STROBE/PD2 R/W/PD3
PD4-7
TIMER2
Clock Control Gen. Control
Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data Mem. Addr.
BUS DRIVER PC0-7
A port I/O RAM 640 x 17 bit (data) Data 0x00 Control 0x04
LATCH
0x000 to 0x027F
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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
functional description
The 'C604 is a member of the MSP50C6xx family, which is based on the MSP50C614 core. For specific details about the core operations, instruction sets, register definitions, port configuration, etc., please consult the MSP50C614 user's guide (SPSU014). The 'C604 can be used as a slave synthesizer in slave mode or can operate stand-alone in master mode. The slave mode activates logic circuitry internal to the device that gives the device a dedicated slave interface. The slave or master mode is controlled by the bit 0 of the Port G (PG0). By default the device initially starts in slave mode. To change to master mode write a 0x01 to G port 0 (0x2C). To change back to slave mode write a 0x00 to port G bit 0 (0x2C).
master mode
In master mode, the slave logic circuitry is disabled and 'C604 has 16 general-purpose I/Os. These 16 input/output pins are organized as 2-byte-wide ports (C and D), initialized as inputs. Each of the pins can be configured as a totem-pole output or as a high-impedance input by setting or clearing the appropriate bit in the appropriate control register (0x14, 0x1C). When configured as an output, the data driven by the output pin can be controlled by setting or clearing the appropriate bit in the appropriate data register (0x10, 0x18). Whether configured as input or as output, reading the data port reads the actual state of the pin. External interrupts can be caused by transitions on pins PD2, PD3, PD4, and PD5 in the master mode. These interrupts are supported whether the pins are programmed as inputs or outputs.
slave mode
In slave mode, the slave logic circuitry is enabled allowing the device to have a dedicated slave interface. In this mode, only four pins of port D (PD4-PD7) are available as general-purpose I/O while the remaining pins (PD0-PD3) are redefined as INRDY, OUTRDY, STROBE and R/W. These pins are used to operate the slave interface. The 'C604 controls the INRDY and OUTRDY pins to let the external microcontroller know when the slave is ready to accept or transmit data. The external microcontroller controls the R/W and STROBE pins of 'C604 to sequence the read/write data flow. Each read or write sequence generates an interrupt that needs to be serviced by an interrupt service routine. These interrupt service routines need to be written by the code developer. The INT3 interrupt service routine indicates that the host has completed the write sequence, and the slave should read the data from port A. The INT4 interrupt service routine indicates the host has completed the read sequence. An interrupt is not generated when a read/write is done on port G bit 0 (PG0). The slave interface consists of:
D D D D
8-bit bidirectional data bus (PC0 - PC7) 2 status outputs: INRDY/PD0, and OUTRDY/PD1 2 control inputs: STROBE/PD2, and R/W/PD3 4 general-purpose I/Os (PD4-PD7)
Port C is used as an 8-bit bidirectional data bus. When data is to be sent to the host, it needs to be written to port C data register (0x10). When data is read from the host, it needs to be read from port A data register (0x00). Port A pins are not physically brought outside the device but are internally connected with the pins of port C.
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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
pin assignments
SIGNAL PC0 - PC7 PD4- PD7 PD0/INRDY PD1/OUTRDY PD2/STROBE PD3/R/W PIN NUMBER 39 32 43 40 6 5 4 3 PAD NUMBER 25 18 29 26 6 5 4 3 I/O I/O I/O I/O O I/O O I/O I I/O I DESCRIPTION Port C general-purpose I/O (1 Byte) Port D general-purpose I/O (1 Nibble) (Master) Port D general-purpose I/O (Slave) INRDY output to host (Master) Port D general-purpose I/O (Slave) OUTRDY output to host (Master) Port D general-purpose I/O (Slave) STROBE input from host (Master) Port D general-purpose I/O (Slave) Read/write input from host Input/Output Ports
Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set. Please refer to Section 3.3, Comparator, in the MSP50C614 User's Guide (SPSU014) for details. Scan Port Control Signals SCANIN SCANOUT SCANCLK SYNC TEST 11 8 10 9 7 11 8 10 9 7 I O I I I Scan port data input Scan port data output Scan port clock Scan port synchronization 'C604 test modes
The Scan Port pins must be bonded out on any 'C604 production board. Please consult the Important Note regarding Scan Port Bond Out, see Chapter 7 in the MSP50C614 User's Guide (SPSU014). Oscillator Reference Signals OSCOUT OSCIN PLL DACP DACM RESET 15 14 13 47 45 12 15 14 13 33 31 12 O I O O O Initialization I Initialization Power Signals Resistor/crystal reference out Resistor/crystal reference in Phase-lock-loop filter Digital-to-analog output 1 (+) Digital-to-analog output 2 (-)
DAC Sound Output
VSS 16, 48, 49, 64 16, 34, 35, 36 Ground VDD 1, 2, 31, 44, 46 1, 2, 17, 30, 32 Processor power (+) VSS and VDD connections service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor across these pins is therefore required.
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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
pin assignments
PM PACKAGE (TOP VIEW)
VDD VDD3
R/W STROBE OUTRDY INRDY
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
V SS NC NC NC NC NC NC NC NC NC NC NC NC NC
NC V SS2 VSS1 DACP VDD2 DACM VDD1 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 DATA/COMMAND PC5 PC6 PC7
TEST SCANOUT SYNC SCANCLK SCANIN RESET PLL OSCIN OSCOUT VSS
10 11 12 13 14 15
33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC NC NC NC NC NC NC NC NC NC NC NC NC NC V DD
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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
system initialization sequence in the slave mode
D D
Initialize the host processor first. The host must hold the slave RESET pin low until the slave STROBE pin can be held high by the host throughout the slave initialization process.
The INRDY and OUTRDY pins are set high by the slave on the rising edge of the slave RESET pin. slave mode software initialization
D D D D
Write 0x00 to port A (0x00), port C (0x10), port D (0x18) data registers. Configure the port C (PC0-PC7), port D0, and port D1 as output ports. (Write 0xFF to port C (0x14) and 0x03 to port D (0x1C) control registers) Configure port A (PA0-PA7), PORT D2, and port D3 as input ports (default at reset). Write 0x00 to port A (0x04) and 0x03 to port D (0x1C) control registers. After the slave completes its initialization, the slave needs to inform the host that it is ready to read or write data.
NOTE: The default mode for the MSP50C604 is the slave mode. The 'C604 can be set to master mode by writing a 1 to port G bit 0. This is an internal bit that is not available on the 'C604 external pins. NOTE: The initialization sequence given previously is a specific requirement for setting up the 'C604 in slave mode. For the basic initialization requirements of the device, please refer to the MSP50C614 user's guide (SPSU014).
write to slave in the slave mode
D D D D D D D D D D D D D
The slave indicates it is ready to receive data from the host by dropping INRDY low. This is done by writing low-high-low to port D (0x18) bit 0 (PD0). On the falling edge of the internal PD0 pulse, INRDY toggles low, notifying the host that the slave is ready to receive data. The host writes data to the slave by setting R/W low and then pulsing the STROBE high-low-high. The slave latches the data on the rising edge of the STROBE pulse and sets INRDY high. An INT3 interrupt is generated as INRDY goes high completing the write cycle. The latched data is read by the slave through port A (0x00) data register.
read from slave in the slave mode When the slave has data for the host, it places the data in port C (0x10). The slave then indicates that the data is ready by dropping OUTRDY low. This is done by writing low-high-low to port D (0x18) bit 1 (PD1). On the falling edge of the internal PD1 pulse, OUTRDY toggles low notifying the host that the slave is ready to send data. The host responds by setting R/W high and then pulsing STROBE high-low-high. The host should latch the data before raising STROBE high. This informs the slave that the data has been written to the host. The OUTRDY is pulled high by the slave at the rising edge of STROBE. An INT4 interrupt is generated as OUTRDY goes high completing the read cycle.
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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 7 V Supply current, IDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to VDD + 0.3 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to VDD + 0.3 V Storage temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise noted, all voltages are measured with respect to VSS . 2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device.
recommended operating conditions
PARAMETER TEST CONDITIONS MIN MAX UNIT
VDD VIH
Supply voltage (with respect to VSS) VDD = 3 V High-level input voltage VDD = 4.5 V VDD = 5.2 V VDD = 3 V
3.0 2 3 3.5 0 0 0
5.2 3.3 4.8 5.2 1 1.5 1.7 -2 5 -10 20
V V
VIL IOH IOL IOL(DAC) f(CPU) R(DAC) TA
Low-level input voltage High-level output current (per pin of I/O port) Low-level output current (per pin of I/O port) Low-level output DAC current CPU clock rate (as programmed) Resistance between DACP and DACM Operating free-air temperature
VDD = 4.5 V VDD = 5.2 V VDD = 4.5 V, VOH = 4 V VDD = 4.5 V, VOL = 0.5 V VDD = 4.5 V, VOH = 4 V VDD = 4.5 V, VOL = 0.5 V
V mA mA mA mA kHz C
IOH(DAC) High-level output DAC current
64 12,320 32 Device functionality 0 70
This parameter cannot exceed 15 mA total per internal VDD pin. Port C and port D share 1 internal VDD. Ports A and G0 are used internally.
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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
dc electrical characteristics, TA = 25C
PARAMETER VDD = 3 V RESET Threshold changes VDD = 5.2 V Input leakage current Standby current Operating current Supply current Input offset voltage F port pullup resistance Trim deviation Voltage deviation Temperature deviation Resistance deviation TEST CONDITIONS Positive going threshold Negative going threshold Hysteresis Positive going threshold Negative going threshold Hysteresis Ilkg I(STANDBY) IDD I(SLEEP-deep) I(SLEEP-mid) I(SLEEP-light) VIO R(PULLUP) f(RTO t i ) (RTO-trim) f(RTO lt) (RTO-volt) f(RTO t (RTO-temp) ) f(RTO ) (RTO-res) Excludes OSCIN RESET is low VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 5 V RRTO = 470 k, VDD = 4.5 V, TA = 25C, fRTO = 8.192 MHz (PLL setting = 7 Ch) RRTO = 470 k, VDD = 3.5 to 5.2 V, fRTO = 8.192 MHz (PLL setting = 7 Ch) RRTO = 470 k, FCLOCK = 12.32 MHz DAC off, ARM set, DAC off, DAC off, ARM set, ARM clear, OSC disabled OSC enabled OSC enabled 0.05 15 0.05 40 60 25 70 150 2 TA = 25C, 3 1 5 1.5 -0 1 0.1 1 0.1 01 10 60 100 50 mV k % %/V %/C %/R A MIN TYP 2.4 1.8 0.6 3.3 2.9 0.4 1 10 A A mA V V MAX UNIT
Vref = 1 to 4.25 V
VDD = 4.5 V, TA = 0 to 70C, fRTO = 8.192 MHz (PLL setting = 7 Ch) VDD = 4.5 V, TA = 25C, ROSC = 470 k @ 1%, fRTO = 8.192 MHz (PLL setting = 7 Ch)
Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
external component absolute values
PARAMETER R(RTO) C(PLL) RTO external resistance PLL external capacitance TA = 25C, TA = 25C, TEST CONDITIONS 1% tolerance 10% tolerance MIN MAX 470 3300 UNIT k pF
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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
timing requirements
PARAMETER t(RESET) t1(WIDTH) t2(WIDTH) Reset pulsed low, while 'C604 has power applied Pulse width required prior to a negative transition at pin (PD3, PD5, or PF0...PF7 interrupt) Pulse width required prior to a positive transition at pin (PD2 or PD4 interrupt) MIN 100 2 2 MAX UNIT ns 1/FCPU 1/FCPU
Figure 1. Initialization Timing Diagram
RESET
tRESET
Figure 2. MSP50P604 External Interrupt Pin Pulse Width Requirements t1WIDTH and t2WIDTH
t1WIDTH (PD3, PD5, or F port)
t1WIDTH t2WIDTH (PD2, or PD4)
t2WIDTH
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MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
timing diagram
D0 D1 1 1
INRDY tIS
2
7 tSI 2 7 tOS tSO
OUTRDY
R/W
3 tSR 4 tST 6
3 tSR 4 tST 6
tRS
tRS
STROBE INT3
8
INT4 tS tH Data New Data tDV
8
Write to Slave 1. Slave signals readiness to receive data from host. 2. Slave drops INRDY. 3. Host drops R/W to indicate a write. 4. Host drops STROBE. 5. Host places data on the bus. 6. Host raises STROBE indicating data is valid. 7. Slave raises INRDY, latching the data. 8. INT3 is triggered when INRDY rises.
INRDY low to STROBE low R/W to STROBE low STROBE low STROBE high to R/W STROBE high to INRDY high Data setup Data hold
10
CCCCCCCCCCCCCCCCCCCCCCCCCC C C CCCCCCCCCCCCCCCCCCCCCCCCCC C C
Valid Data
5
5
Read from Slave 1. Slave signals readiness to send data to host. 2. Slave drops OUTRDY. 3. Host raises R/W to indicate a read. 4. Host drops STROBE. 5. Slave places data on the bus. 6. Host raises STROBE after reading the data. 7. Slave raises OUTRDY. 8. INT4 is triggered when OUTRDY rises.
Table 1. Timing Constrains
Write to Slave tIS (min) = 5 ns tRS (min) = 75 ns tST (min) = 100 ns tSR (min) = 25 ns tSI (max) = 75 ns tS (min) = 15 ns tH (min) = 80 ns R/W to STROBE low STROBE low STROBE high to R/W STROBE high to OUTRDY high STROBE Low to data valid STROBE High to data high Z Read from Slave OUTRDY low to STROBE low tOS (min) = 5 ns tRS (min) = 75 ns tST (min) = 100 ns tSR (min) = 25 ns tSO (max) = 75 ns tDV (max) = 90 ns tDZ (min) = 90 ns
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CCC CCC
tDZ
EEEEEE EEEEEE
CCCC CCCC
MSP50C604 MIXED-SIGNAL PROCESSOR
SPSS028A - MAY 2000 - REVISED JUNE 2000
MECHANICAL DATA
PM (S-PQFP-G64)
0,27 0,17 48 33
PLASTIC QUAD FLATPACK
0,50
0,08 M
49
32
64
17 0,13 NOM
1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,45 1,35
16 Gage Plane
0,25 0,05 MIN 0- 7
0,75 0,45
Seating Plane 1,60 MAX 0,08 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads.
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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