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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
D D D D D D D D D
1.65-V to 5.5-V VCC Operation Useful for Both Analog and Digital Applications Specified Break-Before-Make Switching Rail-to-Rail Signal Handling High Degree of Linearity High Speed, Typically 0.5 ns (VCC = 3 V, CL = 50 pF) Low On-State Resistance, Typically 6 (VCC = 4.5 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
DBV OR DCK PACKAGE (TOP VIEW)
B2 GND B1
1 2 3
6 5 4
S VCC A
YEP OR YZP PACKAGE (BOTTOM VIEW)
B1 GND B2
34 25 16
A VCC S
description/ordering information
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of up to VCC (peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION
TA PACKAGE NanoStar - WCSP (DSBGA) 0.23-mm Large Bump - YEP -40C to 85C NanoFree - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) SOT (SOT-23) - DBV SOT (SC-70) - DCK ORDERABLE PART NUMBER SN74LVC1G3157YEPR Tape and reel SN74LVC1G3157YZPR Tape and reel Tape and reel SN74LVC1G3157DBVR SN74LVC1G3157DCKR CC5_ C5_ C5 _ _ _C5_ TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. FUNCTION TABLE CONTROL INPUT S L H ON CHANNEL B1 B2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
logic diagram (positive logic)
B2
1 6
S
4
A
B1
3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Switch I/O voltage range, VI/O (see Notes 1, 2, 3, and 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA I/O port diode current, IIOK (VI/O < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA On-state switch current, II/O (VI/O = 0 to VCC) (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 6): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 5.5 V maximum. 4. VI, VO, VA, and VBn are used to denote specific conditions for VI/O. 5. II, IO, IA, and IBn are used to denote specific conditions for II/O. 6. The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
recommended operating conditions (see Note 7)
MIN VCC VI/O VIN VIH VIL High-level High level input voltage control input voltage, Low-level Low level input voltage, control input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.65 0 0 VCC x 0.75 VCC x 0.7 VCC x 0.25 VCC x 0.3 20 20 10 10 ns/V MAX 5.5 VCC 5.5 UNIT V V V V V
t/v
Input transition rise/fall time
TA -40 85 C NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VI = 0 V VI = 1.65 V VI = 0 V VI = 2.3 V VI = 0 V VI = 3 V VI = 0 V VI = 2.4 V VI = 4.5 V On-state switch resistance over signal range 0 VBn VCC (see Figures 1 and 2) IO= 4 mA IO = -4 mA IO = 8 mA IO = -8 mA IO = 24 mA IO = -24 mA IO = 30 mA IO = -30 mA IO = -30 mA IA = -4 mA IA = -8 mA IA = -24 mA IA = -30 mA IA = -4 mA IA = -8 mA IA = -24 mA IA = -30 mA IA = -4 mA IA = -8 mA IA = -24 mA IA = -30 mA Ioffk IS(on) S( ) IIN ICC ICC Cin Cio(off) Cio(on) Off-state Off state switch leakage current On state switch leakage current On-state Control input current Supply current Supply-current change Control input capacitance Switch input/output capacitance Switch input/output capacitance S Bn Bn A 0 VI, VO VCC, (see Figure 3) VI = VCC or GND, , VO = Open (see Figure 4) 0 VIN VCC VIN = VCC or GND VIN = VCC - 0.6 V VCC 1.65 1 65 V 2.3 23V 3V MIN TYP 11 15 8 11 7 9 6 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 55V 5.5 0 V to 5.5 V 5.5 V 5.5 V 5V 5V 5V 2.7 5.2 17.3 17.3 0.5 0.1 0.1 0.1 110 26 9 4 0.05 1 1 1 0.1 0.05 1 1 1 10 500 A A A A A pF pF pF 7 7 MAX 20 50 12 30 9 20 7 12 15 140 45 18 10 UNIT
ron
On-state switch resistance
S See Figures 1 and 2
rrange
ron
Difference of on-state resistance between switches#
See Figure 1
VBn = 1.15 V VBn = 1.6V VBn = 2.1 V VBn = 3.15 V
ron(flat) (fl t)
ON resistance flatness||
0 VB VCC Bn
TA = 25C Measured by the voltage drop between I/O pins at the indicated current through the switch. ON resistance is determined by the lower of the voltages on the two (A or B) ports. Specified by design ron = ron(max) - ron(min) measured at identical VCC, temperature, and voltage levels. # This parameter is characterized, but not tested in production. || Flatness is defined as the difference between the maximum and minimum values of ON resistance over the specified range of conditions. k Ioff is the same as IS(off) (off-state switch leakage current).
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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
analog switch characteristics, TA = 25C
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS RL = 50 , fin = sine wave i (see Figure 6) VCC 1.65 V Frequency response q y (switch on) A or Bn Bn or A 2.3 V 3V 4.5 V 1.65 V Crosstalk (between switches) B1 or B2 B2 or B1 RL = 50 , fin = 10 MHz (sine wave) i (see Figure 7) 2.3 V 3V 4.5 V 1.65 V Feed-through attenuation g (switch off) A or Bn Bn or A CL = 5 pF, RL = 50 , fin = 10 MHz (sine wave) i (see Figure 8) CL = 0.1 nF, RL = 1 M, , , (see Figure 9) VI = 0.5 V p-p, RL = 600 05 , fin = 600 Hz to 20 kHz (sine wave) (see Figure 10) ( Fi 2.3 V 3V 4.5 V Charge injection Ch i j ti S A 3.3 V 5V 1.65 V 2.3 V 3V 4.5 V TYP 300 300 300 300 -54 -54 -54 -54 -57 -57 -57 -57 3 7 0.1 0.025 0.015 0.01 % pC dB dB MHz UNIT
Total harmonic distortion
A or Bn
Bn or A
Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads -3 dB. Adjust fin voltage to obtain 0 dBm at input. Specified by design
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 5 and 11)
PARAMETER tpd ten# tdis|| FROM (INPUT) A or Bn S TO (OUTPUT) Bn or A Bn 7 3 VCC = 1.8 V 0.15 V MIN MAX 2 24 13 3.5 2 VCC = 2.5 V 0.2 V MIN MAX 1.2 14 7.5 2.5 1.5 VCC = 3.3 V 0.3 V MIN MAX 0.8 7.6 5.3 1.7 0.8 VCC = 5 V 0.5 V MIN MAX 0.3 5.7 3.8 ns ns UNIT
tB-Mk 0.5 0.5 0.5 0.5 ns tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). # ten is the slower of tPZL or tPZH. || tdis is the slower of tPLZ or tPHZ. k Specified by design
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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC SW 1 S VCC B1 1 SW B2 A VI = VCC or GND GND 2 VO 2 S VIL VIH
VIL or VIH
IO V VI - VO r on
+ V *V I
I O
O
W
Figure 1. On-State Resistance Test Circuit
120 VCC = 1.65 V 100
80
ron
60
40 VCC = 2.3 V 20 VCC = 3 V VCC = 4.5 V 0 0 1 2 VI - V 3 4 5
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC SW 1 S VCC B1 1 SW B2 VI A A GND 2 VO 2 S VIL VIH
VIL or VIH
Condition 1: VI = GND, VO = VCC Condition 2: VI = VCC, VO = GND
Figure 3. Off-State Switch Leakage-Current Test Circuit
VCC
SW 1
S VIL VIH
VIL or VIH
S
VCC B1 1 SW B2 2
2
VO VO = Open
VI
A
A GND
VI = VCC or GND
Figure 4. On-State Switch Leakage-Current Test Circuit
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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
S1 VLOAD Open GND RL TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND
From Output Under Test CL (see Note A)
RL
LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI VCC VCC VCC VCC tr/tf 2 ns 2 ns 2.5 ns 2.5 ns VM VCC/2 VCC/2 VCC/2 VCC/2 VLOAD 2 x VCC 2 x VCC 2 x VCC 2 x VCC CL 50 pF 50 pF 50 pF 50 pF RL 500 500 500 500
V 0.3 V 0.3 V 0.3 V 0.3 V VI
Timing Input tw VI Input VM VM 0V VOLTAGE WAVEFORMS PULSE DURATION VI Input tPLH Output tPHL VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH Output VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VM tPZH VM Data Input tsu VM
VM 0V th VI VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM VM 0V tPLZ VLOAD/2 VOL + V tPHZ VOH - V VOH 0 V VOL
Output Waveform 1 S1 at VLOAD (see Note B)
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC SW 1 S VCC B1 1 SW B2 A GND fin 50 RL = 50 2 RL VO 2 S VIL VIH
VIL or VIH
Figure 6. Frequency Response (Switch On)
S VCC VIL VIH VIL or VIH S VCC B1 VB1 fin
TEST CONDITION 20log10(VO2/VI) 20log10(VO1/VI)
A B2 50 RL = 50 GND
VB2 Analyzer
RL
Figure 7. Crosstalk (Between Switches)
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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC
SW 1
S VIL VIH
VIL or VIH
S
VCC B1 1 SW
2
Analyzer A GND fin 50 RL = 50 B2 2 RL
Figure 8. Feed Through
VCC
S LOGIC INPUT
VCC B1 1 SW B2 2 RGEN
VGE
VOUT
A GND
RL
CL
RL/CL = 1 M/100 pF
LOGIC INPUT
OFF
ON
OFF
VOUT
VOUT
Q = (VOUT) (CL)
Figure 9. Charge-Injection Test
10
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SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424B - JANUARY 2003 - REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC SW 1 S VCC B1 1 SW B2 A GND fin 600 VCC/2 2 2 S VIL VIH 10 F VO CL 50 pF
VIL or VIH
RL 10 k
VCC = 1.65 V, VI = 1.4 VP-P VCC = 2.30 V, VI = 2.0 VP-P VCC = 3.00 V, VI = 2.5 VP-P VCC = 4.50 V, VI = 4.0 VP-P
Figure 10. Total Harmonic Distortion
VCC
S
VCC B1 VI = VCC/2
B2 VO A GND VS RL CL RL/CL = 50 /35 pF VO 0.9 x VO
tD
Figure 11. Break-Before-Make Internal Timing
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MECHANICAL DATA
MPDS026D - FEBRUARY 1997 - REVISED FEBRUARY 2002
DBV (R-PDSO-G6)
PLASTIC SMALL-OUTLINE
0,95 6 4
6X
0,50 0,25
0,20 M
1,70 1,50
3,00 2,60
0,15 NOM
1 3,00 2,80
3
Gage Plane
0,25 0-8 0,55 0,35
Seating Plane 1,45 0,95 0,05 MIN 0,10
4073253-5/G 01/02
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.
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MECHANICAL DATA
MPDS114 - FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,65 6 4
0,30 0,15
0,10 M
1,40 1,10
2,40 1,80
0,13 NOM
1 2,15 1,85
3
Gage Plane
0,15 0-8 0,46 0,26
Seating Plane 1,10 0,80 0,10 0,00 0,10
4093553-3/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-203
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MECHANICAL DATA
MXBG019 - OCTOBER 2002
YZP (R-XBGA-N6)
DIE-SIZE BALL GRID ARRAY
0,50 A 0,95 0,85 B 0,25
C 1,00 B 0,50 A 1 Pin A1 Index Area 6X 2 0,25 0,20 0,05 M C A B 0,05 M C
1,45 1,35
0,05 C 0,50 Max Seating Plane 0,20 0,15 C
4204741-3/A 10/2002 NOTES: A. B. C. NOTES: D. All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoFree package configuration. This package is lead-free. Refer to the 6 YEP package (drawing 4204725) for tin-lead (SnPb).
NanoFree is a trademark of Texas Instruments.
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MECHANICAL DATA
MXBG022 - OCTOBER 2002
YEP (R-XBGA-N6)
DIE-SIZE BALL GRID ARRAY
0,50 A 0,95 0,85 B 0,25
C 1,00 B 0,50 A 1 Pin A1 Index Area 6X 2 0,25 0,20 0,05 M C A B 0,05 M C
1,45 1,35
0,05 C 0,50 Max Seating Plane 0,20 0,15 C
4204725-3/A 10/2002 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoFree package configuration. This package is tin-lead (SnPb). Refer to the 6 YZP package (drawing 420741) for lead-free.
NanoFree is a trademark of Texas Instruments.
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