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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
D
D D
D D D D
Organization - TM2EP64DxN . . . 2 097152 x 64 Bits - TM2EP72DxN . . . 2 097152 x 72 Bits - TM4EP64DxN . . . 4 194304 x 64 Bits - TM4EP72DxN . . . 4 194304 x 72 Bits Single 3.3-V Power Supply (10% Tolerance) TM2EP64DxN -- Uses Eight 16M-Bit (2M x 8-Bit) Dynamic Random Access Memories (DRAMs) in Thin Small-Outline Package (TSOP), or Small-Outline J-Lead Package (SOJ) TM2EP72DxN -- Uses Nine 16M-Bit (2M x 8-Bit) DRAMs in TSOP, or SOJ TM4EP64DxN -- Uses 16 16M-Bit (2M x 8-Bit) DRAMs in TSOP, or SOJ TM4EP72DxN -- Uses 18 16M-Bit (2M x 8-Bit) DRAMs in TSOP, or SOJ Performance ranges
ACCESS ACCESS ACCESS TIME TIME TIME tRAC tCAC tAA MAX MAX MAX 50 ns 13 ns 25 ns 60 ns 15 ns 30 ns 70 ns 18 ns 35 ns EDO CYCLE tHPC MIN 20 ns 25 ns 30 ns
D D D D D D D D
JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket High-Speed, Low-Noise LVTTL Interface Long Refresh Period: 32 ms (2 048 Cycles) 3-State Output Extended-Data-Out (EDO) Operation With CAS-Before-RAS (CBR), RAS-Only, and Hidden Refresh Serial Presence Detect (SPD) Using EEPROM Ambient Air Temperature Range 0C to 70C Gold-Plated Contacts
'xEPxxDxN-50 'xEPxxDxN-60 'xEPxxDxN-70
description
The TM2EP64DPN is a 16M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of eight TMS427809A, 2 097 152 byte x 8-bit 2K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS887). The TM2EP64DJN is available with an SOJ package (DZ suffix). The TM2EP72DPN is a 16M-byte, 168-pin DIMM. The DIMM is composed of nine TMS427809A, 2 097 152 byte x 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS887). The TM2EP72DJN is available with an SOJ package (DZ suffix). The TM4EP64DPN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of sixteen TMS427809A, 2 097 152 x 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. The TM4EP64DJN is available with an SOJ package (DZ suffix). The TM4EP72DPN is a 32M-byte, 168-pin DIMM. The DIMM is composed of 18 TMS427809A, 2 097 152 x 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS887). The TM4EP72DJN is available with an SOJ package (DZ suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
operation
The TMxEPxxDxN DIMMs operate as displayed in Table 1. Table 1. TMxEPxxDxN DIMM Device Table
DIMM TM2EP64DxN TM2EP72DxN TM4EP64DxN TM4EP72DxN DEVICE AND QUANTITY ( ) TMS427809A (8) TMS427809A (9) TMS427809A (16) TMS427809A (18) C td h i th f ti l Connected as shown in the functional diagram. block diagram
2
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM2EP64DPN ( SIDE VIEW )
TM4EP72DPN ( SIDE VIEW )
PIN NOMENCLATURE A[0:10] A[0:9] DQ[0:63] CB[0:7] CAS[0:7] RAS[0:3] WE0 and WE2 OE0 and OE2 SA[0:2] SDA SCL NC VDD VSS Row Address Inputs Column Address Inputs Data In / Data Out Check-Bit In / Check-Bit Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial Presence Detect (SPD) Device Add Input SPD Address / Data SPD Clock No-Connect Pin 3.3-V Supply Ground
1
10 11
40
41
84
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SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
4 NO. 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 PIN NAME RAS0 CAS1 CAS0 DQ15 VDD DQ14 DQ13 DQ12 DQ10 DQ11 VDD WE0 VDD VDD VDD DQ4 VSS DQ9 DQ8 DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VSS DQ0 VSS A0 OE0 VSS NC CB1 CB0 A10 NC NC NC A8 A6 A4 A2
NO.
84
83
82
81
80
VSS 120 79AAAAAA 121 NC
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62AAAAAA 104 NC
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45AAAAAA 87 RAS2
44
43
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PIN NAME
Pin Assignments
DQ31
DQ30
DQ29
VDD DQ28
DQ27
DQ26
DQ25
VSS DQ24
DQ23
DQ22
VSS DQ21
VDD DQ20
DQ19
DQ18
DQ17
VSS DQ16
CAS3
CAS2
WE2
VDD
VDD NC
SDA
VSS OE2
SCL
CB3
CB2
NC
NC
NC
NC
NC
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NO. 126 125 124 123 122 109 108 107 106 105 103 102 101 100 119 118 117 116 115 114 113 112 110 111 99 98 97 96 95 94 93 92 91 90 89 88 86 85 PIN NAME RAS1 CAS5 CAS4 DQ47 VDD DQ46 DQ45 DQ44 DQ43 DQ42 VSS DQ41 DQ40 DQ39 DQ38 DQ37 VDD DQ36 DQ35 DQ34 DQ33 VSS DQ32 VDD NC VDD NC VSS A1 VSS NC CB5 CB4 NC NC NC NC A9 A7 A5 A3 NC NO. 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 PIN NAME DQ63 DQ62 DQ61 VDD DQ60 DQ59 DQ58 DQ57 VSS DQ56 DQ55 DQ54 VSS DQ53 VDD DQ52 DQ51 DQ50 DQ49 VSS DQ48 CAS7 CAS6 RAS3 VDD VDD NC VSS NC VSS NC CB7 CB6 SA2 SA1 SA0 NC NC NC NC NC NC
TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
D D D
PC substrate: 1,27
" 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
functional block diagram
The following table shows the four DIMM modules and locations (Ux/UBx) that are used.
COMPONENT TABLE MODULE TM2EP64DxN TM2EP72DxN TM4EP64DxN TM4EP72DxN LOCATIONS USED U[0:7] U[0:8] U[0:7], UB[0:7] U[0:8], UB[0:8]
RAS0 WE0 OE0 CAS0 DQ[0:7] CAS OE W RAS DQ[0:7] U0
RAS1 WE0 OE0 CAS OE W RAS DQ[0:7] UB0
RAS2 WE2 OE2 CAS4 DQ[32:39] CAS OE W RAS
RAS3 WE2 OE2 CAS OE W RAS DQ[0:7] UB4
DQ[0:7] U4
CAS1 DQ[8:15]
CAS OE W RAS DQ[0:7] U1
CAS OE W RAS DQ[0:7] UB1
CAS5 DQ[40:47]
CAS
OE W RAS
CAS OE W RAS DQ[0:7] UB5
DQ[0:7] U5
CAS1 CB[0:7]
CAS OE W RAS DQ[0:7] U8
CAS OE W RAS DQ[0:7] UB8
CAS6 DQ[48:55]
CAS
OE W RAS
CAS OE W RAS DQ[0:7] UB6
DQ[0:7] U6
CAS2 DQ[16:23]
CAS OE W RAS DQ[0:7] U2
CAS OE W RAS DQ[0:7] UB2
CAS7 DQ[56:63]
CAS
OE W RAS
CAS OE W RAS DQ[0:7] UB7
DQ[0:7] U7
CAS3 DQ[24:31]
CAS OE W RAS DQ[0:7] U3
CAS OE W RAS DQ[0:7] UB3
A[0: 10]
A[0 : 10] : U[0:8], UB[0:8]
SPD EEPROM SCL SDA A0 A1 A2
Legend: SPD = Serial Presence Detect
SA0 VDD
SA1
SA2
VSS
U[0:8], UB[0:8] Two 0.1 F (minimum) per DRAM U[0:8], UB[0:8]
6
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM2EP64DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W TM2EP72DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W TM4EP64DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W TM4EP72DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA
MIN 3 2 2 0 NOM MAX 3.6 UNIT V V V V V VDD VSS Supply voltage Supply voltage 3.3 0 VIH VIH - SPD VIL TA High-level input voltage Low-level input voltage Ambient temperature High-level input voltage for the SPD device VDD + 0.3 5.5 0.8 70 - 0.3 C
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(A) Ci(OE) Ci(CAS) Ci(RAS) Ci(W) Co Ci/o(SDA) Ci(SPD) Input capacitance, A0 - A10 Input capacitance, OEx Input capacitance, CASx Input capacitance, RASx Input capacitance, WEx Output capacitance Input/output capacitance, SDA input Input capacitance, SA0,SA1,SA2,SCL inputs '2EP64DxN MIN MAX 42 30 9 30 30 9 9 7 '2EP72DxN MIN MAX 47 37 16 37 37 9 9 7 '4EP64DxN MIN MAX 82 58 16 30 38 16 9 7 '4EP72DxN MIN MAX 92 72 30 37 37 16 9 7 UNIT pF pF pF pF pF pF pF pF
NOTE 2: VDD = NOM supply voltage 10%, and the bias on pins under test is 0 V.
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
TM2EP64DxN
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '2EP64DxN-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2EP64DxN-60 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2EP64DxN-70 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC1
VDD = 3.6 V,
Minimum cycle
960
800
720
mA
ICC2
Standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
16
16
16
mA
8
8
8
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current
960
800
720
mA
ICC4
880
720
640
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
8
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM2EP72DxN
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '2EP72DxN-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2EP72DxN-60 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2EP72DxN-70 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC1
VDD = 3.6 V,
Minimum cycle
976
816
736
mA
ICC2
Standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
18
18
18
mA
9
9
9
mA
ICC3
Average refresh current (RASx-only refresh or CBR) Average EDO current
976
816
736
mA
ICC4
990
810
720
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM4EP64DxN
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '4EP64DxN-50 MIN 2.4 VDD - 0.2 0.4 0.2 20 20 MAX '4EP64DxN-60 MIN 2.4 VDD- 0.2 0.4 0.2 20 20 MAX '4EP64DxN-70 MIN 2.4 V VDD - 0.2 0.4 V 0.2 20 20 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC1
VDD = 3.6 V,
Minimum cycle
976
816
736
mA
ICC2
Standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
32
32
32
mA
16
16
16
mA
ICC3
Average refresh current (RASx-only refresh or CBR) Average EDO current
976
816
736
mA
ICC4
896
736
656
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
10
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM4EP72DxN
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '4EP72DxN-50 MIN 2.4 VDD - 0.2 0.4 0.2 20 20 MAX '4EP72DxN-60 MIN 2.4 VDD - 0.2 0.4 0.2 20 20 MAX '4EP72DxN-70 MIN 2.4 V VDD - 0.2 0.4 V 0.2 20 20 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC1
VDD = 3.6 V,
Minimum cycle
1098
918
828
mA
ICC2
Standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
36
36
36
mA
18
18
18
mA
ICC3
Average refresh current (RASx-only refresh or CBR) Average EDO current
1098
918
828
mA
ICC4
1008
828
738
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
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11
TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3)
PARAMETER tAA tCAC tCPA tRAC tOEA tCLZ tREZ tCEZ tOEZ tWEZ Access time from column address (see Note 4) Access time from CASx (see Note 4) Access time from CASx precharge (see Note 4) Access time from RASx (see Note 4) Access time from OEx (see Note 4) Delay time, CASx to output in low impedance Output buffer turn off delay from RASx (see Note 5) Output buffer turn off delay from CASx (see Note 5) Output buffer turn off delay from OEx (see Note 5) Output buffer turn off delay from WEx (see Note 5) 0 3 3 3 3 13 13 13 13 'xEP64DxN-50 'xEP72DxN-50 MIN MAX 25 13 28 50 13 0 3 3 3 3 15 15 15 15 'xEP64DxN-60 'xEP72DxN-60 MIN MAX 30 15 35 60 15 0 3 3 3 3 18 18 18 18 'xEP64DxN-70 'xEP72DxN-70 MIN MAX 35 18 40 70 18 ns ns ns ns ns ns ns ns ns ns UNIT
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
'xEP64DxN-50 'xEP72DxN-50 MIN tHPC tPRWC tCSH tCHO tDOH tOEP tCAS tWPE tCP tOCH Cycle time, EDO page mode, read-write Cycle time, EDO read-write Delay time, RASx active to CASx precharge Hold time, OEx from CASx Hold time, output from CASx Precharge time, OEx Pulse duration, CASx active Pulse duration, WEx active (output disable only) Pulse duration, CASx precharge Setup time, OEx before CASx 20 57 40 7 5 5 8 7 8 8 5 10 000 MAX 'xEP64DxN-60 'xEP72DxN-60 MIN 25 68 48 10 5 5 10 7 10 10 5 10 000 MAX 'xEP64DxN-70 'xEP72DxN-70 MIN 30 78 58 10 5 5 12 7 10 10 5 10 000 MAX ns ns ns ns ns ns ns ns ns ns ns UNIT
tOEP Precharge time, OEx NOTE 3: With ac parameters, it is assumed that tT = 2 ns.
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
ac timing requirements
'xEP64DxN-50 'xEP72DxN-50 MIN tRC tRWC tRASP tRAS tRP tWP tRASS tRPS tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tCSR tCAH tDH tRAH tRCH tRRH tWCH tROH tWRH tCHR tOEH tRHCP tCHS tAWD Cycle time, random read or write Cycle time, read-write Pulse duration, RASx active, fast page mode (see Note 6) Pulse duration, RASx active, non-page mode (see Note 6) Pulse duration, RASx precharge Pulse duration, write command Pulse duration, RASx active, self refresh (see Note 7) Pulse duration, RASx precharge after self refresh Setup time, column address Setup time, row address Setup time, data in (see Note 8) Setup time, read command Setup time, write command before CASx precharge Setup time, write command before RASx precharge Setup time, write command before CASx active (early-write only) Setup time, WEx high before RASx low (CBR refresh only) Setup time, CASx referenced to RASx ( CBR refresh only ) Hold time, column address Hold time, data in (see Note 8) Hold time, row address Hold time, read command referenced to CASx (see Note 9) Hold time, read command referenced to RASx (see Note 9) Hold time, write command during CASx active ( early-write only ) Hold time, RASx referenced to OEx Hold time, WEx high after RASx low (CBR refresh only) Hold time, CASx referenced to RASx ( CBR refresh only ) Hold time, OEx command Hold time, RASx active from CASx precharge Hold time, CASx referenced to RASx (self refresh only) Delay time, column address to write command ( read-write only ) 84 111 50 50 30 8 100 90 0 0 0 0 8 8 0 10 5 8 8 8 0 0 8 8 10 10 13 28 - 50 42 100 000 10 000 MAX 'xEP64DxN-60 'xEP72DxN-60 MIN 104 135 60 60 40 10 100 110 0 0 0 0 10 10 0 10 5 10 10 10 0 0 10 10 10 10 15 35 - 50 49 100 000 10 000 MAX 'xEP64DxN-70 'xEP72DxN-70 MIN 124 160 70 70 50 10 100 130 0 0 0 0 12 12 0 10 5 12 12 10 0 0 12 10 10 10 18 40 - 50 57 100 000 10 000 MAX ns ns ns ns ns ns UNIT
ms
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCRP Delay time, CASx precharge to RASx 5 5 5 ns NOTES: 6. In a read-write cycle, tRWD and tRWL must be observed. 7. During the period of 10 s tRASS 100 s, the device is in a transition state from normal-operation mode to self-refresh mode. 8. Referenced to the later of CASx or WEx in write operations 9. Either tRRH or tRCH must be satisfied for a read cycle.
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
ac timing requirements (continued)
'xEP64DxN-50 'xEP72DxN-50 MIN tCWD tOED tRAD tRAL tCAL tRCD tRPC tRSH tRWD tCPW tREF tT Delay time, CASx to write command ( read-write only ) Delay time, OEx to data in Delay time, RASx to column address ( see Note 10) Delay time, column address to RASx precharge Delay time, column address to CASx precharge Delay time, RASx to CASx ( see Note 10) Delay time, RASx precharge to CASx Delay time, CASx active to RASx precharge Delay time, RASx to write command (read-write only) Delay time, CASx precharge to write command (read-write only) Refresh time interval Transition time 2 30 13 10 25 18 12 5 8 67 45 32 30 2 37 25 MAX 'xEP64DxN-60 'xEP72DxN-60 MIN 34 15 12 30 20 14 5 10 79 54 32 30 2 45 30 MAX 'xEP64DxN-70 'xEP72DxN-70 MIN 40 18 12 35 25 14 5 12 92 62 32 30 52 35 MAX ns ns ns ns ns ns ns ns ns ns ms ns UNIT
NOTE 10: The maximum value is specified only to ensure access time.
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments module comply with the current JEDEC SPD Standard. Please see the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 2 - TM2EP64DxN Table 4 - TM4EP64DxN Table 3 - TM2EP72DxN Table 5 - TM4EP72DxN
Table 2. Serial Presence Detect Data for the TM2EP64DxN
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E LVTTL tRAC = 50 ns tCAC = 13 ns Non-Parity 15.6 s x8 N/A Rev. 1 41 97h '2EP64DxN-50 ITEM 128 bytes DATA 80h '2EP64DxN-60 ITEM 128 bytes DATA 80h '2EP64DxN-70 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71
256 bytes EDO 11 10 1 bank 64 bits
08h 02h 0Bh 0Ah 01h 40h 00h 01h 32h 0Dh 00h 00h 08h 00h 01h 29h 9700...00h
256 bytes EDO 11 10 1 bank 64 bits
08h 02h 0Bh 0Ah 01h 40h 00h
256 bytes EDO 11 10 1 bank 64 bits
08h 02h 0Bh 0Ah 01h 40h 00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-Parity 15.6 s x8 N/A Rev. 1 53 97h
01h 3Ch 0Fh 00h 00h 08h 00h 01h 35h 9700...00h
LVTTL tRAC = 70 ns tCAC = 18 ns Non-Parity 15.6 s x8 N/A Rev. 1 66 97h
01h 46h 12h 00h 00h 08h 00h 01h 42h 9700...00h
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
serial presence detect (continued)
Table 2. Serial Presence Detect Data for the TM2EP64DxN (Continued)
BYTE NO. 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166 FUNCTION DESCRIBED Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data '2EP64DxN-50 ITEM TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA '2EP64DxN-60 ITEM TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA '2EP64DxN-70 ITEM TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
serial presence detect (continued)
Table 3. Serial Presence Detect Data for the TM2EP72DxN
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC = 50 ns tCAC = 13 ns ECC 15.6 s x8 x8 Rev. 1 59 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '2EP72DxN-50 ITEM 128 bytes DATA 80h '2EP72DxN-60 ITEM 128 bytes DATA 80h '2EP72DxN-70 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
256 bytes EDO 11 10 1 bank 72 bits
08h 02h 0Bh 0Ah 01h 48h 00h 01h 32h 0Dh 02h 00h 08h 08h 01h 3Bh 9700...00h
256 bytes EDO 11 10 1 bank 72 bits
08h 02h 0Bh 0Ah 01h 48h 00h
256 bytes EDO 11 10 1 bank 72 bits
08h 02h 0Bh 0Ah 01h 48h 00h
LVTTL tRAC = 60 ns tCAC = 15 ns ECC 15.6 s x8 x8 Rev. 1 71 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 02h 00h 08h 08h 01h 47h 9700...00h
LVTTL tRAC = 70 ns tCAC = 18 ns ECC 15.6 s x8 x8 Rev. 1 84 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 46h 12h 02h 00h 08h 08h 01h 54h 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
serial presence detect (continued)
Table 4. Serial Presence Detect Data for the TM4EP64DxN
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC = 50 ns tCAC = 13 ns Non-Parity 15.6 s x8 N/A Rev. 1 42 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '4EP64DxN-50 ITEM 128 bytes DATA 80h '4EP64DxN-60 ITEM 128 bytes DATA 80h '4EP64DxN-70 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
256 bytes EDO 11 10 2 banks 64 bits
08h 02h 0Bh 0Ah 02h 40h 00h 01h 32h 0Dh 00h 00h 08h 00h 01h 2Ah 9700...00h
256 bytes EDO 11 10 2 banks 64 bits
08h 02h 0Bh 0Ah 02h 40h 00h
256 bytes EDO 11 10 2 banks 64 bits
08h 02h 0Bh 0Ah 02h 40h 00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-Parity 15.6 s x8 N/A Rev. 1 54 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 08h 00h 01h 36h 9700...00h
LVTTL tRAC = 70 ns tCAC = 18 ns Non-Parity 15.6 s x8 N/A Rev. 1 67 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 46h 12h 00h 00h 08h 00h 01h 43h 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
serial presence detect (continued)
Table 5. Serial Presence Detect for the TM4EP72DxN
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC = 50 ns tCAC = 13 ns ECC 15.6 s x8 x8 Rev. 1 60 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '4EP72DxN-50 ITEM 128 bytes DATA 80h '4EP72DxN-60 ITEM 128 bytes DATA 80h '4EP72DxN-70 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
256 bytes EDO 11 10 2 banks 72 bits
08h 02h 0Bh 0Ah 02h 48h 00h 01h 32h 0Dh 02h 00h 08h 08h 01h 3Ch 9700...00h
256 bytes EDO 11 10 2 banks 72 bits
08h 02h 0Bh 0Ah 02h 48h 00h
256 bytes EDO 11 10 2 banks 72 bits
08h 02h 0Bh 0Ah 02h 48h 00h
LVTTL tRAC = 60 ns tCAC = 15 ns ECC 15.6 s x8 x8 Rev. 1 72 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 02h 00h 08h 08h 01h 48h 9700...00h
LVTTL tRAC = 70 ns tCAC = 18 ns ECC 15.6 s x8 x8 Rev. 1 85 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 46h 12h 02h 00h 08h 08h 01h 55h 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
device symbolization (TM4EP64DPN illustrated)
TM4EP64DPN Unbuffered Key Position YY MM T -SS = = = =
-SS
YYMMT
3.3-V Voltage Key Position Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
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SMMS684A - AUGUST 1997 - REVISED FEBRUARY 1998
MECHANICAL DATA
BR (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE
5.255 (133,48) 5.245 (133,22) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places
(Note D) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.054 (1,37) 0.046 (1,17)
0.039 (1,00) TYP 0.125 (3,18) 0.118 (3,00) DIA 2 Places
0.050 (1,27) 0.125 (3,18)
0.014 (0,35) MAX 0.118 (3,00) TYP 0.700 (17,78) TYP 1.005 (25,53) 0.995 (25,27) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only)
4088180/A 07/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes de-panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities.
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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