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TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES
SMMS679 - MARCH 1997
D D D D D D D D D D
Organization TM124BBK32H/ I . . . 1 048 576 x 32 TM248CBK32H/ I . . . 2 097 152 x 32 Single 5-V Power Supply (10% Tolerance) 72-Pin Single In-Line Memory Module (SIMM) for Use With Socket TM124BBK32H/ I - Uses Two 16M-Bit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM248CBK32H/ I - Uses Four 16M-Bit DRAMs in Plastic SOJ Packages Long Refresh Period 16 ms (1 024 Cycles) All Inputs, Outputs, Clocks Fully TTL-Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh
D D
Presence Detect Performance Ranges:
ACCESS ACCESS ACCESS READ TIME TIME TIME OR tRAC tAA tCAC WRITE CYCLE (MAX) (MAX) (MAX) (MIN) '124BBK32H / I-50 50 ns 25 ns 13 ns 90 ns '124BBK32H / I-60 60 ns 30 ns 15 ns 110 ns '124BBK32H / I-70 70 ns 35 ns 18 ns 130 ns '248CBK32H / I-50 50 ns 25 ns 13 ns 90 ns '248CBK32H / I-60 60 ns 30 ns 15 ns 110 ns '248CBK32H / I-70 70 ns 35 ns 18 ns 130 ns
D D D D
Low Power Dissipation Operating Free-Air Temperature Range 0C to 70C Gold-Tabbed Versions Available: TM124BBK32H TM248CBK32H Tin-Lead (Solder) Tabbed Versions Available: TM124BBK32I TM248CBK32I
description
TM124BBK32H/ I The TM124BBK32H / I is a 32M-bit dynamic random-access memory (DRAM) module organized as four times 1 048 576 x 8 in a 72-pin SIMM. The SIMM is composed of two TMS418160ADZ, 1 048 576 x 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160ADZ is described in the TMS418160A data sheet (literature number SMKS891). The TM124BBK32H/ I SIMM is available in the single-sided BK-leadless module for use with sockets. TM248CBK32H/ I The TM248CBK32H / I is a 64M-bit DRAM organized as four times 2 097 152 x 8 in a 72-pin SIMM. The SIMM is composed of four TMS418160ADZ, 1 048 576 x 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160ADZ is described in the TMS418160A data sheet (literature number SMKS891). The TM248CBK32H / I SIMM is available in the double-sided BK-leadless module for use with sockets.
operation
The TM124BBK32H / I operates as two TMS418160ADZ DRAMs, connected as shown in the functional block diagram and Table 1. The TM248CBK32H / I operates as four TMS418160ADZ DRAMs connected as shown in the functional block diagram and Table 1. The common I / O feature dictates the use of early-write cycles to prevent contention on D and Q.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
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TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES
SMMS679 - MARCH 1997
BK SINGLE-IN-LINE MEMORY MODULE ( TOP VIEW )
TM124BBK32H/I ( SIDE VIEW )
TM248CBK32H/I ( SIDE VIEW )
VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 RAS2 NC NC NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0 - A9 CAS0 - CAS3 DQ0 - DQ31 NC PD1 - PD4 RAS0 - RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 50 ns TM124BBK32H/I 60 ns 70 ns 50 ns TM248CBK32H/I 60 ns 70 ns PD1 (67) VSS VSS VSS NC NC NC PD2 (68) VSS VSS VSS NC NC NC PD3 (69) VSS NC VSS VSS NC VSS PD4 (70) VSS NC NC VSS NC NC
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TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES
SMMS679 - MARCH 1997
operation (continued)
Table 1. Connection Table
DATA BLOCK DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 RASx SIDE 1 RAS0 RAS0 RAS2 RAS2 SIDE 2 RAS1 RAS1 RAS3 RAS3 CASx CAS0 CAS1 CAS2 CAS3
Side 2 applies to the TM248CBK32H/I only.
single in-line memory module and components
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch / inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124BBK32H and TM248CBK32H: Nickel plate and gold plate over copper Contact area for TM124BBK32I and TM248CBK32I: Nickel plate and tin / lead over copper
functional block diagram (TM124BBK32H/I and TM248CBK32H/I, side 1)
A0 - A9 RAS0 W 10 RAS2
10
CAS0 CAS1
1M x 16 A0 -A9 DQ0 - RAS DQ7 W LCAS DQ8 - DQ15 UCAS
10 D0 - D7 CAS2 CAS3
D8 - D15
1M x 16 A0 -A9 DQ0 - RAS DQ7 W LCAS DQ8 - DQ15 UCAS
D16 - D23 D24 - D31
functional block diagram (TM248CBK32H/I, side 2)
A0 - A9 RAS1 W 10 RAS3
10
CAS1 CAS0
1M x 16 A0 -A9 DQ0 - RAS DQ7 W LCAS DQ8 - UCAS DQ15
10 D8 - D15 D0 - D7 CAS3 CAS2
1M x 16 A0 -A9 DQ0 - RAS DQ7 W LCAS DQ8 - UCAS DQ15
D24 - D31
D16 - D23
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TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES
SMMS679 - MARCH 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM124BBK32H, TM124BBK32I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W TM248CBK32H, TM248CBK32I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, VO = 0 V to VCC, CAS high VCC = 5.5 V, Minimum cycle VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, tPC = MIN, CAS cycling RAS low, '124BBK32H / I - 50 MIN 2.4 0.4 10 10 MAX '124BBK32H / I - 60 MIN 2.4 0.4 10 10 MAX '124BBK32H / I - 70 MIN 2.4 0.4 10 10 MAX UNIT V V A A
IO
ICC1
360
320
300
mA
4
4
4
mA
ICC2
Standby current
2
2
2
mA
ICC3
Average refresh current (RAS only or CBR) Average page current
360
320
300
mA
ICC4
220
180
160
mA
For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions.
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TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES
SMMS679 - MARCH 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, VO = 0 V to VCC, CAS high VCC = 5.5 V, Minimum cycle '248CBK32H / I - 50 MIN 2.4 0.4 10 20 MAX '248CBK32H / I - 60 MIN 2.4 0.4 10 20 MAX '248CBK32H / I - 70 MIN 2.4 0.4 10 20 MAX UNIT V V A A
ICC1
368
328
308
mA
ICC2
Standby current
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
8
8
8
mA
4
4
4
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
720
640
600
mA
ICC4
440
360
320
mA
For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5)
PARAMETER Ci(A) Ci(R) Ci(C) Ci(W) Co(DQ) Input capacitance, A0 - A9 Input capacitance, RAS inputs Input capacitance, CAS inputs Input capacitance, W Output capacitance on DQ0 - DQ31 '124BBK32H / I MIN MAX 10 7 7 14 7 '248CBK32H / I MIN MAX 20 7 14 28 14 UNIT pF pF pF pF pF
NOTE 5: VCC = 5 V 0.5 V, and the bias on pins under test is 0 V.
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TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES
SMMS679 - MARCH 1997
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tRAC tCPA tCLZ tOH Access time from column address Access time from CAS low Access time from RAS low Access time from column precharge CAS to output in the low-impedance state Output disable time from start of CAS high 0 3 0 13 '124BBK32H / I - 50 '248CBK32H / I - 50 MIN MAX 25 13 50 30 0 3 0 15 '124BBK32H / I - 60 '248CBK32H / I - 60 MIN MAX 30 15 60 35 0 3 0 18 '124BBK32H / I - 70 '248CBK32H / I - 70 MIN MAX 35 18 70 40 ns ns ns ns ns ns ns UNIT
tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'124BBK32H / I - 50 '248CBK32H / I - 50 MIN tRC tRWC tPC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tCAH tRHCP tDH tRAH tRCH Cycle time, random read or write (see Note 7) Cycle time, read-write Cycle time, page-mode read or write (see Notes 7 and 8) Pulse duration, page mode, RAS low Pulse duration, nonpage mode, RAS low Pulse duration, CAS low Pulse duration, CAS high Pulse duration, RAS high (precharge) Pulse duration, W low Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data before CAS low Setup time, W high before CAS low Setup time, W low before CAS high Setup time, W low before RAS high Setup time, W low before CAS low Hold time, column address after CAS low Hold time, RAS high from CAS precharge Hold time, data after CAS low Hold time, row address after RAS low Hold time, W high after CAS high (see Note 9) 90 131 35 50 50 13 8 30 10 0 0 0 0 13 13 0 10 30 10 8 0 0 100 000 10 000 10 000 MAX '124BBK32H / I - 60 '248CBK32H / I - 60 MIN 110 155 40 60 60 15 10 40 10 0 0 0 0 15 15 0 10 35 10 10 0 0 100 000 10 000 10 000 MAX '124BBK32H / I - 70 '248CBK32H / I - 70 MIN 130 181 45 70 70 18 10 50 10 0 0 0 0 18 18 0 15 40 15 10 0 0 100 000 10 000 10 000 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
tRRH Hold time, W high after RAS high (see Note 9) NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be tCP . 9. Either tRRH or tRCH must be satisfied for a read cycle.
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TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES
SMMS679 - MARCH 1997
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'124BBK32H / I - 50 '248CBK32H / I - 50 MIN tWCH tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tREF Hold time, W low after CAS low Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low (CBR only) Delay time, CAS low to RAS high Refresh time interval 10 10 5 50 5 13 25 25 18 5 13 16 30 2 37 25 MAX '124BBK32H / I - 60 '248CBK32H / I - 60 MIN 10 10 5 60 5 15 30 30 20 5 15 16 30 2 45 30 MAX '124BBK32H / I - 70 '248CBK32H / I - 70 MIN 15 10 5 70 5 15 35 35 20 5 18 16 30 52 35 MAX ns ns ns ns ns ns ns ns ns ns ns ms ns UNIT
tT Transition time 2 NOTE 10: The maximum value is specified only to ensure access time.
device symbolization (TM124BBK32H/I illustrated)
TM124BBK32H
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
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TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES
SMMS679 - MARCH 1997
MECHANICAL DATA
BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE
4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP
0.054 (1,37) 0.047 (1,19)
1.005 (25,53) 0.995 (25,27)
0.050 (1,27) 0.040 (1,02) TYP
0.128 (3,25) 0.120 (3,05)
0.010 (0,25) MAX 0.400 (10,16) TYP 0.208 (5,28) MAX 0.360 (9,14) MAX (For Double-Sided SIMM)
4040197 / B 02/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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