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TM4100GAD8 4194304 BY 8-BIT DRAM MODULE
SMMS508C - MARCH 1992 - REVISED JUNE 1995
D D D D D D D D
Organization . . . 4 194304 x 8 Single 5-V Power Supply (10% Tolerance) 30-Pin Single In-Line Memory Module (SIMM) for Use With Sockets Utilizes Eight 4-Megabit DRAMs in Plastic Small-Outline J-Lead Packages (SOJs) Long Refresh Period 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Performance Ranges:
ACCESS TIME tRAC (MAX) 60 ns 70 ns 80 ns ACCESS ACCESS TIME TIME tAA tCAC (MAX) 30 ns 35 ns 40 ns (MAX) 15 ns 18 ns 20 ns READ OR WRITE CYCLE (MIN) 110 ns 130 ns 150 ns
SINGLE IN-LINE MODULE ( TOP VIEW )
D D D
'4100GAD8-60 '4100GAD8-70 '4100GAD8-80
Common CAS Control for Eight Common Data-In and Data-Out Lines Low Power Dissipation Operating Free-Air Temperature Range 0C to 70C
description description
The TM4100GAD8 is a dynamic random-access memory (DRAM) module organized as 4 194 304 x 8 bits in a 30-pin leadless single in-line memory module (SIMM). The SIMM is composed of eight TMS44100DJ 4 194 304 x 1-bit DRAMs in 20/26-lead plastic small-outline J-lead packages (SOJ) mounted on a substrate with decoupling capacitors. The TM4100GAD8 is available in the AD single-sided, leadless module for use with sockets. The TM4100GAD8 is characterized for operation from 0C to 70C.
VCC CAS DQ1 A0 A1 DQ2 A2 A3 VSS DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 A9 A10 DQ6 W VSS DQ7 NC DQ8 NC RAS NC NC VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
PIN NOMENCLATURE A0 - A10 CAS DQ1 - DQ8 NC RAS VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out No Internal Connection Row-Address Strobe 5-V Supply Ground Write Enable
operation
The TM4100GAD8 operates as eight TMS44100DJs connected as shown in the functional block diagram. Refer to the TMS44100 data sheet for details of its operation. The common I/O feature of the TM4100GAD8 dictates the use of early-write cycles to prevent contention on D and Q.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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TM4100GAD8 4194304 BY 8-BIT DRAM MODULE
SMMS508C - MARCH 1992 - REVISED JUNE 1995
single in-line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for socketable devices: Nickel plate and solder plate over copper
functional block diagram
A0 - A10 RAS CAS W
11
DQ1
4096 x 1 A0 - A10 RAS CAS W Q DQ1 VCC VSS 4096 x 1 A0-A10 RAS CAS W Q DQ2 VCC VSS 4096 x 1 A0 - A10 RAS CAS W Q DQ3 VCC VSS 4096 x 1 A0 - A10 RAS CAS W Q DQ4 VCC VSS
11
DQ5
4096 x 1 A0 - A10 RAS CAS W Q DQ5 VCC VSS 4096 x 1 A0 - A10 RAS CAS W Q DQ6 VCC VSS 4096 x 1 A0 - A10 RAS CAS W Q DQ7 VCC VSS 4096 x 1 A0 - A10 RAS CAS W Q DQ8 VCC VSS
11
11
DQ2
DQ6
11
11
DQ3
DQ7
11
11
DQ4
DQ8
VCC C . . . .C VSS
2
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TM4100GAD8 4194304 BY 8-BIT DRAM MODULE
SMMS508C - MARCH 1992 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Supply voltage range on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VO = 0 V to VCC, VCC = 5.5 V, CAS high VCC = 5.5 V, Minimum cycle '4100GAD8-60 MIN 2.4 0.4 10 10 840 MAX '4100GAD8-70 MIN 2.4 0.4 10 10 720 MAX '4100GAD8-80 MIN 2.4 0.4 10 10 640 MAX UNIT V V A A mA
ICC2
Standby current
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high, VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = minimum, CAS cycling
16
16
16
mA
8
8
8
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
840
720
640
mA
ICC4
720
640
560
mA
CAS-before-RAS (CBR) refresh NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
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TM4100GAD8 4194304 BY 8-BIT DRAM MODULE
SMMS508C - MARCH 1992 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz
PARAMETER Ci(A) Ci(RC) Ci(W) CO Input capacitance, A0 - A10 Input capacitance, CAS and RAS Input capacitance, W Output capacitance (pins DQ1 - DQ8) MIN MAX 40 56 56 12 UNIT pF pF pF pF
NOTE 5: VCC = 5 V 0.5 V and the bias on the pin under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tCPA tRAC tCLZ tOFF Access time from column address Access time from CAS low Access time from column precharge Access time from RAS low CAS to output in low impedance Output disable time after CAS high (see Note 6) 0 0 15 '4100GAD8-60 MIN MAX 30 15 35 60 0 0 18 '4100GAD8-70 MIN MAX 35 18 40 70 0 0 20 '4100GAD8-80 MIN MAX 40 20 45 80 UNIT ns ns ns ns ns ns
NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'4100GAD8-60 MIN tRC tPC tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tCAH tDHR tDH tAR Cycle time, random read or write (see Note 7) Cycle time, page-mode read or write (see Note 8) Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low Delay time, CAS low to RAS high Hold time, column address after CAS low Hold time, data after RAS low (see Note 9) Hold time, data Hold time, column address after RAS low (see Note 9) 110 40 15 0 60 10 15 30 30 20 0 15 10 50 10 50 45 30 MAX '4100GAD8-70 MIN 130 45 15 0 70 10 15 35 35 20 0 18 15 55 15 55 52 35 MAX '4100GAD8-80 MIN 150 50 20 0 80 10 15 40 40 20 0 20 15 60 15 60 60 40 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 7. 8. 9. 10.
All cycle times assume tT = 5 ns. To assure tPC min, tASC should be tCP. The minimum value is measured when tRCD is set to tRCD min as a reference. The maximum value is specified only to assure access time.
4
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TM4100GAD8 4194304 BY 8-BIT DRAM MODULE
SMMS508C - MARCH 1992 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
'4100GAD8-60 MIN tRAH tRCH tRRH tWCH tWCR tWRH tWTH tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tWTS tTAA tTCPA tTRAC tREF Hold time, row address after RAS low Hold time, W high after CAS high (see Note 11) Hold time, W high after RAS high (see Note 11) Hold time, write after CAS low Hold time, W low after RAS low (see Note 9) Hold time, W high after RAS low (CBR refresh only) Hold time, W low (test mode only) Pulse duration, page mode, RAS low Pulse duration, nonpage mode, RAS low Pulse duration, CAS low Pulse duration, CAS high Pulse duration, RAS high (precharge) Pulse duration, write Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data before CAS low Setup time, W high before CAS low Setup time, W low before CAS high Setup time, W low before RAS high Setup time, W low before CAS low Setup time, W high before RAS low (CBR refresh only) Setup time, W low (test mode only) Access time from address (test mode) Access time from column precharge (test mode) Access time from RAS (test mode) Refresh time interval 10 0 0 15 50 10 10 60 60 15 10 40 15 0 0 0 0 15 15 0 10 10 35 40 65 16 2 100 000 10 000 10 000 MAX '4100GAD8-70 MIN 10 0 0 15 55 10 10 70 70 18 10 50 15 0 0 0 0 18 18 0 10 10 40 45 75 16 50 2 100 000 10 000 10 000 MAX '4100GAD8-80 MIN 10 0 0 15 60 10 10 80 80 20 10 60 15 0 0 0 0 20 20 0 10 10 45 50 85 16 50 100 000 10 000 10 000 MAX UINT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
tT Transition time 2 50 NOTES: 9. The minimum value is measured when tRCD is set to tRCD min as a reference. 11. Either tRRH or tRCH must be satisfied for a read cycle.
device symbolization
TM4100GAD8 - SS YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed
NOTE A: The location of symbolization may vary.
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TM4100GAD8 4194304 BY 8-BIT DRAM MODULE
SMMS508C - MARCH 1992 - REVISED JUNE 1995
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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