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TM124GU8A 1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181A-JANUARY 1991-REVISED JANUARY 1993
* * * * * * * *
Organization . . . 1 048 576 x 8 Single 5-V Power Supply (10% Tolerance) 30-Pin Single In-Line Memory Module (SIMM) TM124GU8A Utilizes Two 4-Megabit Dynamic RAMs in Plastic Small-Outline J-Lead Packages (SOJs) Long Refresh Period . . . 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Outputs Performance Ranges:
ACCESS TIME (tRAC) (MAX) 60 ns 70 ns 80 ns ACCESS TIME (tAA) (MAX) 30 ns 35 ns 40 ns READ OR WRITE CYCLE (MIN) 110 ns 130 ns 150 ns
SINGLE IN-LINE MODULE (TOP VIEW)
TM124GU8A-60 TM124GU8A-70 TM124GU8A-80
* *
Low Power Dissipation Operating Free-Air Temperature Range 0C to 70C
description
The TM124GU8A is a dynamic random-access memory module organized as 1 048 576 x 8 in a 30-pin leadless single in-line memory module (SIMM). The TM124GU8A is composed of two TMS44400, 1 048 576 x 4 bit dynamic RAMs in 20/26-lead plastic small-outline J-lead packages (SOJs). The TM124GU8A is mounted on a substrate with decoupling capacitors. The onboard capacitors eliminate the need for bypassing on the motherboard and offer superior performance over equivalent leaded capacitors due to reduced lead inductance. With the elimination of bypass capacitors on the motherboard, reduced PC board size, and fewer plated through-holes, a cost savings can be realized.
VCC CAS DQ1 A0 A1 DQ2 A2 A3 VSS DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 A9 NC DQ6 W VSS DQ7 NC DQ8 NC RAS NC NC VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
PIN NOMENCLATURE A0-A9 CAS DQ1-DQ8 NC RAS VCC VSS Address Inputs Column-Address Strobe Data In/Data Out No Internal Connect Row-Address Strobe 5-V Supply Ground
The TM124GU8A features RAS access times of 60 ns, 70 ns, and 80 ns. All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address lines and data in are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TM124GU8A is characterized for operation from 0C to 70C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1993, Texas Instruments Incorporated
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TM124GU8A 1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181A-JANUARY 1991-REVISED JANUARY 1993
operation
The TM124GU8A operates as two TMS44400s connected as shown in the functional block diagram. The common I/O features of the TM124GU8A dictates the use of early write cycles to prevent contention on the DQ lines.
specifications
Refresh period is extended to 16 milliseconds and, during this period, each of the 1024 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power.
single in-line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness on contact area Bypass capacitors: Multilayer ceramic Contact area for socketable devices: Nickel plate and solder plate over copper
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TM124GU8A 1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181A-JANUARY 1991-REVISED JANUARY 1993
functional block diagram
A0-A9 RAS CAS W 10 1024K x 4 A0-A9 DQ1 DQ2 RAS CAS DQ3 W DQ4 OE VDD VSS 1024K x 4 A0-A9 DQ5 RAS DQ6 CAS DQ7 W DQ8 OE VDD VSS DQ1 DQ2 DQ3 DQ4
10
DQ5 DQ6 DQ7 DQ8
VCC C...C VSS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
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TM124GU8A 1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181A-JANUARY 1991-REVISED JANUARY 1993
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER VOH VOL II IO High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VI = 0 to 6.5 V, VCC = 5.5 V, All other pins = 0 V to VCC VO = 0 to VCC, VCC = 5.5 V, CAS high Minimum cycle, VCC = 5.5 V After 1 memory cycle, RAS and CAS high, VIH = 2.4 V (TTL) After 1 memory cycle, RAS and CAS high, VIH = VCC - 0.2 V (CMOS) Minimum cycle, VCC= 5.5 V, RAS cycling, CAS high tc(P) = minimum, VCC = 5.5 V, RAS low, CAS cycling TM124GU8A-60 MIN 2.4 0.4 10 10 210 MAX TM124GU8A-70 MIN 2.4 0.4 10 10 180 MAX TM124GU8A-80 MIN 2.4 0.4 10 10 160 MAX UINT V V A A mA
Read or write cycle current ICC1 (see Note 3)
4
4
4
mA
ICC2 Standby Current
2
2
2
mA
Average refresh current ICC3 (see Note 3) Average page current ICC4 (see Note 4)
210 180
180 160
160 140
mA mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL. 4. Measured with a maximum of one address change while CAS = VIH.
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TM124GU8A 1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181A-JANUARY 1991-REVISED JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz
PARAMETER Ci(A) Ci(DQ) Ci(RC) Ci(W) Input capacitance, address inputs Input capacitance, data inputs/outputs Input capacitance, strobe inputs Input capacitance, W input MIN MAX 10 7 14 14 UNIT pF pF pF pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tCPA tRAC tCLZ tOFF Access time from column-address Access time from CAS low Access time from column precharge Access time from RAS low CAS to output in low Z Output disable time after CAS high (see Note 5) 0 0 15 TM124GU8A-60 MIN MAX 30 15 35 60 0 0 18 TM124GU8A-70 MIN MAX 35 18 40 70 0 0 20 TM124GU8A-80 MIN MAX 40 20 45 80 UNIT ns ns ns ns ns ns
NOTE 5: tOFF is specified when the otuput is no longer driven.
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TM124GU8A 1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181A-JANUARY 1991-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air temperature
TM124GU8A-60 MIN tRC tPC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWSR tWTS tCAH tDHR tDH tAR tRAH tRCH tRRH tWCH tWCR tWHR tWTH Random read or write cycle (see Note 6) Page-mode read or write cycle time (see Note 7) Page-mode pulse duration, RAS low Non-page-mode pulse duration, RAS low Pulse duration, CAS low Pulse duration, CAS high Pulse duration, RAS high (precharge) Write pulse duration Column-address setup time before CAS low Row-address setup time before RAS low Data setup time Read setup time before CAS low W low setup time before CAS high W low setup time before RAS high W low setup time before CAS low W high setup time (CAS-before-RAS refresh only) W low setup time (test mode only) Column-address hold time after CAS low Data hold time after RAS low (see Note 8) Data hold time Column-address hold time after RAS low (see Note 8) Row-address hold time after RAS low Read hold time after CAS high (see Note 9) Read hold time after RAS high (see Note 9) Write hold time after CAS low Write hold time after RAS low (see Note 8) W high hold time (CAS-before-RAS refresh only) W low hold time (test mode only) 110 40 60 60 15 10 40 15 0 0 0 0 15 15 0 10 10 10 50 10 50 10 0 0 15 50 10 10 100 000 10 000 10 000 MAX TM124GU8A-70 MIN 130 45 70 70 18 10 50 15 0 0 0 0 18 18 0 10 10 15 55 15 55 10 0 0 15 55 10 10 100 000 10 000 10 000 MAX TM124GU8A-80 MIN 150 50 80 80 20 10 60 15 0 0 0 0 20 20 0 10 10 15 60 15 60 10 0 0 15 60 10 10 100 000 10 000 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Continued next page. NOTES: 6. All cycle times assume tT = 5 ns. 7. To assure tPC min, tASC should be greater than or equal to 5 ns. 8. The minimum value is measured when tRCD is set to tRCD min as a reference. 9. Either tRRH or tRCH must be satisfied for a read cycle.
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TM124GU8A 1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181A-JANUARY 1991-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air temperature (concluded)
TM124GU8A-60 MIN tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tTAA tTCPA tTRAC tREF tT Delay time, RAS low to CAS high (CAS-before-RAS refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CAS-before-RAS refresh only) Delay time, RAS low to column-address (see Note 10) Delay time, column-address to RAS high Delay time, column-address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low (CBR only) Delay time, CAS low to RAS high Access time from address (test mode) Access time from column precharge (test mode) Access time from RAS (test mode) Refresh time interval Transition time 2 15 0 60 10 15 30 30 20 0 15 35 40 65 16 50 2 45 30 MAX TM124GU8A-70 MIN 15 0 70 10 15 35 35 20 0 18 40 45 75 16 50 2 52 35 MAX TM124GU8A-80 MIN 20 0 80 10 15 40 40 20 0 20 45 50 85 16 50 60 40 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
NOTE 10: The maximum value is specified only to assure access time.
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TM124GU8A 1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181A-JANUARY 1991-REVISED JANUARY 1993
30-pin U-A single in-line memory module
5,28 (0.208) MAX 89,03 (3.505) 88,77 (3.495) 3,18 (0.125) TYP 16,64 (0.655) MAX
Pin Spacing 2,54 (0.100) T.P. (see Note A) 1,78 (0.070) TYP 3,38 (0.133) TYP
10,16 (0.400) TYP
1, 37 (0.054) 1, 19 (0.047)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
device symbolization
TM124GU8A - SS YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed
NOTE: The location of the part number may vary.
Printed in U. S. A. 8
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SMMS181A
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Copyright (c) 1998, Texas Instruments Incorporated

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