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UC1625 UC2625 UC3625
Brushless DC Motor Controller
FEATURES
* Drives Power MOSFETs or Power Darlingtons Directly * 50V Open Collector High-Side Drivers * Latched Soft Start * High-speed Current-Sense Amplifier with Ideal Diode * Pulse-by-Pulse and Average Current Sensing * Over-Voltage and Under-Voltage Protection * Direction Latch for Safe Direction Reversal * Tachometer * Trimmed Reference Sources 30mA * Programmable Cross-Conduction Protection * Two-Quadrant and Four-Quadrant Operation
DESCRIPTION
The UC3625 family of motor controller ICs integrate most of the functions required for high-performance brushless DC motor control into one package. When coupled with external power MOSFETs or Darlingtons, these ICs perform fixed-frequency PWM motor control in either voltage or current mode while implementing closed loop speed control and braking with smart noise rejection, safe direction reversal, and cross-conduction protection. Although specified for operation from power supplies between 10V and 18V, the UC1625 can control higher voltage power devices with external level-shifting components. The UC1625 contains fast, high-current push-pull drivers for low-side power devices and 50V open-collector outputs for high-side power devices or level shifting circuitry. The UC1625 is characterized for operation over the military temperature range of -55C to +125C, while the UC2625 is characterized from -40C to +105C and the UC3625 is characterized from 0C to 70C. (NOTE: ESD Protection to 2kV)
TYPICAL APPLICATION
VREF
+5V TO HALL SENSORS
+15V
VMOTOR
100nF 20F 10k QUAD DIR ROSC 33k 3k 10k 2 22 6 1k 1 100nF 28 27 25 2200pF COSC UC3625
100nF
3k + 20F 2N3904 10 11 3k 16 17 18 14 13 12
+ 100F
19
2N3906 IRF9350
TO MOTOR TO OTHER CHANNELS
4k
TO OTHER CHANNELS 10 IRF532
REQUIRED FOR BRAKE AND FAST REVERSE
15 21 26 3 24 23 8 9 10 4 5 7
20 10k
BRAKE
3nF CT
100nF 68k RT 5nF 100nF 2nF 2nF 2nF FROM HALL SENSORS 240 5nF 0.02 RS REQUIRED FOR AVERAGE CURRENT SENSING 0.02 RD
240
UDG-99045
SLUS353A - NOVEMBER 1999
UC1625 UC2625 UC3625 ABSOLUTE MAXIMUM RATINGS
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V Pwr VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +20V PWM In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6V E/A IN(+), E/A IN(-) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 12V ISENSE1, ISENSE2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.3 to 6V OV-Coast, Dir, Speed-In, SSTART, Quad Sel . . . . . . -0.3 to 8V H1, H2, H3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 12V PU Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 50V PU Output Current . . . . . . . . . . . . . . . . . . +200 mA continuous PD Output Current . . . . . . . . . . . . . . . . . . 200 mA continuous E/A Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA ISENSE Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . -10 mA Tach Out Output Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mA VREF Output Current . . . . . . . . . . . . . . . . . . -50 mA continuous Operating Temperature Range UC1625. . . . . . -55C to 125C Operating Temperature Range UC2625. . . . . . -40C to 105C Operating Temperature Range UC3625. . . . . . . . . 0C to 70C
CONNECTION DIAGRAM
DIL-28 (TOP VIEW) J or N PACKAGE
Note 1: Currents are positive into and negative out of the specified terminal. Note 2: Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations of packages. Note 3: This pinout applies to the SOIC (DW), PLCC (Q), and LCC (L) packages (ie. pin 22 has the same function on all packages.)
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for: TA = 25C; Pwr VCC = VCC = 12V; ROSC = 20k to VREF; COSC = 2nF; RTACH = 33k; CTACH = 10nF; and all outputs unloaded. TA = TJ. PARAMETER Overall Supply current VCC Turn-On Threshold VCC Turn-Off Threshold Overvoltage/Coast OV-Coast Inhibit Threshold OV-Coast Restart Threshold OV-Coast Hysteresis OV-Coast Input Current Logic Inputs H1, H2, H3 Low Threshold H1, H2, H3 High Threshold H1, H2, H3 Input Current Quad Sel, Dir Thresholds Quad Sel Hysteresis Dir Hysteresis Quad Sel Input Current Dir Input Current PWM Amp/Comparator E/A In(+), E/A In(-) Input Current PWM In Input Current Error Amp Input Offset Error Amp Voltage Gain To 2.5V To 2.5V 0V < VCOMMON-MODE < 3V -5.0 0 -10 70 90 -0.1 3 5.0 30 10 A A mV dB -30 -30 Over Operating Range Over Operating Range Over Operating Range, to 0V Over Operating Range 0.8 1.6 -400 0.8 1.0 1.9 -250 1.4 70 0.6 50 -1 150 30 1.2 2.0 -120 2.0 V V A V mV V A A Over Operating Range 1.65 1.55 0.05 -10 1.75 1.65 0.10 -1 1.85 1.75 0.15 0 V V V A Over Operating Range Over Operating Range Over Operating Range 8.65 7.75 14.5 8.95 8.05 30.0 9.45 8.55 mA V V TEST CONDITIONS MIN TYP MAX UNITS
2
UC1625 UC2625 UC3625
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for: TA = 25C; Pwr VCC = VCC = 12V; ROSC = 20k to VREF; COSC = 2nF; RTACH = 33k; CTACH = 10nF; and all outputs unloaded. TA = TJ. PARAMETER PWM Amp/Comparator (cont.) E/A Out Range SSTART Pull-up Current SSTART Discharge Current SSTART Restart Threshold Current Amp Gain Level Shift Peak Current Threshold Over Current Threshold ISENSE1, ISENSE2 Input Current ISENSE1, ISENSE2 Offset Current Range ISENSE1, ISENSE2 Tachometer/Brake Tach-Out High Level Tach-Out Low Level On Time On Time Change With Temp RC-Brake Input Current Threshold to Brake, RC-Brake Brake Hysteresis, RC-Brake Speed-In Threshold Speed-In Input Current Low-Side Drivers Voh, -1mA, Down From VCC V Voh, -50mA, Down From VCC Vol, 1mA Vol, 50mA Rise/Fall Time High-Side Drivers Vol, 1mA Vol, 50mA Leakage Current Fall Time Oscillator Frequency Frequency Reference Output Voltage Output Voltage Load Regulation Line Regulation Short Circuit Current Over Operating Range 0mA to -20mA Load 10V to 18V VCC Over Operating Range 4.9 4.7 -40 -10 50 5.0 5.0 -5 -1 100 10 150 5.1 5.3 V V mV mV mA Over Operating Range 40 35 50 60 65 kHz kHz Over Operating Range Over Operating Range Output Voltage = 50V 10% to 90% Slew Time, 50mA Load 50 0.1 1.0 0.4 1.8 25 V V A ns Over Operating Range Over Operating Range Over Operating Range Over Operating Range 10% to 90% Slew Time, into 1nF 1.60 1.75 0.05 0.36 50 2.1 2.2 0.4 0.8 V V V ns Over Operating Range 220 -30 Over Operating Range To 0V Over Operating Range -4.0 0.8 Over Operating Range, 10k to 2.5V Over Operating Range, 10k to 2.5V 170 220 0.1 -1.9 1.0 0.09 257 -5 290 30 1.2 4.7 5 5.3 0.2 280 V V s % mA V V mV A ISENSE1 = .3V, ISENSE2 = .5V to .7V ISENSE1 = .3V, ISENSE2 = .3V ISENSE1 = 0V, Force ISENSE2 ISENSE1 = 0V, Force ISENSE2 To 0V To 0V -1 1.75 2.4 0.14 0.26 -850 1.95 2.5 0.20 0.30 -320 2 2.15 2.65 0.26 0.36 0 12 2 V/V V V V A A V To 0V To 2.5V 0.25 -16 0.1 0.1 -10 0.4 0.2 3.50 -5 3.0 0.3 V A mA V TEST CONDITIONS MIN TYP MAX UNITS
3
UC1625 UC2625 UC3625
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for: TA = 25C; Pwr VCC = VCC = 12V; ROSC = 20k to VREF; COSC = 2nF; RTACH = 33k; CTACH = 10nF; and all outputs unloaded. TA = TJ. PARAMETER Miscellaneous Output Turn-On Delay Output Turn-Off Delay 1 1 s s TEST CONDITIONS MIN TYP MAX UNITS
BLOCK DIAGRAM
Quad Sel RC-Osc PWM In E/A Out E/A In(+) E/A In (-) SSTART ISENSE ISENSE1 ISENSE2 VCC OV-Coast 22 25 26 27 1 28 24 3 ABS VALUE 4 2X 5 19 23 1.75V Dir Speed-In 6 7 0.25V +5V PWM CLOCK DIR H1 8 +5V D L Q H1 COAST CHOP QUAD CROSS CONDUCTION PROTECTION LATCHES DECODER 13 L PDB 11 14 Pwr Vcc PDA DIRECTION LATCH 3.1V 2.5V 250 R S Q Q1 2.9V OSC S PWM CLOCK R Q 5V REFERENCE 2 VREF
10A
0.2V
9V
PWM CLOCK 18 PUA
17
PUB
16
PUC
H2
9 +5V
D
Q
H2
H3
9
D L EDGE DETECT
Q
H3 BRAKE 12 15 PDC GND
+5V 2k RC-Brake 21 ONE SHOT 1V
20
Tach-Out
UDG-99044
4
UC1625 UC2625 UC3625 PIN DESCRIPTIONS
Dir, Speed-In: The position decoder logic translates the Hall signals and the Dir signal to the correct driver signals (PUs and PDs). To prevent output stage damage, the signal on Dir is first loaded into a direction latch, then shifted through a two-bit register. As long as Speed-In is less than 250mV, the direction latch is transparent. When Speed-In is higher than 250mV, the direction latch inhibits all changes in direction. Speed-In can be connected to Tach-Out through a filter, so that the direction latch is only transparent when the motor is spinning slowly, and has too little stored energy to damage power devices. Additional circuitry detects when the input and output of the direction latch are different, or when the input and output of the shift register are different, and inhibits all output drives during that time. This can be used to allow the motor to coast to a safe speed before reversing. The shift register guarantees that direction can't be changed instantaneously. The register is clocked by the PWM oscillator, so the delay between direction changes is always going to be between one and two oscillator periods. At 40kHz, this corresponds to a delay of between 25s and 50s. Regardless of output stage, 25s dead time should be adequate to guarantee no overlap cross-conduction. Toggling DIR will cause an output pulse on Tach-Out regardless of motor speed. E/A In(+), E/A In(-), E/A Out, PWM In: E/A In(+) and E/A In(-) are not internally committed to allow for a wide variety of uses. They can be connected to the ISENSE, to Tach-Out through a filter, to an external command voltage, to a D/A converter for computer control, or to another op amp for more elegant feedback loops. The error amplifier is compensated for unity gain stability, so E/A Out can be tied to E/A In(-) for feedback and major loop compensation. E/A Out and PWM In drive the PWM comparator. For voltage-mode PWM systems, PWM In can be connected to RC-Osc. The PWM comparator clears the PWM latch, commanding the outputs to chop. The error amplifier can be biased off by connecting E/A In(-) to a higher voltage than E/A In(+). When biased off, E/A Out will appear to the application as a resistor to ground. E/A Out can then be driven by an external amplifier. GND: All thresholds and outputs are referred to the GND pin except for the PD and PU outputs. H1, H2, H3: The three shaft-position sensor inputs consist of hysteresis comparators with input pull-up resistors. Logic thresholds meet TTL specifications and can be driven by 5V CMOS, 12V CMOS, NMOS, or open-collectors. Connect these inputs to motor shaft position sensors that are positioned 120 electrical degrees apart. If noisy signals are expected, zener clamp and filter these inputs with 6V zeners and an RC filter. Suggested filtering components are 1k and 2nF. Edge skew in the filter is not a problem, because sensors normally generate modified Gray code with only one output changing at a time, but rise and fall times must be shorter than 20s for correct tachometer operation. Motors with 60 electrical degree position sensor coding can be used if one or two of the position sensor signals is inverted. ISENSE1, ISENSE2, ISENSE: The current sense amplifier has a fixed gain of approximately two. It also has a built-in level shift of approximately 2.5V. The signal appearing on ISENSE is:
I SENSE = 2 .5V + (2 * ABS (I SENSE 1 - I SENSE 2 ))
ISENSE1 and ISENSE2 are interchangeable and can be used as differential inputs. The differential signal applied can be as high as 0.5V before saturation. If spikes are expected on ISENSE1 or ISENSE2, they are best filtered by a capacitor from ISENSE to ground. Filtering this way allows fast signal inversions to be correctly processed by the absolute value circuit. The peak-current comparator allows the PWM to enter a current-limit mode with current in the windings never exceeding approximately 0.2V/RSENSE. The over current comparator provides a fail-safe shutdown in the unlikely case of current exceeding 0.3V/RSENSE. Then, soft start is commanded, and all outputs are turned off until the high current condition is removed. It is often essential to use some filter driving ISENSE1 and ISENSE2 to reject extreme spikes and to control slew rate. Reasonable starting values for filter components might be 250 series resistors and a 5nF capacitor between ISENSE1 and ISENSE2. Input resistors should be kept small and matched to maintain gain accuracy. OV-Coast: This input can be used as an over-voltage shutdown in put, as a coast input, or both. This input can be driven by TTL, 5V CMOS, or 12V CMOS.
5
UC1625 UC2625 UC3625 PIN DESCRIPTIONS (cont.)
PDA, PDB, PDC: These outputs can drive the gates of N-Channel power MOSFETs directly or they can drive the bases of power Darlingtons if some form of current limiting is used. They are meant to drive low-side power devices in high-current output stages. Current available from these pins can peak as high as 0.5A. These outputs feature a true totem-pole output stage. Beware of exceeding IC power dissipation limits when using these outputs for high continuous currents. These outputs pull high to turn a "low-side" device on (active high). PUA, PUB, PUC: These outputs are open-collector, high-voltage drivers that are meant to drive high-side power devices in high-current output stages. These are active low outputs, meaning that these outputs pull low to command a high-side device on. These outputs can drive low-voltage PNP Darlingtons and P-channel MOSFETs directly, and can drive any high-voltage device using external charge-pump techniques, transformer signal coupling, cascode level-shift transistors, or opto-isolated drive (high-speed opto devices are recommended). (See applications). PWR VCC: This supply pin carries the current sourced by the PD outputs. When connecting PD outputs directly to the bases of power Darlingtons, the PWR VCC pin can be current limited with a resistor. Darlington outputs can also be "Baker Clamped" with diodes from collectors back to PWR VCC. (See Applications) Quad Sel: The IC can chop power devices in either of two modes, referred to as "two-quadrant" (Quad Sel low) and "four-quadrant" (Quad Sel high). When two-quadrant chopping, the pull-down power devices are chopped by the output of the PWM latch while the pull-up drivers remain on. The load will chop into one commutation diode, and except for back-EMF, will exhibit slow discharge current and faster charge current. Two-quadrant chopping can be more efficient than four-quadrant. When four-quadrant chopping, all power drivers are chopped by the PWM latch, causing the load current to flow into two diodes during chopping. This mode exhibits better control of load current when current is low, and is preferred in servo systems for equal control over acceleration and deceleration. The Quad Sel input has no effect on operation during braking. RC-Brake: Each time the Tach-Out pulses, the capacitor tied to RC-Brake discharges from approximately 3.33V down to 1.67V through a resistor. The tachometer pulse width is approximately T = 0.67 RT CT, where RT and CT are a resistor and capacitor from RC-Brake to ground. Recommended values for RT are 10k to 500k, and recommended values for CT are 1nF to 100nF, allowing times between 5s and 10ms. Best accuracy and stability are achieved with values in the centers of those ranges. RC-Brake also has another function. If RC-Brake pin is pulled below the brake threshold, the IC will enter brake mode. This mode consists of turning off all three high-side devices, enabling all three low-side devices, and disabling the tachometer. The only things that inhibit low-side device operation in braking are low-supply, exceeding peak current, OV-Coast command, and the PWM comparator signal. The last of these means that if current sense is implemented such that the signal in the current sense amplifier is proportional to braking current, the low-side devices will brake the motor with current control. (See applications) Simpler current sense connections will result in uncontrolled braking and potential damage to the power devices. RC-Osc: The UC3625 can regulate motor current using fixed-frequency pulse width modulation (PWM). The RC-Osc pin sets oscillator frequency by means of timing resistor ROSC from the RC-Osc pin to VREF and capacitor COSC from RC-Osc to Gnd. Resistors 10k to 100k and capacitors 1nF to 100nF will work best, but frequency should always be below 500kHz. Oscillator frequency is approximately:
F=
(ROSC
2 * COSC )
Additional components can be added to this device to cause it to operate as a fixed off-time PWM rather than a fixed frequency PWM, using the RC-Osc pin to select the monostable time constant. The voltage on the RC-Osc pin is normally a ramp of about 1.2V peak-to-peak, centered at approximately 1.6V. This ramp can be used for voltage-mode PWM control, or can be used for slope compensation in current-mode control. SSTART: Any time that VCC drops below threshold or the sensed current exceeds the over-current threshold, the soft-start latch is set. When set, it turns on a transistor that pulls down on SSTART. Normally, a capacitor is connected to this pin, and the transistor will completely discharge the capacitor. A comparator senses when the NPN transistor has completely discharged the capacitor, and allows the soft-start latch to clear when the fault is removed. When the fault is removed, the soft-start capacitor will charge from the on-chip current source.
6
UC1625 UC2625 UC3625 PIN DESCRIPTIONS (cont.)
SSTART clamps the output of the error amplifier, not allowing the error amplifier output voltage to exceed SSTART regardless of input. The ramp on RC-Osc can be applied to PWM In and compared to E/A Out. With SSTART discharged below 0.2V and the ramp minimum being approximately 1.0V, the PWM comparator will keep the PWM latch cleared and the outputs off. As SSTART rises, the PWM comparator will begin to duty-cycle modulate the PWM latch until the error amplifier inputs overcome the clamp. This provides for a safe and orderly motor start-up from an off or fault condition. Tach-Out: Any change in the H1, H2, or H3 inputs loads data from these inputs into the position sensor latches. At the same time data is loaded, a fixed-width 5V pulse is triggered on Tach-Out. The average value of the voltage on Tach-Out is directly proportional to speed, so this output can be used as a true tachometer for speed feedback with an external filter or averaging circuit which usually consists of a resistor and capacitor. Whenever Tach-Out is high, the position latches are inhibited, such that during the noisiest part of the commutation cycle, additional commutations are not possible. Although this will effectively set a maximum rotational speed, the maximum speed can be set above the highest expected speed, preventing false commutation and chatter. VCC: This device operates with supplies between 10V and 18V. Under-voltage lockout keeps all outputs off below 7.5V, insuring that the output transistors never turn on until full drive capability is available. Bypass VCC to ground with an 0.1F ceramic capacitor. Using a 10F electrolytic bypass capacitor as well can be beneficial in applications with high supply impedance. VREF: This pin provides regulated 5 volts for driving Hall-effect devices and speed control circuitry. VREF will reach +5V before VCC enables, ensuring that Hall-effect devices powered from VREF will become active before the UC3625 drives any output. Although VREF is current limited, operation over 30mA is not advised. For proper performance VREF should be bypassed with at least a 0.1F capacitor to ground.
APPLICATION INFORMATION
Cross Conduction Prevention The UC3625 inserts delays to prevent cross conduction due to overlapping drive signals. However, some thought must always be given to cross conduction in output stage design because no amount of dead time can prevent fast slewing signals from coupling drive to a power device through a parasitic capacitance. The UC3625 contains input latches that serve as noise blanking filters. These latches remain transparent through any phase of a motor rotation and latch immediately after an input transition is detected. They remain latched for two cycles of the PWM oscillator. At a PWM oscillator speed of 20kHz, this corresponds to 50s to 100s of blank time which limits maximum rotational speed to 100kRPM for a motor with six transitions per rotation or 50kRPM for a motor with 12 transitions per rotation. This prevents noise generated in the first 50s of a transition from propagating to the output transistors and causing cross-conduction or chatter. The UC3625 also contains six flip flops corresponding to the six output drive signals. One of these flip flops is set every time that an output drive signal is turned on, and 7 cleared two PWM oscillator cycles after that drive signal is turned off. The output of each flip flop is used to inhibit drive to the opposing output (see below). In this way, it is impossible to turn on driver PUA and PDA at the same time. It is also impossible for one of these drivers to turn on without the other driver having been off for at least two PWM oscillator clocks.
EDGE FINDER PWM CLK PULL UP FROM DECODER PULL DOWN
SHIFT REG
S R
Q Q PUA
S R
Q Q PDA
Figure 1. Cross conduction prevention.
UC1625 UC2625 UC3625 TYPICAL CHARACTERISTICS
1MHz
Oscillator Frequency
100kHz
Ro sc 10kHz
10k 30k 100 k
Ro sc Ro sc -
1kHz
100Hz 0.001 0.01 0.1
COSC (F)
Figure 2. Oscillator frequency vs. COSC and ROSC.
Figure 4. Supply current vs. temperature.
100ms
10ms
RT -
500 100 30k
k
On Time
1ms
RT RT -
k
100s
RT -
10k
10s
1s 0.001
0.01
0.1
CT (F)
Figure 3. Tachometer on time vs RT and CT. Figure 5. Soft start pull-up current vs temperature.
8
UC1625 UC2625 UC3625 TYPICAL CHARACTERISTICS (cont.)
Figure 6. Soft start discharge current vs. temperature.
Figure 7. Current sense amplifier transfer function.
APPLICATION INFORMATION (cont.)
Power Stage Design The UC3625 is useful in a wide variety of applications, including high-power in robotics and machinery. The power output stages used in such equipment can take a number of forms, according to the intended performance and purpose of the system. Below are four different power stages with the advantages and disadvantages of each shown. For high-frequency chopping, fast recovery circulating diodes are essential. Six are required to clamp the windings. These diodes should have a continuous current rating at least equal to the operating motor current, since diode conduction duty-cycle can be high. For low-voltage systems, Schottky diodes are preferred. In higher voltage systems, diodes such as Microsemi UHVP high voltage platinum rectifiers are recommended. In a pulse-by-pulse current control arrangement, current sensing is done by resistor RS, through which the transistor's currents are passed (Fig. A, B, and C). In these cases, RD is not needed. The low-side circulating diodes go to ground and the current sense terminals of the UC3625 (ISENSE1 and ISENSE2) are connected to RS through a differential RC filter. The input bias current of the current sense amplifier will cause a common mode offset voltage to appear at both inputs, so for best accuracy, keep the filter resistors below 2k and matched. The current that flows through RS is discontinuous because of chopping. It flows during the on time of the power stage and is zero during the off time. Consequently, the voltage across RS consists of a series of pulses, occurring at the PWM frequency, with a peak value indicative of the peak motor current. To sense average motor current instead of peak current, add another current sense resistor (RD in Fig. D) to measure current in the low-side circulating diodes, and operate in four quadrant mode (pin 22 high). The negative voltage across RD is corrected by the absolute value current sense amplifier. Within the limitations imposed by Table 1, the circuit of Fig. B can also sense average current.
9
UC1625 UC2625 UC3625 APPLICATION INFORMATION (cont.)
FIGURE A
FIGURE B
TO MOTOR
TO MOTOR
RS
RS
FIGURE C
FIGURE D
TO MOTOR
TO MOTOR
RS
RS
RD
FIGURE A FIGURE B FIGURE C FIGURE D
2 QUADRANT YES YES YES YES
4 QUADRANT NO YES YES YES
SAFE BRAKING NO NO YES YES
POWER REVERSE NO IN 4-QUAD MODE ONLY IN -4QUAD MODE ONLY IN-4QUADMODE ONLY
CURRENT SENSE PULSE BY PULSE AVERAGE YES NO YES YES YES NO YES YES
10
UC1625 UC2625 UC3625 APPLICATION INFORMATION (cont.)
Figure 8. Fast high-side P-channel driver.
Figure 11. Power NPN low-side driver.
For drives where speed is critical, P-Channel MOSFETs can be driven by emitter followers as shown in Fig. 8. Here, both the level shift NPN and the PNP must withstand high voltages. A zener diode is used to limit gate-source voltage on the MOSFET. A series gate resistor is not necessary, but always advisable to control overshoot and ringing. High-voltage optocouplers can quickly drive high-voltage MOSFETs if a boost supply of at least 10 volts greater than the motor supply is provided (See Fig. 9.) To protect the MOSFET, the boost supply should not be higher than 18 volts above the motor supply. For under 200V 2-quadrent applications, a power NPN driven by a small P-Channel MOSFET will perform well as a high-side driver as in Fig. 10. A high voltage small-signal NPN is used as a level shift and a high voltage low-current MOSFET provides drive. Although the NPN will not saturate if used within its limitations, the base-emitter resistor on the NPN is still the speed limiting component. Fig. 11 shows a power NPN Darlington drive technique using a clamp to prevent deep saturation. By limiting saturation of the power device, excessive base drive is minimized and turn-off time is kept fairly short. Lack of base series resistance also adds to the speed of this approach. 11
Figure 9. Optocoupled N-channel high-side driver.
Figure 10. Power NPN high-side driver.
UC1625 UC2625 UC3625 APPLICATION INFORMATION (cont.)
+12V 3 33k PUA 7 UC3724N 4 8 5k 1 1nF 2 5 8 1 6 3 100nF 6 7 UC3725N 4 2 VMOTOR
1:2
TO MOTOR
UDG-99047
Figure 12. Fast high-side N-channel driver with transformer isolation.
Fast High-Side N-Channel Driver with Transformer Isolation A small pulse transformer can provide excellent isolation between the UC3625 and a high-voltage N-Channel MOSFET while also coupling gate drive power. In this circuit (shown in Fig. 12), a UC3724 is used as a transformer driver/encoder that duty-cycle modulates the transformer with a 150kHz pulse train. The UC3725 rectifies this pulse train for gate drive power, demodulates the signal, and drives the gate with over 2 amp peak current. Both the UC3724 and the UC3725 can operate up to 500kHz if the pulse transformer is selected appropriately. To raise the operating frequency, either lower the timing resistor of the UC3724 (1k min), lower the timing capacitor of the UC3724 (500pF min) or both. If there is significant capacitance between transformer primary and secondary, together with very high output slew rate, then it may be necessary to add clamp diodes from the transformer primary to +12V and ground. General purpose small signal switching diodes such as 1N4148 are normally adequate. The UC3725 also has provisions for MOSFET current limiting. Consult the UC3725 data sheet for more information on implementing this. Computational Truth Table This table shows the outputs of the gate drive and open collector outputs for given hall input codes and direction signals. Numbers at the top of the columns are pin numbers.
These ICs operate with position sensor encoding that has either one or two signals high at a time, never all low or all high. This coding is sometimes referred to as "120 Coding" because the coding is the same as coding with position sensors spaced 120 magnetic degrees about the rotor. In response to these position sense signals, only one low-side driver will turn on (go high) and one high-side driver will turn on (pull low) at any time.
Table I. Computational truth table.
INPUTS DIR 6 1 1 1 1 1 1 0 0 0 0 0 0 X X H1 8 0 0 0 1 1 1 1 1 1 0 0 0 1 0 H2 9 0 1 1 1 0 0 0 0 1 1 1 0 1 0 H3 10 1 1 0 0 0 1 1 0 0 0 1 1 1 0 Low-Side 12 L L L H H L L L L L H H L L 13 H L L L L H L L H H L L L L 14 L H H L L L H H L L L L L L OUTPUTS High-Side 16 L L H H H H H L L H H H H H 17 H H L L H H L H H H H L H H 18 H H H H L L H H H L L H H H
12
UC1625 UC2625 UC3625 APPLICATION INFORMATION (cont.)
VREF
+5V TO HALL SENSORS
+15V
VMOTOR
100nF 20F 10k QUAD DIR ROSC 33k 3k 10k 2 22 6 1k 1 100nF 28 27 25 2200pF COSC UC3625
100nF
3k + 20F 2N3904 10 11 3k 16 17 18 14 13 12
+ 100F
19
2N3906 IRF9350
TO MOTOR TO OTHER CHANNELS
4k
TO OTHER CHANNELS 10 IRF532
REQUIRED FOR BRAKE AND FAST REVERSE
15 21 26 3 24 23 8 9 10 4 5 7
20 10k
BRAKE
3nF CT
100nF 68k RT 5nF 100nF 2nF 2nF 2nF FROM HALL SENSORS 240 5nF 0.02 RS REQUIRED FOR AVERAGE CURRENT SENSING 0.02 RD
240
UDG-99045
Figure 13. 45V/8A brushless DC motor drive circuit.
N-Channel power MOSFETs are used for low-side drivers, while P-Channel power MOSFETs are shown for high-side drivers. Resistors are used to level shift the UC3625 open-collector outputs, driving emitter followers into the MOSFET gate. A 12V zener clamp insures that the MOSFET gate-source voltage will never exceed 12V. Series 10 gate resistors tame gate reactance, preventing oscillations and minimizing ringing. The oscillator timing capacitor should be placed close to pins 15 and 25, to keep ground current out of the capacitor. Ground current in the timing capacitor causes oscillator distortion and slaving to the commutation signal. The potentiometer connected to pin 1 controls PWM duty cycle directly, implementing a crude form of speed control. This control is often referred to as "voltage mode" because the potentiometer position sets the average motor voltage. This controls speed because
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steady-state motor speed is closely related to applied voltage. Pin 20 (Tach-Out) is connected to pin 7 (SPEED IN) through an RC filter, preventing direction reversal while the motor is spinning quickly. In two-quadrant operation, this reversal can cause kinetic energy from the motor to be forced into the power MOSFETs. A diode in series with the low-side MOSFETs facilitates PWM current control during braking by insuring that braking current will not flow backwards through low-side MOSFETs. Dual current-sense resistors give continuous current sense, whether braking or running in four-quadrant operation, an unnecessary luxury for two-quadrant operation. The 68k and 3nF tachometer components set maximum commutation time at 140s. This permits smooth operation up to 35,000 RPM for four-pole motors, yet gives 140s of noise blanking after commutation. 13
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