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| STP2230SOP July 1997 XB1 DATA SHEET DESCRIPTION The STP2230SOP crossbar switch [1] acts as the bridge among three UltraSPARC UPA devices. One of the buses is dedicated to interfacing to system memory, while the other two are general-purpose buses. These buses are used for interfacing memory, a processor bus, and an I/O bus. In this particular configuration, eighteen XB1s are required per system implementation. Crossbar Switch FEATURES * Three-port crossbar - 16-bit data - 8-bit processor - 4-bit data ports * Decoupled memory port; loading and unloading of memory data can take place in parallel with other operations * Burst transfers operate on four bytes of data per slice * Power-up safe buses; all buses power up tristated so there will be no bus contention with other parts which may be on the buses * Implemented in 0.8-micron BiCMOS and housed in a 48-pin TSSOP package (also called DGG or "shrink-wide bus") 1. The STP2230SOP crossbar switch is also referred to as BMX. 1 STP2230SOP XB1 Crossbar Switch BLOCK, LOGIC, AND TYPICAL APPLICATION DIAGRAMS Chip Boundary IMR_DATA[3:0] A_BUS[15:0] MRB_CTRL MWB_CTRL Memory Data Interface Block IMW_DATA[3:0] PW_DATA[7:0] I/O Data Interface Block PIR_DATA[7:0] Processor Data Interface Block C_BUS[3:0] X_MIE X_MIO X_MPE X_MPO Command Decode Block BMX_CMD[3:0] X_PM X_IM X_PIB X_PIS X_IPB X_IPS X_IDLE X_RESET X_TEST B_BUS[7:0] PMR_DATA[7:0] SYS_CLK Note: In previous documentation, the A_BUS, B_BUS, and C_BUS were referred to as M_BUS, P_BUS, and I_BUS respectively. Figure 1. STP2230SOP Block Diagram STP2230SOP Memory Data Bus 16 MWB_CTRL MRB_CTRL BMX_CMD [3:0] 4 CLK - CLK + SEL[3:0] B[7:0] 8 Processor Data Bus A[15:0] C[3:0] 4 I/O Data Bus Figure 2. STP2230SOP Logic Diagram 2 July 1997 XB1 Crossbar Switch STP2230SOP Processor Data Bus, B[143:0] STP2230SOP Crossbar Switch Array (18) (XB1) Memory Data Bus, A[288:0] I/O Data Bus C[71:0] STP2220SOP UPA-to-SBus Interface (U2S) A[35:0] STAT Controls SBus 144 144 Cmd/Ctrl UltraSPARC A[35:0] STP2200SOP Uniprocessor System Controller (USC) MEMADDR[12:0] RAS[3:0] CAS[3:0] WE Memory SIMMs Figure 3. STP2230SOP Typical Application Diagram July 1997 3 STP2230SOP XB1 Crossbar Switch SIGNAL DESCRIPTIONS Signal A[15:0] B[7:0] C[3:0] MRB_CTRL MWB_CTRL CLK+, CLK- BMX_CMD[3:0] I/O I/O I/O I/O I I I I No. Pins 16 8 4 1 1 2 4 Description Bidirectional data from memory bus. Processor port, bidirectional, registered Input/output port, bidirectional, registered Memory read buffer control Memory write buffer control Differential clock signals Command input signals I/F Type LV TTL, 5-volt tolerant LV TTL LV TTL LV TTL LV TTL 3.3-V PECL LV TTL 4 July 1997 XB1 Crossbar Switch STP2230SOP ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings [1] Symbol VDD VCC VIN VIN_A_BUS IIN IOUT TST FCLK DC supply voltage DC supply voltage Input voltage range Input voltage range (A_bus) DC input current DC output current Storage temperature Clock frequency STP2230SOP-83 STP2230SOP-100 - 50 - 65 0.050 0.050 Parameter Min - 0.5 - 0.5 - 0.5 - 0.5 Max 4.6 6.0 VDD + 0.5 VCC + 0.5 -18 50 150 83.34 100 Units V V V V mA mA C MHz MHz 1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions Symbol VDD VCC TC TJ DC supply voltage DC supply voltage Case temperature Junction temperature Parameter Min 3.15 4.75 0 0 Typ 3.3 5.0 - - Max 3.45 5.25 75 105 Units V V C C Capacitance Symbol CIN COUT CIO Parameter Input capacitance Output capacitance Input/Output capacitance Conditions Any input Any output Min - - - Max 6 8 10 Units pF pF pF July 1997 5 STP2230SOP XB1 Crossbar Switch DC Characteristics Symbol VIL VIH VIL VIH VDIFF VOL VOH ICC IDD Parameter Voltage input low Voltage input high PECL clock voltage input low PECL clock voltage input high Input differential voltage (PECL inputs) Voltage output low Voltage output high VCC input current VDD input current IOL = 8 mA IOH = -8 mA 2.4 0.8 - 2.4 1 0.2 0.5 - 35 35 Conditions Min - 2.0 Typ Max 0.8 - 1.6 Units V V V V V V V mA mA AC Characteristics -83 Symbol tCO,UPA tVO,UPA tCO,M tVO,M tSPI tSM tHPI tHM tCYCLE tWL tWH Parameter Clock to output for processor and I/O ports [1] 0.5 6 TBD 2.0 4.0 0.5 2.0 12 5.4 5.4 2.0 4.0 0.5 2.0 10 4.4 4.4 Min Typ Max 5.4 0.5 6 TBD Min -100 Typ Max 5.4 Unit ns ns ns ns ns ns ns ns ns ns ns Clock to output for processor and I/O ports Clock to output for memory port Clock to output valid for memory port Input setup time for processor and I/O ports Input setup time for memory port Input hold time for processor and I/O ports Input hold time for memory port Clock cycle time Clock minimum low width Clock minimum high width 1. Note: tCO is specified with a 50 pF loading. This timing improves with a 3.1 nS with a 25 pF loading. AC Characteristics - Clock Signal -83 Symbol FCLK Clock Frequency Parameter Min 0.1 Typ Max 83.4 Min 0.1 -100 Typ Max 100 Unit MHz 6 July 1997 XB1 Crossbar Switch STP2230SOP -83 Symbol tCYCLE tWL tWH tE Clock cycle time Clock minimum low width Clock minimum high width Clock rise/fall time Parameter Min 12 5.4 5.4 250 600 Typ Max Min 10 4.4 4.4 250 -100 Typ Max Unit ns ns ns 600 ps July 1997 7 STP2230SOP XB1 Crossbar Switch tCYCLE tWH CLK+ tWL tE(RISE) 3.0V 0.0V tE(FALL) 3.0V CLK- tSU tH 0.0V Input VDD/2 tVO Output 1.5V tCO Figure 4. Signal Timing Definition 8 July 1997 XB1 Crossbar Switch STP2230SOP TIMING DIAGRAMS 0 CLK MRB_CTRL BMX_CMD A[15:0] C[3:0] MI* D[0:3] D0 D1 D2 D[4:7] D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 Figure 5. Basic Memory Read to I/O Ports 0 CLK MRB_CTRL BMX_CMD A[15:0] C[3:0] MI* D[0:3] D0 D1 D2 D3 D[4:7] D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 Figure 6. Memory Read to I/O Port Controlled by MRB_CTRL 0 CLK MRB_CTRL BMX_CMD A[15:0] B[7:0] MP* D[0:3] D0, D1 D[4:7] D2, D3 D4, D5 D6, D7 1 2 3 4 5 6 7 8 9 10 11 Figure 7. Basic Memory Read to Processor 0 CLK MRB_CTRL BMX_CMD A[15:0] B[7:0] MP* D[0:3] D0, D1 D2, D3 D[4:7] D4, D5 D6, D7 1 2 3 4 5 6 7 8 9 10 11 Figure 8. Memory Read to Processor Controlled by MRB_CTRL July 1997 9 STP2230SOP XB1 Crossbar Switch 0 CLK BMX_CMD B[7:0] MWB_CTRL A[15:0] PM 1 2 3 4 5 6 7 8 9 10 11 D0, D1 D2, D3 D4, D5 D6, D7 D[0:3] D[4:7] Figure 9. Basic Memory Write From Processor 0 CLK BMX_CMD C[3:0] MWB_CTRL A[15:0] D[0:3] D[4:7] IM D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 Figure 10. Basic Memory Write From I/O Ports 0 CLK BMX_CMD B[7:0] C[3:0] PIS D0, D1 D0 D1 1 2 3 4 5 6 7 8 9 10 11 Figure 11. Single Transfer From Processor to I/O Port 0 CLK BMX_CMD B[7:0] C[3:0] PIB D0, D1 D2, D3 D4, D5 D0 D6, D7 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 Figure 12. Block Transfer From Processor to I/O Port 10 July 1997 XB1 Crossbar Switch STP2230SOP 0 CLK BMX_CMD C[3:0] B[7:0] IPS 1 2 3 4 5 6 7 8 9 10 11 D0 D1 D0, D1 Figure 13. Single Transfer From I/O to Processor 0 CLK BMX_CMD C[3:0] B[7:0] IPB D0 D1 D2 D3 D0, D1 D4 D5 D2, D3 D6 D7 D4, D5 D6, D7 1 2 3 4 5 6 7 8 9 10 11 Figure 14. Block Transfer From I/O to Processor 0 CLK CMD P_BUS{7:0] I_BUS[3:0] M_BUS[15:0] 1 2 3 4 5 6 7 8 9 10 11 TEST D0, D1 TEST D2, D3 D0 TEST D4, D5 D2 TEST D6, D7 D4 D4, 5, 4, 5 IDLE IDLE IDLE IDLE D0, 1, 0, 1 D2, 3, 2, 3 Figure 15. X_TEST Basic Timing 0 CLK CMD P_BUS{7:0] I_BUS[3:0] M_BUS[15:0] 1 2 3 4 5 6 7 8 9 10 11 TEST D0, D1 TEST D2, D3 D1 TEST D4, D5 D3 TEST D6, D7 D5 D4, 5, 4 IDLE IDLE IDLE IDLE D0, 1, 0, 1 D2, 3, 2, 3 Figure 16. X_TEST2 Basic Timing July 1997 11 STP2230SOP XB1 Crossbar Switch 0 CLK BMX_CMD B[7:0] C[3:0] A[15:0] RESET 1 2 3 4 5 6 7 8 9 10 11 IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE Figure 17. RESET Basic Timing 12 July 1997 XB1 Crossbar Switch STP2230SOP PACKAGE INFORMATION 48-Pin SOP Pin Assignments Pin 1 2 3 4 5 6 7 8 Signal Name BMX_CMD0 BMX_CMD1 A0 GND A1 A2 VCC A3 Pin 9 10 11 12 13 14 15 16 Signal Name A4 GND Pin 17 18 19 20 21 22 23 24 Signal Name A10 VCC A11 A12 GND Pin 25 26 27 28 29 30 31 32 Signal Name MWB_CTRL MRB_CTRL C3 GND CLK - CLK + VDD C2 Pin 33 34 35 36 37 38 39 40 Signal Name C1 GND C0 B7 B6 B5 GND B4 Pin 41 42 43 44 45 46 47 48 Signal Name B3 VDD B2 A5 A6 A7 A8 GND A9 B1 GND B0 BMX_CMD2 BMX_CMD3 A13 A14 A15 Top View BMX_CMD0 BMX_CMD1 A0 GND A1 A2 VCC A3 A4 GND A5 A6 A7 A8 GND A9 A10 VCC A11 A12 GND A13 A14 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 25 25 BMX_CMD3 BMX_CMD2 B0 GND B1 B2 VDD B3 B4 GND B5 B6 B7 C0 GND C1 C2 VDD CLK + CLK - GND C3 MRB_CTRL MWB_CTRL July 1997 13 STP2230SOP XB1 Crossbar Switch 48-Pin SOP Package Dimensions 0,50 48 0,30 0,15 25 0,08 M 6,40 6,00 8,40 7,80 0,15 NOM Gage Plane 1 A 0-5 0,60 0,40 24 0,25 Seating Plane 1,20 MAX 0,10 MIN 0,10 Dimension A Max Min mm 12.80 12.40 Note: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions include mold flash or protrusion. 14 July 1997 XB1 Crossbar Switch STP2230SOP ORDERING INFORMATION Part Number STP2230SOP STP2230SOP-100 Speed 83 MHz 100 MHz Crossbar switch for the UPA bus Crossbar switch for the UPA bus Description Documnet Part Number: 802-7955-02 July 1997 15 STP2230SOP XB1 Crossbar Switch 16 July 1997 |
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