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LH1548
LH1548
DESCRIPTION
The LH1548 is a 240-output segment driver IC suitable for driving large/medium scale dot matrix LCD panels, and is used in personal computers/ work stations. Through the use of UST (Ultra Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. When combined with the LH1530 common driver, it can create a low power consuming, highresolution LCD.
240-output LCD Segment Driver IC
PIN CONNECTIONS
272-PIN TCP
Y1 1 Y2 Y3
TOP VIEW
FEATURES
CHIP SURFACE
* * * *
* * * * * *
*
Number of LCD drive outputs : 240 Supply voltage for LCD drive : +10.0 to +42.0 V Supply voltage for the logic system : +2.5 to +5.5 V Shift clock frequency - 25 MHz (Max.) : VDD = +5.00.5 V - 15 MHz (Max.) : VDD = +3.0 to +4.5 V - 12 MHz (Max.) : VDD = +2.5 to +3.0 V Low power consumption Low output impedance Adopts a data bus system 8-bit/12-bit parallel input modes are selectable with a mode (MD) pin. Automatic transfer function of an enable signal Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 240 bits of input data Package : 272-pin TCP (Tape Carrier Package)
272 V0R V2R V3R V5R VSS TEST2 TEST1 MD SHL FR EIO1 LP DISPOFF XCK DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 EIO2 VDD V5L V3L V2L 241 V0L
Y238 Y239 Y240 240
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
LH1548
PIN DESCRIPTION
PIN NO. 1 to 240 241, 272 242, 271 243, 270 244, 269 245 264 265 246, 262 247 to 258 259 260 261 263 266, 267 268 SYMBOL Y1-Y240 V0L, V0R V2L, V2R V3L, V3R V5L, V5R VDD SHL MD EIO2, EIO1 DI0-DI11 XCK LP FR TEST1, TEST2 VSS I/O O - - - - - I I I/O I I I I I I - DESCRIPTION LCD drive output Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for logic system (+2.5 to +5.5 V) Input for selecting the reading direction of display data Mode selection input Input/output for chip selection Display data input Clock input for taking display data Control input for output of non-select level Latch pulse input for display data AC-converting signal input for LCD drive waveform Test mode selection input Ground (0 V)
BLOCK DIAGRAM
V0R 260 272 V2R 271 V3R 270 V5R 269 Y1 1 Y2 2 Y239 239 Y240 240 244 V5L FR 263 EIO1 262 EIO2 246 LEVEL SHIFTER ACTIVE CONTROL 240-BIT 4-LEVEL DRIVER 243 V3L
240
240-BIT LEVEL SHIFTER
240
242 V2L 241 V0L
240-BIT LINE LATCH
48 48 48 48 48
LP 261 XCK 259 SHL 264 MD 265
CONTROL LOGIC
24
24 BITS x 2 DATA LATCH
DATA LATCH CONTROL
SP CONVERSION & DATA CONTROL (8 to 24 or 12 to 24)
TEST CIRCUIT
247 DI0
248 DI1
249 DI2
250 DI3
251 DI4
252 DI5
253 DI6
254 DI7
255 DI8
256 DI9
257 258 266 267 245 DI10 DI11 TEST1 TEST2 VDD
268 VSS
2
LH1548
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK FUNCTION Controls the selection or non-selection of the chip. Following an LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 240 bits of data have been read in. Once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. SP Conversion & Data Control Data Latch Control Data is retained until 24 bits have been completely input, after which they are put on the internal data bus 24 bits at a time. Selects the state of the data latch which reads in the data bus signals. The shift direction is controlled by the control logic. For every 48 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. Latches the data on the data bus. The latch state of each LCD drive output pin is controlled by the control logic and the data latch control; 240 bits of data are read in 10 sets of 24 bits. Line Latch Level Shifter 4-Level Driver All 240 bits which have been read into the data latch are simultaneously latched at the falling edge of the LP signal, and are output to the level shifter block. The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the driver block. Drives the LCD drive output pins from the latch data, and selects one of 4 levels (V0, V2, V3 or V5) based on the FR and signals. Controls the operation of each block. When an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 240 bits of data are read in, and the chip is non-selected. Test Circuit The circuit for testing. During normal operation, it isn't activated.
Active Control
Data Latch
Control Logic
3
LH1548
INPUT/OUTPUT CIRCUITS
VDD
I
To Internal Circuit
VSS (0 V)
Applicable pins DI11-DI0, XCK, LP, SHL, FR, MD, , TEST1, TEST2
Fig. 1 Input Circuit
VDD
To Internal Circuit
VDD VSS (0 V) I Output Signal
O Control Signal VSS (0 V)
Applicable pins EIO1, EIO2
Fig. 2 Input/Output Circuit
V0
V0
V2
Control Signal 1
Control Signal 2
O
Control Signal 3
Control Signal 4
VSS (0 V)
V3
VSS (0 V)
V5
Applicable pins Y1-Y240
Fig. 3 LCD Drive Output Circuit
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LH1548
FUNCTIONAL DESCRIPTION Pin Functions
SYMBOL VDD VSS V0L, V0R V2L, V2R V3L, V3R V5L, V5R FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage * Normally use the bias voltages set by a resistor divider. * Ensure that voltages are set such that VSS V5 < V3 < V2 < V0. * ViL and ViR (i =
0, 2, 3, 5)
aren't connected with inside IC. Therefore, it is necessary that
these pins connect with an external power supply. Input pins for display data * In 8-bit parallel input mode, input data into the 8 pins, DI7-DI0. Connect DI11-DI8 to VSS or VDD.
DI11-DI0
* In 12-bit parallel input mode, input data into the 12 pins, DI11-DI0. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Clock input pin for taking display data * Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data * Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data * When set to VSS level "L", data is read sequentially from Y240 to Y1.
XCK LP
SHL
* When set to VDD level "H", data is read sequentially from Y1 to Y240. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Control input pin for output of non-select level * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. * When set to VSS level "L", the LCD drive output pins (Y1-Y240) are set to level V5. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD driving waveform * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. * Normally it inputs a frame inversion signal. * The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Mode selection pin * When set to VSS level "L", 8-bit parallel input mode is set.
FR
MD
* When set to VDD level "H", 12-bit parallel input mode is set. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations.
5
LH1548
SYMBOL Input/output pins for chip selection * When SHL input is at VSS level "L", EIO1 is set for output, and EIO2 is set for input. * When SHL input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output. * During output, set to "H" while LP* is "H", and after 240 bits of data have been read, set to "L" for one cycle (from rising edge to rising edge of XCK), after which it returns to "H". * During input, the chip is selected while * is "H" after the LP signal is input. The chip is non-selected after 240 bits of data have been read. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. TEST1 TEST2 Test mode selection pins * During normal operation, fix to VSS level "L". LCD drive output pins * Corresponding directly to each bit of the data latch, one level (V0, V2, V3, or V5) is selected and output. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations. FUNCTION
EIO1 EIO2
Y1-Y240
6
LH1548
Functional Operations
TRUTH TABLE
FR L L H H X LATCH DATA L H L H X H H H H L LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240) V3 V5 V2 V0 V5
NOTES :
* VSS V5 < V3 < V2 < V0, L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care * "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage which is assigned by specification for each power pin.
RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS (a) 8-bit Parallel Input Mode
MD SHL EIO1 EIO2 DATA NUMBER OF CLOCKS 3 CLOCK 2 CLOCK 1 CLOCK Y217 Y225 Y233 Y218 Y219 Y220 Y221 Y222 Y223 Y224 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y234 Y235 Y236 Y237 Y238 Y239 Y240 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 INPUT 30 CLOCK 29 CLOCK 28 CLOCK DI0 Y1 Y9 Y17 DI1 DI2 L L Output Input DI3 DI4 DI5 DI6 DI7 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y232 Y231 Y230 Y229 Y228 Y227 Y226 Y225 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y224 Y223 Y222 Y221 Y220 Y219 Y218 Y217
L
H
Input
Output
7
LH1548
(b) 12-bit Parallel Input Mode
MD SHL EIO1 EIO2 DATA NUMBER OF CLOCKS 3 CLOCK 2 CLOCK 1 CLOCK Y205 Y217 Y229 Y206 Y218 Y230 Y207 Y208 Y209 Y210 Y211 Y212 Y213 Y214 Y215 Y216 Y36 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 Y25 Y219 Y220 Y221 Y222 Y223 Y224 Y225 Y226 Y227 Y228 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y231 Y232 Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 INPUT 20 CLOCK 19 CLOCK 18 CLOCK Y1 Y13 Y25 DI0 DI1 Y2 Y14 Y26 DI2 DI3 DI4 H L Output Input DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI0 DI1 DI2 DI3 DI4 H H Input Output DI5 DI6 DI7 DI8 DI9 DI10 DI11 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 Y232 Y231 Y230 Y229 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y228 Y227 Y226 Y225 Y224 Y223 Y222 Y221 Y220 Y219 Y218 Y217 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y216 Y215 Y214 Y213 Y212 Y211 Y210 Y209 Y208 Y207 Y206 Y205
8
LH1548
CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS (a) When SHL = "L"
Top data Data flow Y240 EIO2 Y1 EIO1 SHL XCK XCK DI11 -DI0 LP MD LP MD FR FR Y240 EIO2 Y1 EIO1 SHL DI11 -DI0 XCK LP MD FR Y240 EIO2 Y1 EIO1 SHL DI11 -DI0 LP EIO2 Y240 XCK Last data
XCK LP MD FR DI11-DI0 12
VSS
(b) When SHL = "H"
VDD 12
DI11-DI0 FR MD LP XCK FR MD LP XCK FR
MD
LP
XCK
DI11 -DI0
DI11 -DI0
SHL VSS EIO1 Y1 EIO2 Y240 Data flow Top data
SHL EIO1 Y1 EIO2 Y240
SHL EIO1 Y1
DI11 -DI0
FR MD
Last data
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LH1548
TIMING CHART OF 4-DEVICE CASCADE CONNECTION
FR
LP
XCK
TOP DATA DI11-DI0 n* 1 2 device A EI (device A) EO (device A) EO (device B) EO (device C) n* 1 2 device B n* 1 2 device C n* 1 2 device D
LAST DATA n* 1 2
H L
* n = 30 in 8-bit parallel input mode. n = 20 in 12-bit parallel input mode.
10
LH1548
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows. o When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power. o It is advisable to connect the serial resistor (50 to 100 $) or fuse to the LCD drive power V0 of the system as a current limiter. Set up a suitable value of the resistor in consideration of the display grade. And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on function. After that, cancel the function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level V5 on function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here.
VDD
VDD VSS VDD VSS V0
V0 VSS
11
LH1548
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage (1) SYMBOL VDD V0 Supply voltage (2) V2 V3 V5 Input voltage Storage temperature VI TSTG APPLICABLE PINS VDD V0L, V0R V2L, V2R V3L, V3R V5L, V5R DI11-DI0, XCK, LP, SHL, FR, , MD, EIO1, EIO2, TEST1, TEST2 -45 to +125 C RATING -0.3 to +7.0 -0.3 to +45.0 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 -0.3 to VDD + 0.3 UNIT V V V V V V 1, 2 NOTE
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to VSS (0 V).
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage (1) Supply voltage (2) Operating temperature SYMBOL VDD V0 TOPR APPLICABLE PINS VDD V0L, V0R MIN. +2.5 +10.0 -20 TYP. MAX. +5.5 +42.0 +85 UNIT V V C NOTE 1, 2
NOTES :
1. The applicable voltage on any pin with respect to VSS (0 V). 2. Ensure that voltages are set such that VSS V5 < V3 < V2 < V0.
12
LH1548
ELECTRICAL CHARACTERISTICS DC Characteristics
(VSS = V5 = 0 V, VDD = +2.5 to +5.5 V, V0 = +10.0 to +42.0 V, TOPR = -20 to +85 C)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current I/O leakage current Output resistance Standby current Supply current (1) (Non-selection) Supply current (2) (Selection) Supply current (3) SYMBOL CONDITIONS VIL VIH VOL VOH ILI ILI/O IOL = +0.4 mA IOH = -0.4 mA VSS VI VDD APPLICABLE PINS MIN. DI11-DI0, XCK, LP, SHL, FR, MD, EIO1, EIO2, 0.7VDD EIO1, EIO2 All input pins EIO1, EIO2 1.0 Y1-Y240 VSS VDD VDD V0L, V0R 1.5 2.0 VDD - 0.4 10.0 10.0 1.5 2.0 2.5 75.0 2.4 14.4 2.0 TYP. MAX. UNIT 0.3VDD V V +0.4 V V A A k$ A mA mA mA 1 2 3 4 NOTE
VSS VI VDD V0 = 40 V |VON| V0 = 30 V RON = 0.5 V V0 = 20 V ISTB IDD1 IDD2 I0
NOTES :
1. VDD = +5.0 V, V0 = +40.0 V, VIH = VDD, VIL = VSS. 2. VDD = +5.0 V, V0 = +40.0 V, fXCK = 25 MHz, no-load, EI = VDD. The input data is turned over by data taking clock (8-bit parallel input mode). 3. VDD = +5.0 V, V0 = +40.0 V, fXCK = 25 MHz, no-load, EI = VSS. The input data is turned over by data taking clock (8-bit parallel input mode). 4. VDD = +5.0 V, V0 = +40.0 V, fXCK = 25 MHz, fLP = 38.4 kHz, fFR = 80 Hz, no-load. The input data is turned over by data taking clock (8-bit parallel input mode).
13
LH1548
AC Characteristics
(Mode 1) (VSS = V5 = 0 V, VDD = +5.00.5 V, V0 = +10.0 to +42.0 V, TOPR = -20 to +85 C, the figure in parenthesis applies when TOPR1 = -20 to +60 C)
SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tS tR tF tD tPD1 tPD2 CONDITIONS tR, tF 7 (5) ns MIN. 40 (36) 12 14 5 15 15 5 25 25 25 5 (4) TYP. UNIT ns ns ns ns ns ns ns ns ns ns ns 50 ns 50 ns 28 (27) ns 1.2 s 1.2 s MAX. NOTE 1
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time Output delay time (1) Output delay time (2) Output delay time (3)
2 2
CL = 15 pF CL = 15 pF CL = 15 pF
NOTES :
1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Mode 2)
(VSS = V5 = 0 V, VDD = +3.0 to +4.5 V, V0 = +10.0 to +42.0 V, TOPR = -20 to +85 C, the figure in parenthesis applies when TOPR1 = -20 to +60 C)
SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tS tR tF tD tPD1 tPD2 CONDITIONS tR, tF 10 ns MIN. 66 (60) 23 (20) 23 (20) 10 25 (20) 30 10 30 30 30 12 (10) TYP. UNIT ns ns ns ns ns ns ns ns ns ns ns 50 ns 50 ns 44 (40) ns 1.2 s 1.2 s MAX. NOTE 1
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time Output delay time (1) Output delay time (2) Output delay time (3)
2 2
CL = 15 pF CL = 15 pF CL = 15 pF
NOTES :
1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
14
LH1548
(Mode 3) (VSS = V5 = 0 V, VDD = +2.5 to +3.0 V, V0 = +10.0 to +42.0 V, TOPR = -20 to +85 C)
SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tS tR tF tD tPD1 tPD2 CONDITIONS tR, tF 10 ns MIN. 82 28 28 10 30 30 10 30 30 30 15 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s NOTE 1
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time Output delay time (1) Output delay time (2) Output delay time (3)
CL = 15 pF CL = 15 pF CL = 15 pF
50 50 57 1.2 1.2
2 2
NOTES :
1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
15
LH1548
Timing Chart
tWLPH LP tLD tLS XCK tR tWCK DI11-DI0 LAST DATA tF tDS TOP DATA tDH tSL tLH tWCKH tWCKL
Fig. 4 Timing Characteristics (1)
LP XCK tS EI EO tD 1 2 n*
* n = 30 in 8-bit parallel input mode. n = 20 in 12-bit parallel input mode.
Fig. 5 Timing Characteristics (2)
LP
FR tPD2 tPD1 tPD2 tPD1 V0 V2 Y1-Y240 V3 V5
Fig. 6 Timing Characteristics (3)
16
LH1530 x 4 DIO1 O1-O120 50-100 $ SHL FR MODE CK DISP DIO2 OFF DIO1 O1-O120 SHL FR MODE CK DISP DIO2 OFF DIO1 SHL MODE FR CK DISP DIO2 OFF DIO1 SEG2 SEG1 O1-O120 SHL FR MODE CK DISP DIO2 OFF Y1-Y240 COM479 COM480 O1-O120 COM1 COM2
VEE
V0
R
V1
R V2 (n - 4) R V3 R V4 R V5
1 920 x 480 DOT MATRIX LCD PANEL
SYSTEM CONFIGURATION EXAMPLE
VDD
VSS
SEG1920 SEG1919
17
6 6 EIO1 FR MD LP SHL DISP DI11OFF DI0 XCK EIO2 12
(Case of 1/n bias)
Y1-Y240
Y1-Y240
Y1-Y240
YD FR LP
XCK EIO1 FR MD LP SHL DISP DI11OFF DI0 XCK EIO2 EIO1 FR MD LP SHL DISP DI11OFF DI0 XCK EIO2 EIO1 FR MD LP SHL DISP DI11OFF DI0 XCK EIO2
Controller
XD11-XD0
LH1548 x 8
LH1548
LH1548F
0.4 (SL) 0.2 (SL) V0L V0L V2L V3L V5L NC VDD NC EIO2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 XCK DISPOFF LP EIO1 FR SHL NC NC VSS V5R V3R V2R V0R V0R [0.4] Film center Device center 11.500.7 10.65 (SL) 19.80 (SL) [19.2 (E.L.)] 18.9MAX. (Resin area) P0.60 x (31 - 1) = 18.000.03 O2.0 (Good device hole) W0.30.02 O1.0 (PI) O1.2 (Cu) 11.9 (PI) 0.25 (SL) 0.5 (PI) [2.25 (E.L.)] 0.9 (SL) 10.65 (SL) [0.4]
PACKAGE
0.9 (SL)
0.1+0.15 (SL) -0.10
Sprocket center
0.15MAX. Pattern side
Chip center
1.0MAX. Total
0.75MAX. Backside
0.224
0.95MAX. (Resin area)
1.350.7
UPILEX is a trademark of UBE INDUSTRIES, LTD..
[5.5 (E.L.)] 0.95 (SL) 3.65 (SL) [3.25 (E.L.)] 1.35 (SL) 6.25 (SL) 0.60 (SL) 0.6 (SL) 6.15
2.250.03
3.75 (SR)
NC6 NC5 NC4 Y240 Y239
o Tape Specification
Tape width Tape type Perforation pitch 35 mm Wide 2 pitches
PACKAGES FOR LCD DRIVERS
Y2 Y1 NC3 NC2 NC1
------------------------------
18
[1.0 (E.L.]) 0.6 (SL) 8.0 (SL) 0.6 (SL) 1.150.2(SR) 1.9810.05 0.6 (SL) 17.6550.025 9.45 (SL) 19.8 (SL) 22.0 (SL) 9.45 (SL) P0.07 x (246 - 1) = 17.150.025
1.35MAX. (Resin area)
0.60 (SL)
0.2380.02 [0.15]
[1.9MIN.] [0.5 (SR)] [0.4]
0.2380.02
o Tape Material
Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 #7100 SLP 18 m Epoxy resin
0.212
(Unit : mm)

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