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HD-LINX TM GS1511
HDTV Serial Digital Formatter
DATA SHEET KEY FEATURES * SMPTE 292M compliant * NRZ(I) encoding * SMPTE 292M scrambler with BYPASS option * selectable TRS insertion * selectable line number insertion * selectable line based CRC insertion * selectable active picture illegal code re-mapping * 20 bit 3.3V CMOS compatible input data bus * optimized output interface to GS1522 * Pb-free and Green * single +3.3V power supply * 5V tolerant I/O APPLICATIONS * SMPTE 292M Serial Digital Interfaces DESCRIPTION The GS1511 HDTV Serial Digital Formatter formats the HDTV Luma and Chroma data according to SMPTE 292M prior to serialization by the GS1522 HDTV Serializer. The GS1511 optionally inserts TRS and line number signals based on externally supplied H, V and F signals. The device also allows the insertion of CRCs based on TRS signals embedded in the input data streams, should the user choose not to supply external HVF signals. Following the insertion of TRS, Line Number, and CRC, protected words of 000-003 and 3FC to 3FF occurring during the active video period are optionally re-mapped to 004 and 3FB respectively. Prior to exiting the device SMPTE 292M compliant NRZ(I) encoding and scrambling may be performed on the data stream.
GS1511
TRS_Y/C DET_TRS 2 CODE PROTECT
TRS_INS LN_INS CRC_INS 3
BP_SC
DATA_IN [19:10] (LUMA) DATA_IN [9:0] (CHROMA) PCLK_IN INPUT BUFFER and BLANKER TRS and LINE NUMBER DETECTION ILLEGAL CODE REMAPPING
TRS INSERTION LINE NUMBER INSERTION CRC INSERTION
DATA_OUT NRZI ENCODER SMPTE SCAMBLER [19:0]
BLANK
3 [H:V:F]
RSTLN
SRST
OEN
GS1511 FUNCTIONAL BLOCK DIAGRAM
Revision Date: June 2004 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com
Document No. 52248 - 5
TABLE OF CONTENTS 1. PIN OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
2. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 DC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 AC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
GS1511
3. DETAILED DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. PACKAGE & ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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1. PIN OUT
VDD NC NC NC
VDD
TEST
1.1 PIN ASSIGNMENT
GND
GND
GND
GND
GND
GND
VDD VDD VDD VDD VDD NC NC NC NC NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GS1511
GENNUM CORPORATION
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
102
101
100
DATA_IN[19] DATA_IN[18] DATA_IN[17] DATA_IN[16] DATA_IN[15] DATA_IN[14]
DATA_OUT[19] DATA_OUT[18] DATA_OUT[17] DATA_OUT[16] DATA_OUT[15] VDD GND DATA_OUT[14] DATA_OUT[13] DATA_OUT[12] DATA_OUT[11] DATA_OUT[10] DATA_OUT[9] VDD GND DATA_OUT[8] DATA_OUT[7] VDD GND DATA_OUT[6] DATA_OUT[5] DATA_OUT[4] DATA_OUT[3] DATA_OUT[2] DATA_OUT[1] DATA_OUT[0]
VDD GND DATA_IN[13] DATA_IN[12] DATA_IN[11] DATA_IN[10]
GS1511 TOP VIEW
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 3 4 5 6 7 8 9 F V H NC NC NC NC VDD VDD VDD VDD GND GND GND GND GND GND SRST BP_SC RSTLN BLANK LN_INS TRS Y/C TRS_INS CRC_INS DET_TRS CODE_PROTECT
VDD GND DATA_IN[9] DATA_IN[8] DATA_IN[7] DATA_IN[6] DATA_IN[5] DATA_IN[4] DATA_IN[3] DATA_IN[2] DATA_IN[1] DATA_IN[0]
VDD GND
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
30 31 32 33 34 35 36 37 38
1
2
TN
NC
NC
NC
NC
NC
VDD
OEN
GND
GND
PCLK_IN
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1.2 PIN DESCRIPTIONS PIN NUMBER 1 2, 4, 14, 19, 24, 37, 46, 50, 58, 69, 79, 82, 91, 94, 110, 116, 128 3, 20, 25, 38, 47, 51, 59, 68, 78, 81, 90, 93, 99, 102, 109, 115, 127 5 NAME PCLK_IN GND TIMING Synchronous N/A TYPE Input Ground DESCRIPTION Parallel Data Clock input. 74.25MHz or 74.25/1.001MHz. Ground. Ground power supply connections.
GS1511
VDD
N/A
Power
Power. Positive power supply connections.
DET_TRS
Nonsynchronous
Input
Control Signal Input. Used to enable or disable the detection of the TRS signals embedded in the video stream. When DET _TRS is high, the device detects the TRS signals embedded in the input video stream and uses the detected HVF signals instead of the external HVF signals. When DET _TRS is low, TRS detection is disabled. The device uses the external supplied HVF signals. Control Signal Input. When BLANK is low, the device sets the accompanying LUMA and CHROMA data to their appropriate blanking levels. When BLANK is high, the LUMA and CHROMA data streams pass through this stage of the device unaltered. See timing diagram Figure 3. Ground. This pin must be connected to GND for normal operation.
6
BLANK
Synchronous wrt PCLK_IN
Input
7, 17, 95
GND
N/A
8
CODE_PROTECT
Nonsynchronous
Input
Control Signal Input. Used to enable or disable re-mapping of out-of-range words contained in the active portion of the video signal. When this signal is high, the device re-maps out-ofrange words contained within the active portion of the video signal into CCIR-601 compliant words. Values between 000-003 are re-mapped to 004. Values between 3FC and 3FF are remapped to 3FB. When this signal is low, out-of-range words in the active video region pass through the device unaltered. Control Signal Input. Line number reset signal which must be asserted once per frame at the beginning of the frame (for example, on the falling edge of the F signal). A high to low transition will reset the line number counter of the device to one (1). See Figure 2 for timing. Control Signal Input. Used to enable or bypass the SMPTE292M scrambler and NRZ(I) encoder. When BP_SC is low, the video stream is scrambled according to SMPTE 292M and NRZ(I) encoded. When BP_SC is high, the scrambler and NRZ(I) encoder are by-passed. Control Signal Input. Used to reset the SMPTE292M scrambler and NRZI encoder. When SRST is low, the scrambler and encoder operate normally. A low to high transition on SRST causes the scrambler and encoder to reset. Control Signal Input. Only used when DET_TRS is high. When TRS_Y/C is high, the device detects and uses TRS signals embedded in the LUMA (DATA_IN[19:10]) channel. When TRS_Y/C is low, the device detects and uses TRS signals embedded in the CHROMA (DATA_IN[9:0]) channel.
9
RSTLN
Synchronous wrt PCLK_IN
Input
10
BP_SC
Nonsynchronous
Input
11
SRST
Nonsynchronous
Input
12
TRS_Y/C
Nonsynchronous
Input
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1.2 PIN DESCRIPTIONS (Continued) PIN NUMBER 13 NAME TRS_INS TIMING Nonsynchronous TYPE Input DESCRIPTION Control Signal Input. Used to enable or disable insertion of TRS into the video streams. When TRS_INS is high, the device inserts SMPTE 292M compliant TRS signals into the input LUMA and CHROMA data streams based on the supplied HVF signals. When TRS_INS is low, the device does not insert TRS signals. Control Signal Input. Used to enable or disable insertion of line numbers into the video stream. When LN_INS is high, the device inserts SMPTE 292M compliant line number information into the LUMA and CHROMA channels. When LN_INS is low, the device does not insert the line number information into the LUMA and CHROMA channels. Line number insertion is only available when user supplied external FVH data is used (DET_TRS set LOW). Control Signal Input. Used to enable or disable insertion of CRCs into the video stream. When CRC_INS is high, the device calculates and inserts line based CRCs. When CRC_INS is low, this feature is disabled. This pin must be connected to VDD for normal operation.
GS1511
15
LN_INS
Nonsynchronous
Input
16
CRC_INS
Nonsynchronous
Input
18, 99, 102, 76, 77, 80, 83-89, 92, 96-98, 100, 101 21
VDD
N/A
H
Synchronous wrt PCLK_IN
Input
Control Signal Input. This signal indicates the Horizontal blanking period of the input video data stream. The device inserts HDTV TRS based on the supplied HVF signals. Refer to Figure 4 for required timing of H relative to LUMA (DATA_IN[19:10]) and CHROMA (DATA_IN[9:0]). Control Signal Input. This signal indicates the Vertical blanking period of the input video data streams. Refer to Figure 4 for required timing of V relative to LUMA (DATA_IN[19:10]) and CHROMA (DATA_IN[9:0]).
22
V
Synchronous wrt PCLK_IN
Input
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1.2 PIN DESCRIPTIONS (Continued) PIN NUMBER 23 NAME F TIMING Synchronous wrt PCLK_IN TYPE Input DESCRIPTION Control Signal Input. This signal indicates the ODD/EVEN field of the input video data streams. Refer to Figure 4 for required timing of F relative to LUMA (DATA_IN[19:10]) and CHROMA (DATA_IN[9:0]). When the input video format is progressive scan, F should remain low at all times.
GS1511
26, 27, 28, 29, 30-34, 65, 66, 67, 71-75, 35
NC
N/A
No Connect. Do not connect these pins.
TN
N/A
TEST
Test pin. Used for test purposes only. This pin must be connected to VDD for normal operation. Control Signal Input. Used to enable the DATA_OUT[19:0] output bus or set it to a high Z state. When OEN is low, the DATA_OUT[19:0] bus is enabled. When OEN is high, the DATA_OUT[19:0] bus is disabled and in a high Z state. Output Data Bus. The device generates a 20 bit wide data stream running at 74.25 (or 74.25/1.001) MHz. DATA_OUT[19] is the MSB and DATA_OUT[0] is the LSB.
36
OEN
Nonsynchronous
Input
64, 63, 62, 61, 60, 57 56, 55, 54, 53, 52, 49, 48, 45, 44, 43, 42, 41, 40, 39 70
DATA_OUT[19:0]
Synchronous wrt PCLK_IN
Outputs
TEST
N/A
TEST
Test Pin. Used for test purposes only. This pin must be connected to GND for normal operation. Input Data Bus. LUMA CHANNEL. DATA_IN [19] is the MSB of the LUMA input signal (pin 103). DATA_IN [10] is the LSB of the LUMA input signal (pin 114).
103,104,105, 106, 107, 108, 111, 112, 113, 114 117, 118, 119, 120, 121, 122, 123, 124, 125, 126
DATA_IN [19:10] (LUMA channel)
Synchronous wrt PCLK_IN
Input
DATA_IN [9:0] (CHROMA channel)
Synchronous wrt PCLK_IN
Input
CHROMA Input Data Bus. CHROMA CHANNEL DATA_IN [9] is the MSB of the CHROMA signal (pin 117). DATA_IN [0] is the LSB of the CHROMA signal (pin 126).
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2. ELECTRICAL CHARACTERISTICS
2.1 ABSOLUTE MAXIUMUM RATINGS PARAMETER Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range VALUE -0.5V to +4.6V -0.5V < VIN < 5.5V
GS1511
0C TA 70C -40C TS 125C 260C
Lead Temperature (soldering 10 seconds)
2.2 DC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0C to 70C, unless otherwise shown
PARAMETER Positive Supply Voltage Supply Current Input Logic LOW Voltage Input Logic HIGH Voltage Output Logic LOW Voltage
SYMBOL VDD DD VIL VIH VOL VOH
CONDITIONS
MIN 3.0
TYP 3.3 413 3.3 0.3
MAX 3.6 480 0.8 5.0 0.4
UNITS V mA V V V
NOTES
= 74.25MHz, TA = 25C ILEAKAGE < 10A ILEAKAGE < 10A VDD = 3.0 to 3.6V, IOL= 4mA VDD = 3.0 to 3.6V, IOH = -4mA
2.1 -
Output Logic HIGH Voltage
2.6
-
-
V
2.3 AC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0C to 70C, unless otherwise shown
PARAMETER Clock Input Frequency Input Data Setup Time Input Data Hold Time Input Clock Duty Cycle Output Data Hold Time Output Enable Time Output Disable Time Output Data Delay Time Output Data Rise/Fall Time
SYMBOL FHSCI tSU tIH
CONDITIONS
MIN 2.5 1.5 40
TYP 74.25 -
MAX 80 60 8 10 10 2.75
UNITS MHz ns ns % ns ns ns ns ns
NOTES Also supports 74.25/ 1.001MHz 50% levels 50% levels
tOH toen todis tOD
With 15pF load With 15pF load With 15pF load With 15pF load With 15pF load
2.0 -
20% to 80% levels
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3. DETAILED DESCRIPTION
3.1 DATA INPUT AND OUTPUTS
3.2 INPUT BLANKER
Data enters and exits the device synchronous to the rising edge of PCLK_IN as shown in Figure 1.
Data words entering the GS1511 can be dynamically set to Luma and Chroma blanking levels if desired as shown in Figure 3. Blanking is applied to both the LUMA and CHROMA channels simultaneously.
GS1511
PCLK_IN
DATA_IN
DATA
DATA
DATA
DATA
DATA
DATA_OUT
tSU tIH
DATA
DATA
tOH tOD
Fig. 1 Synchronous I/O Timing
PCLK_IN
DATA_IN[19:0]
n Frames
3FF
000
000
XYZ (EAV ID)
LN0
LN1
EAV For Line#1
Line#1 Inserted Here
RSTLN
Transistion From Low To High Can Happen at Any Point
Fig. 2 RSTLN Timing
PCLK_IN
DATA_IN[19:0]
WORD X
WORD X+1
WORD X+2
WORD X+3
WORD X+4
WORD X+6
WORD X+7
WORD X+8
Data To Be Blanked
BLANK
Fig. 3 Timing of Dynamic Data Blanking
PCLK_IN DATA_IN[19:10] (LUMA) DATA_IN[9:0] (CHROMA) H V F
3FF 000 000 XYZ (EAV ID) XYZ (EAV ID) YLN 0 3FF 000 000 XYZ (SAV ID) XYZ (SAV ID)
3FF
000
000
CLN0
3FF
000
000
Fig. 4 HVF Input Timing
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4. REFERENCES Compliant with SMPTE 292M. 5. PACKAGE & ORDERING INFORMATION
5.1 PACKAGE DIMENSIONS
GS1511
23.20 0.25 20.0 0.10 18.50 REF
12 TYP 17.20 0.25 12.50 REF 14.0 0.10 0-7 0.13 MIN. RADIUS 1.6 REF 3.00 MAX 0.88
0.15
0.75 MIN 0 -7 0.30 MAX RADIUS
128 pin MQFP
0.50 BSC 0.27 0.08 2.80 0.25
All dimensions in millimetres
5.2 ORDERING INFORMATION PART NUMBER GS1511-CQR GS1511-CQRE3 PACKAGE 128 pin MQFP 128 pin MQFP TEMPERATURE RANGE 0C to 70C 0C to 70C Pb-FREE AND GREEN No Yes
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
REVISION NOTES: Added Pb-free and green information. For latest product information, visit www.gennum.com
GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright May 2002 Gennum Corporation. All rights reserved. Printed in Canada.
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