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XTR300
SBOS336B - JUNE 2005 - REVISED MARCH 2006
Industrial Analog Current/Voltage OUTPUT DRIVER
FEATURES
D USER-SELECTABLE: Voltage or Current D D D D
Output +40V SUPPLY VOLTAGE VOUT: 10V (up to 17.5V at 20V supply) IOUT: 20mA (linear up to 24mA) SHORT- OR OPEN-CIRCUIT FAULT INDICATOR PIN NO CURRENT SHUNT REQUIRED OUTPUT DISABLE FOR SINGLE INPUT MODE
APPLICATIONS
D D D D D
PLC OUTPUT PROGRAMMABLE DRIVER INDUSTRIAL CROSS-CONNECTORS INDUSTRIAL HIGH-VOLTAGE I/O 3-WIRE-SENSOR CURRENT OR VOLTAGE OUTPUT 10V 2- AND 4-WIRE VOLTAGE OUTPUT Patents Pending
D D D THERMAL PROTECTION D OVER-CURRENT PROTECTION D SEPARATE DRIVER AND RECEIVER
CHANNELS
DESCRIPTION
The XTR300 is a complete output driver for industrial and process control applications. The output can be configured as current or voltage by the digital I/V select pin. No external shunt resistor is required. Only external gain-setting resistors and a loop compensation capacitor are required. The separate driver and receiver channels provide flexibility. The Instrumentation Amplifier (IA) can be used for remote voltage sense or as a high-voltage, highimpedance measurement channel. In voltage output mode, a copy of the output current is provided, allowing calculation of load resistance. The digital output selection capability, together with the error flags and monitor pins, make remote configuration and troubleshooting possible. Fault conditions on the output and on the IA input as well as over-temperature conditions are indicated by the error flags. The monitoring pins provide continuous feedback about load power or impedance. For additional protection, the maximum output current is limited and thermal protection is provided. Digital communication like HART can be modulated onto the input signal. The receive signal applied to the output can be detected at the monitor pins in both current and voltage output modes. In addition to HART communication, the device offers system or sensor configuration through the signal connector. The XTR300 is specified over the -40C to +85C industrial temperature range and for supply voltage up to 40V.
D DESIGNED FOR TESTABILITY
CC
XTR300 IMON R IMON 1k Input Signal V IN SET
V+
V- Current Copy
ICOPY IDRV
(Optional)
OPA
DRV
IA IN+ R OS RSET IIA IA V REF GND1 IA OUT RIA 1k OD M1 M2 GND3 Digital Control Error Flags RG 2 IA IN- GND2 EFCM EFLD EF OT DGND RG 1
R GAIN
Load
Figure 1. XTR300 Basic Diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. HART is a registered trademark of the HART Communication Foundation. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2005-2006, Texas Instruments Incorporated
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XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V Signal Input Terminals Voltage(2) . . . . . . . . . . . . . . . . . . . . . . (V-) - 0.5V to (V+) + 0.5V Current(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Output Short Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited. (3) See the Driver Output Disable section in Application Information section for thermal protection.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT XTR300 PACKAGE-LEAD QFN-20 (5mm x 5mm) PACKAGE DESIGNATOR RGW PACKAGE MARKING XTR300
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
PIN ASSIGNMENTS
PIN 1 2 3 4 5 NAME M2 M1 VIN SET IMON IAOUT IAIN- IAIN+ RG1 RG2 V- NC DRV NC V+ DGND EFCM EFLD EFOT OD Pad FUNCTION Mode Input Mode Input Noninverting Signal Input Input for Gain Setting; Inverting Input Current Monitor Output Instrumentation Amplifier Signal Output Instrumentation Amplifier Inverting Input Instrumentation Amplifier Noninverting Input Instrumentation Amplifier Gain Resistor Instrumentation Amplifier Gain Resistor Negative Power Supply No Internal Connection Operational Amplifier Output No Internal Connection Positive Power Supply Ground for Digital I/O Error Flag for Common-Mode Over-Range, Active Low Error Flag for Load Error, Active Low Error Flag for Over Temperature, Active Low Output Disable, Disabled Low Exposed thermal pad must be connected to V-
PIN CONFIGURATION
Top View
DGND EFCM EFOT EFLD OD
QFN
6 7 8 9 10
20
19
18
17
16
M2 M1 VIN SET IMON
1 2 3 4 5
Exposed Thermal Die Pad on Underside. (Must be connected to V-)
15 14 13 12 11
V+ NC DRV NC V-
11 12 13 14 15 16 17
6 IAOUT Pad
7 IAIN-
8 IAIN+
9 RG1
10
18
RG2
19 20 Pad
2
XTR300
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ELECTRICAL CHARACTERISTICS: VOLTAGE OUTPUT MODE
Boldface limits apply over the temperature range, TA = -40C to +85C.
All specifications at TA = +25C, VS = 20V, RLOAD = 800, RSET = 2k, ROS = 2k, VREF = 4V, RGAIN = 10k, Input Signal Span 0V to 4V, and CC = 100pF, unless otherwise noted. XTR300 PARAMETER OFFSET VOLTAGE Offset Voltage, RTI vs Temperature vs Power Supply INPUT VOLTAGE RANGE Nominal Setup for 10V Output Input Voltage For Linear Operation NOISE Voltage Noise, f = 0.1Hz to 10Hz, RTI Voltage Noise Density, f = 1kHz, RTI OUTPUT Voltage Output Swing from Rail Gain Nonlinearity vs Temperature Gain Error vs Temperature Output Impedance, dVDRV/dIDRV Output Leakage Current While Output Disabled Short-Circuit Current Capacitive Load Drive Rejection of Voltage Difference between GND1 and GND2, RTO FREQUENCY RESPONSE Bandwidth Slew Rate(2) Settling Time(2)(3), 0.1%, Small Signal Overload Recovery Time VOS dVOS/dT PSRR CONDITION MIN TYP
0.4 1.6
MAX
1.9 6 10
UNITS mV V/C V/V
VS = 5V to 22V See Figure 2 (V-) + 3V
0.2
(V+) - 3V 3 40
V VPP nV/Hz
en IDRV 15mA (V-) +3V
(V+) - 3
0.01 0.1 0.1 1 0.1 1
IB
0.04 0.2
Pin OD = L(1) ISC CLOAD CC = 10nF, RC = 15(2)
15
7 30
20 24
1 130 300 1 0.015 8 12
V %FS ppm/C %FS ppm/C m nA mA F dB kHz V/s V/s s s
-3dB SR SR
G=5 CC = 10nF, CL = 1F, RC = 15 VDRV = 1V 50% Overdrive
(1) Output leakage includes input bias current of INA. (2) Refer to Driving Capacitive Loads section in Application Information. (3) 8s plus number of chopping periods. See Application Information section, Internal Current Sources and Settling Time.
CC
X TR3 00 I MON R IMON 1k Input Sig nal V IN = 0V to 4.0V GND 3 V IN S ET
V+
V- Cu rrent Copy
I COPY I DRV
OPA
DRV
Transfer Function: V OUT =
R GAIN Load
IA IN+ R OS R SET IIA IA RG 2 V REF = 4.0V IA OUT H L L OD M1 M2 D igital Contro l Error Flags IA IN- EF CM E F LD EF OT DGND V GND GND1 GND2 RG 1
RG 2
(
V IN RSET
+
VIN - VREF R OS
)
Figure 2. Standard Circuit for Voltage Output Mode
3
XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS: CURRENT OUTPUT MODE
Boldface limits apply over the temperature range, TA = -40C to +85C.
All specifications at TA = +25C, VS = 20V, RLOAD = 800, RSET = 2k, ROS = 2k, VREF = 4V, Input Signal Span 0 to 4V, and CC = 100pF, unless otherwise noted. XTR300 PARAMETER OFFSET VOLTAGE Input Offset Voltage vs Temperature vs Power Supply INPUT VOLTAGE RANGE Nominal Setup for 20V Output Maximum Input Voltage For Linear Operation NOISE Voltage Noise, f = 0.1Hz to 10Hz, RTI Voltage Noise Density, f = 1kHz, RTI OUTPUT Compliance Voltage Swing from Rail Output Conductance, (dIDRV/dVDRV) Transconductance Gain Error vs Temperature Linearity Error vs Temperature Output Leakage Current While Output Disabled Short-Circuit Current Capacitive Load Drive(1)(2) FREQUENCY RESPONSE Bandwidth Slew Rate(2) Settling Time(2)(3), 0.1%, Small Signal Overload Recovery Time VOS dVOS/dT PSRR CONDITION Output Current < 1A VS = 5V to 22V See Figure 3 (V-) + 3 3 33 IDRV = 24mA dVDRV = 15V, dIDRV = 24mA See Transfer Function IDRV = 24mA IDRV = 24mA IDRV = 24mA IDRV = 24mA Pin OD = L (V-) +3 0.7
0.04 3.6 0.01 1.5 0.12 10 0.1 6 38.5
MIN
TYP
0.4 1.5 0.2
MAX
1.8 6 10
UNITS mV V/C V/V
(V+) - 3
V VPP nV/Hz
in
(V+) - 3
V A/V %FS ppm/C %FS ppm/C nA mA F kHz mA/s s s
IB
0.6
24.5 32
ISC CLOAD -3dB SR IDRV = 2mA CLOAD = 0, 50% Overdrive
1 160 1.3 8 1
(1) Refer to Driving Capacitive Loads section in Application Information. (2) With capacitive load, the slew rate can be limited by the short circuit current and the load error flag can trigger during slewing. (3) 8s plus number of chopping periods. See Application Information section, Internal Current Sources and Settling Time.
CC
XTR300 IMON
V+
V- Current Copy
I COPY Input Signal VIN = 0V to 4.0V IDRV VIN SET OPA DRV
Transfer Function:
IAIN+ RG1
ROS
RSET
IIA IA
IOUT = 10
(
VIN RSET
+
V IN - V REF ROS
)
RG2 VREF = 4.0V IAO UT H L H GND1 OD M1 M2 Digital Control Error Flags IAIN- EFCM EFLD EFOT DGND GND2 IO UT
Figure 3. Standard Circuit for Current Output Mode
4
XTR300
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ELECTRICAL CHARACTERISTICS: OPERATIONAL AMPLIFIER (OPA)
Boldface limits apply over the temperature range, TA = -40C to +85C.
All specifications at TA = +25C, VS = 20V, RLOAD = 800, unless otherwise noted. XTR300 PARAMETER OFFSET VOLTAGE Offset Voltage, RTI Drift vs Power Supply INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio INPUT BIAS CURRENT Input Bias Current Input Offset Current INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain OUTPUT Voltage Output Swing from Rail Short-Circuit Current Output Leakage Current While Output Disabled FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate AOL (V-) + 3V < VDRV < (V+) - 3V , IDRV = 24mA IDRV = 24mA M2 = High M2 = Low Pin OD = L G=1 100 (V-) + 3
25.5 16 32 20
CONDITION VOS dVOS/dT PSRR VCM CMRR IB IOS IDRV = 0A VS = 5V to 22V
MIN
TYP
0.4 1.5 0.2
MAX
1.8 5
UNITS mV V/C V/V V dB nA nA || pF || pF dB
(V-) + 3V < VCM < (V+) - 3V
(V-) + 3 100
(V+) - 3 126
20 0.3 35 10
108 || 5 108 || 5 126 (V+) - 3
38.5 24
ILIMIT ILIMIT ILEAK_DRV GBW SR
10 2 1
V mA mA pA MHz V/s
5
XTR300
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ELECTRICAL CHARACTERISTICS: INSTRUMENTATION AMPLIFIER (IA)
Boldface limits apply over the temperature range, TA = -40C to +85C.
All specifications at TA = +25C, VS = 20V, RIA = 2k, and RGAIN = 2k, unless otherwise noted. See Figure 4. XTR300 PARAMETER OFFSET VOLTAGE Offset Voltage, RTI vs Temperature vs Power Supply INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio INPUT BIAS CURRENT Input Bias Current Input Offset Current INPUT IMPEDANCE Differential Common-Mode TRANSCONDUCTANCE (Gain) Transconductance Error vs Temperature Linearity Error Input Bias Current to G1, G2 Input Offset Current to G1, G2(1) OUTPUT Output Swing to the Rail Output Impedance Short-Circuit Current FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time(2), 0.1% Overload Recovery Time, 50%
GBW 108 || 5 108 || 5 IB IOS 20 1 35 10 VCM VOS dVOS/dT IDRV = 0A VS = 5V to 22V 0.7 2.4 0.8 2.7 10 10
CONDITION
MIN
TYP
MAX
UNITS mV V/C V/V V dB nA nA || pF || pF
PSRR
(V-) + 3 RTI 100 130
(V+) - 3
CMRR
IAOUT = 2 (IAIN+ - IAIN-)/RGAIN IAOUT = 2.4mA, (V-) + 3V < VIAOUT < (V+) - 3V (V-) + 3V < VIAOUT < (V+) - 3V
0.04 0.2 0.01 20 1
0.1 0.1
%FS ppm/C %FS nA nA
IAOUT = 2.4mA IAOUT = 2.4mA ILIMIT ILIMIT M2 = High M2 = Low G = 1, RGAIN = 10k, RIA = 5k G = 1, RGAIN = 10k, RIA = 5k IAOUT = 40A, RGAIN = 10k, RIA = 5k, CL = 100pF RGAIN = 10k, RIA = 15k, CL = 100pF
(V-) + 3 600
7.2 4.5
(V+) - 3
V M mA mA MHz V/s s s
1
1 6 10
SR
(1) See Typical Characteristics curve. (2) 6s plus number of chopping periods. See Application Information section, Internal Current Sources and Settling Time.
ELECTRICAL CHARACTERISTICS: CURRENT MONITOR
Boldface limits apply over the temperature range, TA = -40C to +85C.
All specifications at TA = +25C, VS = 20V, unless otherwise noted. See Figure 4. XTR300 PARAMETER OUTPUT Offset Current vs Temperature vs Power Supply Monitor Output Swing to the Rail Monitor Output Impedance MONITOR CURRENT GAIN Current Gain Error vs Temperature Linearity Error vs Temperature IOS dIOS/dT PSRR VS = 5V to 22V IMON = 2.4mA IMON = 2.4mA IMON = IDRV/10 IDRV = 24mA IDRV = 24mA IDRV = 24mA IDRV = 24mA
0.04 3.6 0.01 1.5 0.1 0.12
CONDITION IDRV = 0A
MIN
TYP
30 0.06 0.1
MAX
100 10
UNITS nA nA/C nA/V V M %FS ppm/C %FS ppm/C
(V-) + 3 200
(V+) - 3
6
XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the temperature range, TA = -40C to +85C.
All specifications at TA = +25C, VS = 20V, unless otherwise noted. See Figure 4. XTR300 PARAMETER POWER SUPPLY Specified Voltage Range Operating Voltage Range Quiescent Current Over Temperature TEMPERATURE RANGE Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Resistance Junction-to-Case Junction-to-Ambient THERMAL FLAG (EFOT) Output Alarm (EFOT pin LOW) Return to Normal Operation (EFOT pin HIGH) DIGITAL INPUTS (M1, M2, OD) VIL Low-Level Input Voltage VIH High-Level Input Voltage Input Current DIGITAL OUTPUTS (EFLD, EFCM, EFOT) IOH High-Level Leakage Current (Open-Drain) VOL Low-Level Output Voltage VOL Low-Level Output Voltage DIGITAL GROUND PIN Current Input (1) EFOT not connected with OD. IOL = 5mA IOL = 2.8mA (V-) DGND (V+) - 7V M1 = M2 = L, OD = H, All Digital Outputs H -25 A -1.2 0.8 0.4 A V 0.8 1.4 1 V V A 140 125 C C qJC qJA 6 38 C/W C/W -40 -55 -55 +85 +125(1) +125 C C C IQ IDRV = IAOUT = 0A VS
5 5 20 22
CONDITION
MIN
TYP
MAX
UNITS
1.8
2.3 2.8
V V mA mA
V
Feedback Network
XTR300 V+ IMON
V- Current Copy
ICOPY IDRV GND3 Input Signal SET RSET GND1 IAOUT RIA H OD M1 M2 GND3 Digital Control Error Flags VIN OPA DRV IAIN+ IIA IA RG1 RG2 IAIN- EFCM EFLD EFOT DGND RGAIN
Figure 4. Standard Circuit for Current Output Mode
7
XTR300
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TYPICAL CHARACTERISTICS
At TA = +25C and V+ = 20V, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE 3.0 2.5 2.0 IQ (mA) 1.5 1.0 0.5 0 IQ (mA) 1.90 1.88 1.86 1.84 1.82 1.80 1.78 1.76 1.74 1.72 -50 -25 1.70 0 25 50 75 100 125 10 15 20 25 30 35 40 45 Temperature (_C) Total Supply Voltage (V) QUIESCENT CURRENT vs SUPPLY VOLTAGE
INPUT BIAS CURRENT vs TEMPERATURE (VIN, SET, IAIN+, IAIN-, RG1, RG2) 0 -5 -10 IB (nA) -15 -20 -25 -30 VS - VOUT (V) 2.2
OPA OUTPUT SWING TO RAIL vs TEMPERATURE I DRV = -24mA 2.0 1.8 1.6 IDRV = +10mA 1.4 IDRV = -20mA 1.2 1.0 I DRV = -10mA IDRV = +20mA IDRV = +24mA
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (_C)
Temperature (_C)
OPA GAIN AND PHASE vs FREQUENCY 180 160 140 120 Gain (dB) 100 80 60 40 20 0 -20 0.001 0.01 0.1 1 10 100 1k 10k 100k 1M Gain Phase 0 -20 -40 -60 Gain (dB) -80 -100 -120 -140 -160 -180 -200 10M Phase (_ ) 60 80 RGAIN = 10k
IA GAIN AND PHASE vs FREQUENCY 0 -45 RIA = 500k 40 R IA = 50k 20 0 R IA = 5k -20 -40 1 Gain Phase 10 100 1k 10k RIA = 1k 100k 1M R IA = 10k -90 -135 -180 -225 -270 10M
Frequency (Hz)
Frequency (Hz)
8
Phase (_ )
XTR300
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TYPICAL CHARACTERISTICS (continued)
At TA = +25C and V+ = 20V, unless otherwise noted.
OPA CMRR AND PSRR vs FREQUENCY 160 140 CMRR, PSRR (dB) CMRR, PSRR (dB) 120 100 PSRR- 80 60 40 20 0 1 10 100 1k 10k 100k Frequency (Hz) SMALL-SIGNAL STEP RESPONSE CURRENT MODE PSRR+ CMRR 20 0 1 10 100 1k 10k 100k Frequency (Hz) LARGE-SIGNAL STEP RESPONSE CURRENT MODE 140 120 100 80 PSRR- 60 CMRR 40 PSRR+ IA CMRR AND PSRR vs FREQUENCY
100mV/div
IOUT = 200A G=8 CL = 100nF || RL = 800 CC = 4.7nF RSET = 1k RG = 10k See Figure 3 200s/div
10V/div
IOUT = 20mA G=8 CL = 100nF || RL = 800 CC = 4.7nF RSET = 1k RG = 10k See Figure 3 200s/div LARGE-SIGNAL STEP RESPONSE VOLTAGE MODE
SMALL-SIGNAL STEP RESPONSE VOLTAGE MODE
50mV/div
5V/div
G=5 CL = 100nF || RL = 800 CC = 4.7nF RSET = 1k RG = 10k See Figure 2 200s/div
G=5 CL = 100nF || RL = 800 CC = 4.7nF RSET = 1k RG = 10k See Figure 2 200s/div
9
XTR300
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TYPICAL CHARACTERISTICS (continued)
At TA = +25C and V+ = 20V, unless otherwise noted.
INPUT-REFERRED NOISE SPECTRUM VOLTAGE OUTPUT MODE 1M G =5 100k Noise (nV/Hz) 10k 1k 100 10 1 1 10 100 1k 10k 100k Frequency (Hz) 1s/div 1V/div INPUT-REFERRED 0.1Hz to 10Hz NOISE VOLTAGE OUTPUT MODE
INPUT-REFERRED NOISE SPECTRUM CURRENT OUTPUT MODE 1M G = 10 Input-Referred Noise (nV/Hz) 100k 10k 1k 100 10 1 1 10 100 1k 10k 100k Frequency (Hz) 1V/div
INPUT-REFERRED 0.1Hz to 10Hz NOISE CURRENT OUTPUT MODE
1s/div
IA INPUT-REFERRED NOISE SPECTRUM 1M G = 20 Input-Referred Noise (nV/Hz) 100k 10k 1k 100 10 1 1 10 100 1k 10k 100k 1V/div
IA INPUT-REFERRED 0.1Hz to 10Hz NOISE
1s/div
Frequency (Hz)
10
XTR300
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TYPICAL CHARACTERISTICS (continued)
At TA = +25C and V+ = 20V, unless otherwise noted.
OPA OFFSET VOLTAGE DISTRIBUTION 18 16 Percent of Population (%) 25 14 12 10 8 6 4 2 0 -2.0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 0 -3.0 -2.4 -1.8 -1.2 -0.6 0.6 1.2 1.8 2.4 8 800 3.0 10 1000 0 0 Percent of Population (%) 20 15 10 5 30 IA OFFSET VOLTAGE DISTRIBUTION
Offset Voltage (mV) OPA OFFSET VOLTAGE DRIFT DISTRIBUTION 60 50 40 30 20 10 0 -8 -6 -4 -10 -2 0 2 4 6 8 10 40 35 Percent of Population (%) 30 25 20 15 10 5 0 -10 -8 -6
Offset Voltage (mV) IA OFFSET VOLTAGE DRIFT DISTRIBUTION
Percent of Population (%)
-4
-2
2
4 400
Offset Voltage Drift (V/_ C) VOLTAGE MODE GAIN ERROR DISTRIBUTION 40 35 Percent of Population (%) 30 25 20 15 10 5 0 -400 -1000 -800 -600 -200 200 400 600 800 1000 0 Percent of Population (%) 30 25 20 15 10 5 0
Offset Voltage Drift (V/_ C) CURRENT MODE GAIN ERROR DISTRIBUTION
-400
-1000
-800
-600
-200
200
Gain Error (ppm)
Gain Error (ppm)
600
0
6
11
XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
TYPICAL CHARACTERISTICS (continued)
At TA = +25C and V+ = 20V, unless otherwise noted.
VOLTAGE MODE NONLINEARITY DISTRIBUTION 60 50 40 30 20 10 0 -1000 -800 -600 -400 -200 200 400 600 800 1000 0 Percent of Population (%) 60 50 40 30 20 10 0 -400 -1000 -800 -600 -200 200 400 600 800 8 8 1000 10 10 0 0 CURRENT MODE NONLINEARITY DISTRIBUTION
Percent of Population (%)
Nonlinearity (ppm) VOLTAGE MODE GAIN ERROR DRIFT DISTRIBUTION 70 60 Percent of Population (%) 50 40 30 20 10 0 -1.0 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 1.0 0 Percent of Population (%) 60 50 40 30 20 10 0 -10 -8 -6
Nonlinearity (ppm) CURRENT MODE GAIN ERROR DRIFT DISTRIBUTION
-4
-2
2
4 4
Gain Error Drift (ppm/_ C) VOLTAGE MODE NONLINEARITY DRIFT DISTRIBUTION 80 70 Percent of Population (%) 60 50 40 30 20 10 0 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 Percent of Population (%) 100 90 80 70 60 50 40 30 20 10 0 -10 -8 -6
Gain Error Drift (ppm/_C) CURRENT MODE NONLINEARITY DRIFT DISTRIBUTION
-4
-2
0
2
Nonlinearity Drift (ppm/_ C)
Nonlinearity Drift (ppm/_ C)
12
6
6
XTR300
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TYPICAL CHARACTERISTICS (continued)
At TA = +25C and V+ = 20V, unless otherwise noted.
POSITIVE CURRENT LIMIT vs TEMPERATURE 36 34 32 30 I LIMIT (mA) 28 26 24 22 20 18 16 -50 -25 0 25 50 75 100 125 Voltage Mode ILIMIT (mA) Current Mode -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 Temperature (_ C) -50 -25 0 25 Current Mode Voltage Mode NEGATIVE CURRENT LIMIT vs TEMPERATURE
50
75
100
125
Temperature (_C)
NONLINEARITY vs OUTPUT CURRENT (24mA End Point Calibration) 0.025 +25_ C 0 Nonlinearity (%) Nonlinearity (%) -0.025 -0.050 -0.075 -0.10 -55_ C 0 -0.025 -0.050 -0.075 -0.10 0 4 8 12 16 20 24 0.025
NONLINEARITY vs OUTPUT CURRENT (20mA End Point Calibration) +25_C -55_C
+85_ C
+125_C
+85_C
+125_ C
-24 -20 -16 -12 -8
-4
-24 -20 -16 -12 -8
-4
0
4
8
12
16
20
24
Output Current (mA)
Output Current (mA)
13
XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
APPLICATION INFORMATION
V+ C2 100nF C3 100nF V- GND
CC 47nF
GND1
(2)
XTR300 I MON R3 1k S-IN ROS 2k OS RIMON 1k SG GND1 IA-O IAOUT RIA 1k OD M1 M2 GND3 RSET
V+
V-
Thermal Pad
Current Copy ICOPY
I-MON
VIN OPA SET
IDRV DRV
RC 15 C4 100nF
External Load
IAIN+ I IA IA RG2 IAIN- EFCM Digital Control Error Flags EFLD EFOT DGND
(1)
GND1 RGAIN 10k C5 10nF
R6 2.2k CLOAD R7 2.2k GND2 Logic Supply (+2.7V to +5V) RLOAD
RG1
GND4
Pull-up Resistors (10k)
NOTE: (1) See the Electrical Characteristics and Digital Input and Output section for operating limits of DGND. (2) Connect thermal pad to V-.
The following information should be considered during XTR300 circuit configuration: D Recommended bypassing: 100nF or more for D R6, R7, and C5 protect the IA. supply bypassing at each supply. D RLOAD and CLOAD represent the load resistance and D RIMON can be in the k-range or short-circuited if not load capacitance. used. Do not leave this current output D RSET defines the transfer gain. It can be split to allow unconnected--it would saturate the internal current a signal offset and, therefore, allow a 5V singlesource. The current at this IMON output is IDRV/10. supply digital-to-analog converter (DAC) to control a Therefore, VIMON = RIMON (IDRV/10). 10V or 20mA output signal. D R3 is not required but can match RSET (or RSET||ROS) The XTR300 can be used with asymmetric supply voltages; to compensate for the bias current. however, the minimum negative supply voltage should be D RIA can be short-circuited if not used. Do not leave equal to or more negative than -3V (typically -5V). This supthis current output unconnected. RGAIN is selected to ply value ensures proper control of 0V and 0mA with wire re10k to match the output of 10V with 20mA for the sistance, ground offsets, and noise added to the output. For positive output signals, the current requirement from this equal input signal. negative voltage source is less than 5mA. D RC ensures stability for unknown load conditions GND1 through GND4 must be selected to fulfill speci- and limits the current into the internal protection fied operating ranges. DGND must be in the range of diodes. C4 helps protect the device. Over-voltage (V-) DGND (V+) -7V. clamp diodes (standard 1N4002) might be necessary to protect the output.
Figure 5. Standard Circuit Configuration
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XTR300
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Built on a robust high-voltage BI-CMOS process, the XTR300 is designed to interface the 5V or 3V supply domain used for processors, signal converters, and amplifiers to the high-voltage and high-current industrial signal environment. It is specified for up to 20V supply, but can also be powered asymmetrically (for example, +24V and -5V). It is designed to allow insertion of external circuit protection elements and drive large capacitive loads.
R IMON
CC
XTR300 IMON
V+
V- Current Copy
I COPY I DRV V IN SET OPA DRV
FUNCTIONAL FEATURES
The XTR300 provides two basic functional blocks: an instrumentation amplifier (IA) and a driver that is a unique operational amplifier (OPA) for current or voltage output. This combination represents an analog output stage which can be digitally configured to provide either current or voltage output to the same terminal pin. Alternatively, it can be configured for independent measurment channels. Three open collector error signals are provided to indicate output related errors such as over-current or open-load (EFLD) or exceeding the common-mode input range at the IA inputs (EFCM). An over-temperature flag (EFOT) can be used to control output disable to protect the circuit. The monitor outputs (IMON and IAOUT) and the error flags offer optimal testability during operation and configuration. The IMON output represents the current flowing into the load in voltage output mode, while the IAOUT represents the voltage across the connectors in current output mode. Both monitor outputs can be connected together when used in current or voltage output mode because the monitor signals are multiplexed accordingly.
Input Signal
GND3
IA IN+ R SET IIA IA RG 2 GND1 IA OUT OD L L M1 M2 Digital Control Error Flags IA IN- EFCM EF LD EF OT DGND RG 1 R GAIN Load
GND2
Figure 6. Simplified Voltage Output Mode Configuration
Applications not requiring the remote sense feature can use the OPA in stand-alone operation (M1 = high). In this case, the IA is available as a separate input channel. The IA gain can be set by two resistors, RGAIN and RSET:
VOLTAGE OUTPUT MODE
In voltage output mode (M1 and M2 are connected low or left unconnected), the feedback loop through the IA provides high impedance remote sensing of the voltage at the destination, compensating the resistance of a protection circuit, switches, wiring, and connector resistance. The output of the IA is a current that is proportional to the input voltage. This current is internally routed to the OPA summing junction through a multiplexer, as shown in Figure 6. A 1:10 copy of the output current of the OPA can be monitored at the IMON pin. This output current and the known output voltage can be used to calculate the load resistance or load power. During an output short-circuit or an over-current condition the XTR300 output current is limited and EFLD (load error, active low) flag is activated.
V OUT +
R GAIN V 2RSET IN
(1)
or when adding an offset, VREF, to get bidirectional output with a single-ended input:
V OUT +
RGAIN V IN V * V REF ) IN 2 R SET R OS
(2)
The RSET resistor is also used in current output mode. Therefore, it is useful to define RSET for the current mode, then set the ratio between current and voltage span with RGAIN.
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XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
CURRENT OUTPUT MODE
The XTR300 does not require a shunt resistor for current control because it uses a precise current mirror arrangement. In current output mode (M1 connected low, or left unconnected and M2 connected high) a precise copy of 1/10th of the output is internally routed back to the summing junction of the OPA through a multiplexer, closing the control loop for the output current. The OPA driver can deliver more than 24mA within a wide output voltage range. An open-output condition or high-impedance load that prevents the flow of the required current activates the EFLD flag. While in current output mode, a current (IIA) that is proportional to the voltage at the IA input is routed to IAOUT and can be used to monitor the load voltage. A resistor converts this current into voltage. This arrangement makes level shifting easy. Alternatively, the IA can be used as an independent monitoring channel. If this output is not used, connect it to GND to maintain proper function of the monitor stage, as shown in Figure 7.
INPUT SIGNAL CONNECTION
It is possible to drive the XTR300 with a unidirectional input signal and still get a bidirectional output by adding an additional resistor, ROS, and an offset voltage signal, VREF. It can be a mid-point voltage or a signal to shift the output voltage to a desired value. This design is illustrated in Figure 8a, Figure 8b, and Figure 8c. As with a normal operational amplifier, there are several options for offset-shift circuits. The input can be connected for inverting or noninverting gain. Unlike many op amp input circuits, however, this configuration uses current feedback, which removes the voltage relationship between the noninverting input and output potential because there is no feedback resistor.
a) Noninverting Input XTR300 VIN (0 to VOFFSET) OPA VREF ROS 2k RSET 2k I-Feedback
XTR300 IMON
V+
V- Current Copy
ICOPY IDRV Input Signal V IN SET OPA DRV
b) Noninverting Input XTR300 VIN ( VMIDSCALE) OPA
R GAIN Load
IAIN+ R SET IIA IA GND1 IA OUT RIA L H GND3 OD M1 M2 Digital Control Error Flags RG 2 IAIN- GND2 EFCM EF LD EFOT DGND RG 1
VMIDSCALE RSET 1k I-Feedback
c) Inverting Input (VREF = VOFFSET)
Figure 7. Simplified Current Output Mode Configuration
The transconductance (gain) can be set by the resistor, RSET, according to the equation:
VREF VIN ( VOFFSET)
XTR300
OPA RSET 1k I-Feedback
I OUT + 10 V IN RSET
(3)
or when adding an offset VREF to get bidirectional output with a single-ended input:
I OUT + 10
16
VIN V * VREF ) IN RSET R OS
(4)
Figure 8. Circuit Options for Op Amp Output Level-Shifting
XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
The input bias current effect on the offset voltage can be reduced by connecting a resistor in series with the positive input that matches the approximate resistance at the negative input. This resistor placed close to the input pin acts as a damping element and makes the design less sensitive to RF noise. See R3 in Figure 5.
ting. When M1 is high, the internal feedback connections are opened; IAOUT and IMON are both connected to the output pins; and M2 only determines the current limit (ISC) setting.
SUMMARY OF CONFIGURATION MODES(1) EXTERNALLY-CONFIGURED MODE: OPA AND IA
It is possible to use the precision of the operational amplifier (OPA) and instrumentation amplifier (IA) independently from each other by configuring the digital control pins (M1 high). In this mode, the IA output current is routed to IAOUT and the copy of the OPA output current is routed to IMON, as shown in Figure 4. This mode allows external configuration of the analog signal routing and feedback loop. The current output IA has high input impedance, low offset voltage and drift, and very high common-mode rejection ratio. An external resistor (RIA) can be used to convert the output current of the IA (IIA) to an output voltage. The gain is given by:
M1 L L H M2 L H L MODE VOUT IOUT
Ext
DESCRIPTION Voltage Output Mode, ISC = 20mA Current Output Mode, ISC = 32mA IA and IMON on ext. pins, ISC = 20mA
H H Ext IA and IMON on ext. pins, ISC = 32mA (1) OD is a control pin independent of M1 or M2. See the Driver Output Disable section.
Table 1. Mode Configuration
M1 and M2 are pulled low internally with 1A. Terminate these two pins to avoid noise coupling. Output disable (OD) is internally pulled high with approximately 1A.
I IA +
2 RGAIN
V IN or VIA +
2RIA V RGAIN IN
(5)
DRIVING CAPACITIVE LOADS AND LOOP COMPENSATION
For normal operation, the driver OPA and the IA are connected in a closed loop for voltage output. In current output mode, the current copy closes the loop directly. In current output mode, loop compensation is not critical, even for large capacitive loads. However, in voltage output mode, the capacitive load, together with the source impedance and the impedance of the protection circuit, generates additional phase lag. The IA input might also be protected by a low-pass filter that influences phase in the closed loop. The loop compensation low-pass filter consists of CC and the parallel resistance of ROS and RSET. For loop stability with large capacitive load, the external phase shift has to be added to the OPA phase. With CC, the voltage gain of the OPA has to approach zero at the frequency where the total phase approaches 180 + 135. The best stability for large capacitive loads is provided by adding a small resistor, RC (15). See the Output Protection section. An empirical method of evaluation is using a square wave input signal and observing the settling after transients. Use small signal amplitudes only--steep signal edges cause excessive current to flow into the capacitive load and may activate the current limit, which hides or prevents oscillation. A small-signal oscillation can be hidden from large capacitive loads, but observing the IMON output on an appropriate resistor (use a similar value like RSET||ROS) would indicate stability issues. Note that noise pulses at IMON dur-
The OPA provides low drift and high voltage output swing that can be used like a common operational amplifier by connecting a feedback network around it. In this mode, the copy of the output current is available at the IMON pin (it includes the current into the feedback network). It provides an output current limit for protection, which can be set between two ranges by M2. The error flag indicates an overcurrent condition, as well as indicating driving the output into the supply rails. Alternatively, the feedback can be closed through the IMON pin to create a precise voltage-to-current converter.
DRIVER OUTPUT DISABLE
The OPA output (DRV) can be switched to a high-impedance mode by driving the OD control pin low. This input can be connected to the over-temperature flag, EFOT, and a pull-up resistor to protect the IC from over-temperature by disconnecting the load. The output disable mode can be used to sense and measure the voltage at the IA input pins without loading from the DRV output. This mode allows testing of any voltage present at the I/O connector. However, consider the bias current of the IA input pins. The digital control inputs, M1 and M2, set the four operation modes of the XTR300 as shown in Table 1. When M1 is asserted low, M2 determines voltage or current mode and the corresponding appropriate current limit (ISC) set-
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XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
ing overload (EFLD active) are normal and are caused by cycling of the current mirror. The voltage output mode includes the IA in the loop. An additional low-pass filter in the input reverses the phase and therefore increases the signal bandwidth of the loop, but also increases the delay. Again, loop stability has to be observed. Overloading the IA disconnects the closed loop and the output voltage rails.
Current Mirror IR IAIN+ A1 IR
Current Mirror
INTERNAL CURRENT SOURCES, SWITCHING NOISE, AND SETTLING TIME
The accuracy of the current output mode and the DC performance of the IA rely on dynamically-matched current mirrors. Identical current sources are rotated to average out mismatch errors. It can take several clock cycles of the internal 100kHz ocsillator (or a submultiple of that frequency) to reach full accuracy. This may dominate the settling time to the 0.1% accuracy level and can be as much as 100s in current output mode or 40s in voltage output mode. A small portion of the switching glitches appear at the DRV output, and also at the IMON and IAMON outputs. The standard circuit configuration, with RC, C4, and CC, which are required for loop compensation and output protection, also helps reduce the noise to negligible levels at the signal output. If necessary, the monitor outputs can be filtered with a shunt capacitor.
IR
RGAIN IR 2IR Current Mirror
2IR A2 IAIN- 2IR Current Mirror 2IR IIA
Figure 9. IA Block Diagram
The output current, IAOUT, of the instrumentation amplifier is limited to protect the internal circuitry. This current limit has two settings controlled by the state of M2 (see Electrical Characteristics, Short-Circuit Current specification). Note that if RSET is too small, the current output limitation of the instrumentation amplifier can disrupt the closed loop of the XTR300 in voltage output mode. With M2 = low, the nominal RGAIN of 10k allows an input voltage of 20VPP, which produces an output current of 4mAPP. When using lower resistors for RGAIN that can allow higher currents, the IA output current limitation must be taken into account.
IA STRUCTURE, VOLTAGE MONITOR
The instrumentation amplifier has high-impedance NPN transistor inputs that do not load the output signal, which is especially important in current output mode. The output signal is a controlled current that is multiplexed either to the SET pin (to close the voltage output loop) or to IAOUT (for external access). The principal circuit is shown in Figure 9. The two input buffer amplifiers reproduce the input difference voltage across RGAIN. The resulting current through this resistor is bidirectionally mirrored to the output. That mirroring results in the ideal transfer function of:
CURRENT MONITOR
In current output mode (M2 = high), the XTR300 provides high output impedance. A precision current mirror generates an exact 1/10th copy of the output current and this current is either routed to the summing junction of the OPA to close the feedback loop (in the current output mode) or to the IMON pin for output current monitoring in other operating modes.
I IA + IAOUT + 2 (IA IN) * IA IN*) R GAIN
(6)
The accuracy and drift of RGAIN defines the accuracy of the voltage to current conversion. The high accuracy and stability of the current mirrors result from a cycling chopper technique.
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XTR300
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The high accuracy and stability of this current split results from a cycling chopper technique. This design eliminates the need for a precise shunt resistor or a precise shuntvoltage measurement, which would require high commonmode rejection performance. During a saturation condition of the DRV output (the error flag is active), the monitor output (IMON) shows a current peak because the loop opens. Glitches from the current mirror chopper appear during this time in the monitor signal. This part of the signal cannot be used for measurement.
therefore removes the source of power. This connection acts like an automatic shut down, but requires an external pull-up resistor to safely override the internal current sources. The IA channel is not affected, which allows continuous observation of the voltage at the output.
DIGITAL COMMUNICATION: HART
The bandwidth and drive capability of the XTR300 are sufficient to transmit communication signals such as HART. The combination of current monitor and voltage sense with the IA circuit enables communication signal transmission from the signal output connector to the monitor pins in both current or voltage output mode. In current output mode, the signal arrives at IAOUT; in voltage output mode the communication signal modulates the DRV current and arrives at IMON. Both IAOUT and IMON can be connected together because they are internally multiplexed according to the output mode (while M1 = low). Driving a communication signal through the output connector back into the system or sensor, regardless of the output mode, enables easy configuration, calibration, diagnosis, and universal communication.
ERROR FLAGS
The XTR300 is designed for testability of its proper function and allows observation of the conditions at the load connection without disrupting service. If the output signal is not in accordance to the transfer function, an error flag is activated (limited by the dynamic response capabilities). These error flags are in addition to the monitor outputs, IMON and IAOUT, which allow the momentary output current (in voltage mode) or output voltage (in current mode) to be read back. This combination of error flag and monitor signal allows easy observation of the XTR300 for function and working condition, providing the basis for not only remote control, but also for remote diagnosis. All error flags of the XTR300 have open collector outputs with a weak pull-up of approximately 1A to an internal 5V. External pull-up resistors to the logic voltage are required when driving 3V or 5V logic. The output sink current should not exceed 5mA. This is just enough to directly drive optical-couplers, but a current-limiting resistor is required. There are three error flags:
DIGITAL I/O AND GROUND CONSIDERATIONS
The XTR300 offers voltage output mode, current output mode, external configuration, and instrumentation mode (voltage input). In addition, the internal feedback mode can be disconnected and external loop connections can be made. These modes are controlled by M1 and M2 (see the function table). The OD input pin controls enable or disable of the output stage (OD is active low). The digital I/O is referenced to DGND and signals on this pin should remain within 5V of the DGND potential. This DGND pin carries the output low-current (sink current) of the logic outputs. DGND can be connected to a potential within the supply voltage but needs to be 8V below the positive supply. Proper connection avoids current from the digital outputs flowing into the analog ground. It is important to note that DGND has normally reversebiased diodes connected to the supply. Therefore, high and destructive currents could flow if DGND is driven beyond the supply rails by more than a diode forward voltage. Avoid this condition during power-on and power-off!
D
D
D
IA Common-Mode Over-Range (EFCM)--goes low as soon as the inputs of the IA reach the limits of the linear operation for the input voltage. This flag shows noise from the saturated current mirrors which can be filtered with a capacitor to GND. Load Error (EFLD)--indicates fault conditions driving voltage or current into the load. In voltage output mode it monitors the voltage limits of the output swing and the current limit condition caused from short or low load resistance. In current output mode it indicates a saturation into the supply rails from a high load resistance or open load. Over-Temperature Flag (EFOT)--is a digital output that goes low if the chip temperature reaches a temperature of +140C and resets as soon as it cools down to +125C. It does not automatically shut down the output; it allows the user system to take action on the situation. If desired, this output can be connected to output disable (OD) which disables the output and
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XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
OUTPUT PROTECTION
The XTR300 is intended to operate in a harsh industrial environment. Therefore, a robust semiconductor process was chosen for this design. However, some external protection is still required. The instrumentation amplifier inputs can be protected by external resistors that limit current into the protection cell behind the IC-pins, as shown in Figure 10. This cell conducts to the power-supply connection through a diode as soon as the input voltage exceeds the supply voltage. The circuit configuration example shows how to arrange these two external resistors. The bias current is best cancelled if both resistors are equal. The additional capacitor reduces RF noise in the input signal to the IA.
RC is also part of the recommended loop compensation. C4 helps protect the output against RFI and high-voltage spikes.
CC 47nF V+
XTR300 DRV
RC 15
D 1N4002
OPA
I/V OUT D 1N4002 C4 100nF
V-
Figure 11. Example for DRV Output Protection
POWER ON/OFF GLITCH
IAIN+ RG1 RG2 IAIN+ RGAIN C5 10nF R6 2.2k VSENSE+ R7 2.2k VSENSE-
IA
When power is turned on or off, most analog amplifiers generate some glitching of the output because of internal circuit thresholds and capacitive charges. Characteristics of the supply voltage, as well as its rise and fall time, also directly influence output glitches. Load resistance and capacitive load affect the amplitude as well. The output disable control (OD) allows good control over the output during power-on, power-off, and system down time by providing a high impedance to the output. Figure 12a, Figure 12b, and Figure 12c show the output voltage with the output disabled during power on and off--no glitch can be see on the output signal. Holding OD low also prevents glitches in current output mode. Figure 12c indicates no glitches when transitioning from disable to enable. All measurements are made with a load resistance of 1k and tested in the circuit configuration of Figure 5. OD has an internal pull-up of approximately 1A; therefore, a 100k resistor provides safe pull-down during power on--make sure the logic controlling the OD pin does not glitch.
Figure 10. Current Limiting Resistors
The load connection to the DRV output must be low impedance; therefore, external protection diodes may be necessary to handle excessive currents, as shown in Figure 11. The internal protection diodes start to conduct earlier than a normal external PN-type diode because they are affected by the higher die temperature. Therefore, either Schottky diodes are required, or an additional resistor (RC) can be placed in series with the input. An example of this protection is shown in Figure 11. Assuming the standard diodes limit the voltage to 1.4V and the internal diodes clamp at 0.7V, this resistor can limit the current into the internal protection diodes to 50mA:
(1.4V * 0.7V) 15W + 47mA
(7)
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XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
Power-Supply Voltage 5.0V/div
Power-Supply Voltage 5.0V/div
Output 0.5V/div
Output 0.5V/div
Time (10ms/div) a) Power-on in voltage or current output mode. CH 1 shows supply voltage; CH 2 output voltage across a 1k load.
Time (10ms/div) b) Power-off in voltage or current output mode. CH 1 shows supply voltage; CH 2 output voltage across a 1k load.
Output 0.5V/div
OD 2.0V/div
Time (10ms/div) c) CH 2: Output signal during toggle of OD: CH 1 voltage or current output mode across a 1k load.
Figure 12. Output Signal with Output Disabled During Power On/Off
LAYOUT CONSIDERATIONS
Supply bypass capacitors should be close to the package and connected with low-impedance conductors. Avoid noise coupled into RGAIN, and observe wiring resistance. For thermal management, see the Heat Sinking section. Layout for the XTR300 is not critical; however, its internal current chopping works best with good (low dynamic impedance) supply decoupling. Therefore, avoid throughhole contacts in the connection to the bypass capacitors or use multiple through-hole contacts. Switching noise from chopper-type power supplies should be filtered enough to reduce influence on the circuit. Small resistors (2, for example) or damping inductors in series with the supply connection (between the DC/DC converter and the XTR circuit) act as a decoupling filter together with the bypass capacitor, as shown in Figure 13.
V+
V-
L1 10H CB1 100nF
L2 10H
CB2 100nF CB3 1F CB4 1F
V+ XTR300
V-
Figure 13. Suggested Supply Decoupling for Noisy Chopper-Type Supplies
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XTR300
www.ti.com SBOS336B - JUNE 2005 - REVISED MARCH 2006
Resistors connected close to the input pins help dampen environmental noise coupled into conductor traces. Therefore, place the OPA input- and IA input-related resistors close to the package. Also, avoid additional wire resistance in series to RSET, ROS, and RGAIN (observe the reliability of the through-hole contacts), because this could produce gain and offset error as well as drift; 1 is already 0.1% of the 1k resistor. The exposed lead-frame die pad on the bottom of the package must be connected to V-, pin 11 (see the QFN Package section for more details).
The QFN package was specifically designed to provide excellent power dissipation, but board layout greatly influences the heat dissipation of the package. Refer to the QFN Package section for further details. The XTR300 has a junction-to-ambient thermal resistance (qJA) value of 38C/W when soldered to a 2-oz copper plane. This value can be further decreased by the addition of forced air. See Table 2 for the junction-to-ambient thermal resistance of the QFN-20 package. Junction temperature should be kept below +125C for reliable operation. The junction temperature can be calculated by: TJ = TA + PD * qJA where qJA = qJC + qCA TJ = Junction Temperature (C) TA = Ambient Temperature (C) PD = Power Dissipated (W) qJA = Junction-to-Ambient Thermal Resistance qJC = Junction-to-Case Thermal Resistance qCA = Case-to-Air Thermal Resistance
QFN PACKAGE
The XTR300 is available in a QFN package. This leadless, near chip-scale package maximizes board space and enhances thermal and electrical characteristics through an exposed pad. QFN packages are physically small, have a smaller routing area, and improved thermal performance. For optimal heat performance, the exposed power pad must be connected to an adequate heat slug with at least six thermal vias to a copper area. See the example land pattern RGW (S-PQFP-N20), available for download at www.ti.com or at the end of this datasheet. The QFN package can be easily mounted using standard printed circuit board (PCB) assembly techniques. See Application Note, QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages (SCBA017), available for download at www.ti.com, for more information. The exposed leadframe die pad on the bottom of the package must be connected to the V- pin, and proper heat sinking has to be provided.
HEATSINKING METHOD The part is soldered to a 2-oz copper pad under the exposed pad. Soldered to copper pad with forced airflow (150lfm). Soldered to copper pad with forced airflow (250lfm). Soldered to copper pad with forced airflow (500lfm).
qJA 38 36 35 34
Table 2. Junction-to-Ambient Thermal Resistance with Various Heatsinking Efforts
To appropriately determine the required heatsink area, required power dissipation should be calculated and the relationship between power dissipation and thermal resistance should be considered to minimize overheat conditions and allow for reliable long-term operation. The efficiency of the heat sinking can be tested using the EFOT output signal. This output goes low at nominally +140C junction temperature (assume 6% tolerance). With full-power dissipation--for example, maximum current into a 0 load--the ambient temperature can be slowly raised until the OT flag goes low; at this point, the usable operation condition is determined. The recommended landing pattern is shown in document RGW (S-PQFP-N20). The nine (not less than six) throughhole contacts of the inner heat sink solder pad connect to a copper plane in any one layer. It must be large enough to efficiently distribute the heat into the PCB. This pad has to be electrically connected to the V- pin to provide the required substrate connection.
HEAT SINKING
Power dissipation depends on power supply, signal, and load conditions. It is dominated by the power dissipation of the output transistors of the OPA. For DC signals, power dissipation is equal to the product of output current, IOUT and the output voltage across the conducting output transistor (VS - VOUT). It is important to note that the temperature protection will not shut the part down in over-temperature conditions, unless the EFOT pin is connected to the output enable pin OD; see the section on Driver Output Disable. The power that can be safely dissipated by the package is related to the ambient temperature and the heatsink design.
22
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2006
PACKAGING INFORMATION
Orderable Device XTR300AIRGWR XTR300AIRGWRG4 XTR300AIRGWT XTR300AIRGWTG4
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE
Package Type QFN QFN QFN QFN
Package Drawing RGW RGW RGW RGW
Pins Package Eco Plan (2) Qty 20 20 20 20 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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