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Spartan-IIE 1.8V FPGA Automotive IQ Product Family: Introduction and Ordering
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DS106-1 (v1.6) September 24, 2003
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Product Specification - Unlimited in-system reprogrammability - Very low cost System level features - SelectRAM+TM hierarchical memory: * 16 bits/LUT distributed RAM * Configurable 4K-bit true dual-port block RAM * Fast interfaces to external RAM - Low-power segmented routing architecture - Dedicated carry logic for high-speed arithmetic - Efficient multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with enable, set, reset - Four dedicated DLLs for advanced clock control * Eliminate clock distribution delay * Multiply, divide, or phase shift - Four primary low-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic Versatile I/O and packaging - Low cost packages available in all densities - Family footprint compatibility in common packages - 19 high-performance interface standards * LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL * LVDS and LVPECL differential I/O - Up to 120 differential I/O pairs that can be input, output, or bidirectional Fully supported by powerful Xilinx ISE development system - Fully automatic mapping, placement, and routing - Integrated with design entry and verification tools - Extensive IP library including DSP functions and soft
Introduction
The SpartanTM-IIE 1.8V Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The seven-member family offers densities ranging from 50,000 to 600,000 system gates, as shown in Table 1. System performance is supported beyond 200 MHz. Spartan-IIE devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined architecture based on the proven VirtexTM-E platform. Features include block RAM (to 288K bits), distributed RAM (to 221,184 bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loops). Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The Spartan-IIE family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs). *
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Features
* * Guaranteed to meet full electrical specifications over TJ = -40C to +125C Second generation ASIC replacement technology - Densities as high as 15,552 logic cells with up to 600,000 system gates - Streamlined features based on Virtex-E architecture *
Table 1: Spartan-IIE FPGA Family Members Logic Cells 1,728 2,700 3,888 5,292 6,912 10,800 15,552 Typical System Gate Range (Logic and RAM) 23,000 - 50,000 37,000 - 100,000 52,000 - 150,000 71,000 - 200,000 93,000 - 300,000 145,000 - 400,000 210,000 - 600,000 CLB Array (R x C) 16 x 24 20 x 30 24 x 36 28 x 42 32 x 48 40 x 60 48 x 72 Total CLBs 384 600 864 1,176 1,536 2,400 3,456 Maximum Available User I/O(1) 182 182 182 182 329 329 329 Maximum Differential I/O Pairs 83 86 114 120 120 120 120 Distributed RAM Bits 24,576 38,400 55,296 75,264 98,304 153,600 221,184 Block RAM Bits 32K 40K 48K 56K 64K 160K 288K
Device XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E
Notes: 1. User I/O counts include the four global clock/user input pins. See details in Table 3, page 5
(c) 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS106-1 (v1.6) September 24, 2003 Product Specification
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Spartan-IIE 1.8V FPGA Automotive IQ Product Family: Introduction and Ordering Infor9/20/2003ation
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General Overview
The Spartan-IIE family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. The XC2S400E has four columns and the XC2S600E has six columns of block RAM. These functional elements are interconnected by a powerful hierarchy of versatile routing channels (see Figure 1). Spartan-IIE FPGAs are customized by loading configuration data into internal static memory cells. Unlimited reprogramming cycles are possible with this approach. Stored values in these cells determine logic functions and interconnections implemented in the FPGA. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes. Spartan-IIE FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds benefits. Spartan-IIE FPGAs are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. Spartan-IIE FPGAs achieve high-performance, low-cost operation through advanced architecture and semiconductor technology. Spartan-IIE devices provide system clock rates beyond
200 MHz. Spartan-IIE FPGAs offer the most cost-effective solution while maintaining leading edge performance. In addition to the conventional benefits of high-volume programmable logic solutions, Spartan-IIE FPGAs also offer on-chip synchronous single-port and dual-port RAM (block and distributed form), DLL clock drivers, programmable set and reset on all flip-flops, fast carry logic, and many other features.
Spartan-IIE Family Compared to Spartan-II Family
* * * * * Higher density and more I/O Higher performance Unique pinouts in cost-effective packages Differential signaling - LVDS, Bus LVDS, LVPECL VCCINT = 1.8V - Lower power - 5V tolerance with external resistor - 3V tolerance directly LVTTL and LVCMOS2 input buffers powered by VCCO instead of VCCINT Unique larger bitstream
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DLL
DLL
BLOCK RAM
BLOCK RAM
DLL
I/O LOGIC
DS077_01_052102
Figure 1: Basic Spartan-IIE Family FPGA Block Diagram
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BLOCK RAM DLL
BLOCK RAM
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Spartan-IIE 1.8V FPGA Automotive IQ Product Family: Introduction and Ordering Infor9/20/2003ation
DC Specifications
Absolute Maximum Ratings (1)
Symbol VCCINT VCCO VREF VIN VTS TSTG TJ Description Supply voltage relative to GND Supply voltage relative to GND Input reference voltage Input voltage relative to GND (2,3) Voltage applied to 3-state output (3) Storage temperature (ambient) Junction temperature Min -0.5 -0.5 -0.5 -0.5 -0.5 -65 Max 2.0 4.0 4.0 4.05 4.0 +150 +135 Units V V V V V C C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day). 3. Maximum DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and undershoot must be limited to -0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to -2.0V or overshoot to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA. 4. For soldering guidelines, see the Packaging Information on the Xilinx Web site.
Recommended Operating Conditions
Symbol TJ VCCINT VCCO TIN Description Junction temperature Supply voltage relative to GND (1) Supply voltage relative to GND (2) Input signal transition time (3) Min -40 1.8 - 5% 1.2 Max 125 1.8 + 5% 3.6 250 Units C V V ns
Notes: 1. Functional operation is guaranteed down to a minimum VCCINT of 1.62V (Nominal VCCINT -10%). For every 50 mV reduction in VCCINT below 1.71V (nominal VCCINT -5%), all delay parameters increase by 3%. 2. Minimum and maximum values for VCCO vary according to the I/O standard selected. 3. Input and output measurement threshold is ~50% of VCCO.
DC Characteristics Over Operating Conditions
Symbol Description XC2S50E XC2S100E XC2S150E ICCINTQ Quiescent V CCINT supply current(1) XC2S200E XC2S300E XC2S400E XC2S600E
Notes: 1. With no output current loads, no active pull-up resistors, and all I/O pins 3-stated and floating.
Min -
Max 200 350 450 550 650 750 850
Units mA mA mA mA mA mA mA
DS106-1 (v1.6) September 24, 2003 Product Specification
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Spartan-IIE 1.8V FPGA Automotive IQ Product Family: Introduction and Ordering Infor9/20/2003ation
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Spartan-IIE Product Availability
Table 2 shows the package and speed grades available for Spartan-IIE family devices. Table 3 shows the maximum user I/Os Table 2: Spartan-IIE Package and Speed Grade Availability Pins Type Device XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Code -6 -6 -6 -6 -6 -6 -6 144 Plastic TQFP TQ144 Q Q 208 Plastic PQFP PQ208 Q Q Q Q Q 256 Fine Pitch BGA FT256 Q Q Q Q 456 Fine Pitch BGA FG456 Q Q Q available on the device and the number of user I/Os available for each device/package combination.
Notes: 1. Q = Automotive IQ, TJ = -40C to +125C
Table 3: Spartan-IIE User I/O Chart Device XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Maximum User I/O 182 182 182 182 329 329 329 Available User I/O According to Package Type TQ144 102 102 PQ208 146 146 146 146 146 FT256 182 182 182 182 FG456 329 329 329
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DS106-1 (v1.6) September 24, 2003 Product Specification
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Spartan-IIE 1.8V FPGA Automotive IQ Product Family: Introduction and Ordering Infor9/20/2003ation
Ordering Information
Example:
Device Type Speed Grade
XC2S50E -6 PQ 208 Q
Temperature Range Number of Pins Package Type
Device Ordering Options
Device XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Speed Grade -6 Standard Performance Package Type / Number of Pins TQ144 PQ208 FT256 FG456 144-pin Plastic Thin QFP 208-pin Plastic QFP 256-ball Fine Pitch BGA 456-ball Fine Pitch BGA Temperature Range (TJ ) Q = Automotive IQ -40C to +125C
Revision History
Version No. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 Date 07/17/02 11/18/02 11/26/02 06/04/03 06/16/03 07/16/03 09/24/03 Initial Xilinx release. Added XC2S400-E and XC2S600-E devices. Added FG676 to package list. Updated Max User I/O and Differential I/O Pairs in Table 1 and Max User I/O in Table 3. Updated notes for Recommended Operating Conditions. Changed five-member family to seven-member family in first paragraph. Updated features list. Added DC Characteristics Over Operating Conditions table. Deleted "FG676" from Table 2, Table 3, and the Device Ordering Options section. Updated features list, Table 1, DC Characteristics Over Operating Conditions table, and Table 3. Updated title to read "Product Specification" (removed "Advance") Description
DS106-1 (v1.6) September 24, 2003 Product Specification
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