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| Preliminary W49S201 128K x 16 CMOS FLASH MEMORY WITH SYNCHRONOUS BURST READ GENERAL DESCRIPTION The W49S201 is a 2-megabit, 5-volt only CMOS flash memory organized as 128K x 16 bits. The W49S201 supports both asynchronous & high performance synchronous burst read modes. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49S201 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES * Single 5-volt operations: - 5-volt Read - 5-volt Erase - 5-volt Program * Sector configuration - One 8K words boot block with lockout protection - Two 8K words parameter blocks - One 104K words (208K bytes) Main Memory Array Blocks * Fast Program operation: - Word-by-Word programming: 50 S (max.) * Low power consumption - Active current: 35 mA (typ.) - Standby current: 20 A (typ.) * * * * * * * * * Fast Erase operation: 100 mS (typ.) Fast Synchronous Burst Read access time: 15/17 nS (typ.) High performance synchronous burst read mode up to 50 MHz Clock Frequency Support Linear Burst Mode Read with WrapAround Feature. No Burst Length Limitation. Fast Asynchronous Random Read access time: 55/70 nS Endurance: 10K/100K cycles (Typical.) Twenty-year data retention Hardware data protection * * * * * * Automatic program and erase timing with internal VPP generation End of program or erase detection - Toggle bit - Data polling Latched address and data TTL compatible I/O JEDEC standard word-wide pinouts Packaged in 48-pin TSOP -1- Publication Release Date: June 1999 Revision A1 Preliminary W49S201 PIN CONFIGURATIONS BLOCK DIAGRAM VDD VSS CE/OE/WE CONTROL ADV/CLK/MODE RESET 1FFFF MAIN MEMORY 104K WORDS 06000 05FFF PARAMETER BLOCK2 8K WORDS 04000 03FFF PARAMETER BLOCK1 8K WORDS 02000 BOOT BLOCK 01FFF 8K WORDS 00000 DQ0 OUTPUT BUFFER . . DQ15 A0 . A15 A14 A13 A12 A11 A10 A9 A8 NC CLK WE RESET NC MODE ADV NC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 DECODER 48-pin TSOP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE GND CE A0 . A16 PIN DESCRIPTION SYMBOL RESET A0-A16 DQ0-DQ15 CE OE WE ADV CLK MODE VDD GND NC Reset Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Address Valid Clock Synch/Asynch Mode Select Power Supply Ground No Connection PIN NAME -2- Preliminary W49S201 FUNCTIONAL DESCRIPTION Synchronous Burst & Asynchronous Read Mode Features The Winbond's W49S201 Flash device requires 3 additional control pins for synchronous burst read operations: Synchronous/Asynchronous Read Mode Select ( MODE ), Address Valid ( ADV ), and Clock (CLK). This synchronous read mode feature allows W49S201 to be interfaced easily to a wide range of DSP, microprocessors, micro-controllers for higher performance read operations. All these 3 pins are only activated internally when chip is selected (CE = VIL). The MODE input pin is used to select either synchronous or asynchronous read mode for the memory read operations. If MODE is held low, the synchronous burst read mode is selected for the read operation, and if MODE is held high then asynchronous read mode is selected for all read operations (the ADV and CLK are ignored by the Flash internally). The ADV input pin is used when the chip is selected in the synchronous read mode (CE = VIL and MODE = VIL) to load the initial random address into the Flash at the rising edge of the clock when ADV = VIL, and to increment the internal address counter at the rising edge of the clock when ADV = VIH. The CLK input pin can be tied to the system clock to provide the fundamental timing and array synchronous burst read operating frequency. Both ADV and CLK inputs are only enabled when chip is selected to operate in the synchronous burst read mode (CE = VIL and MODE = VIL). The MODE input pin is internally pulled high for applications which does not require the synchronous burst read operations, hence allowing these additional 3 pins to be considered as the No Connect (NC) pins. However, Winbond recommends that these 3 pins be driven at known logic level externally if possible. The states of these 3 additional pins are ignored during all write operations. Asynchronous Random Read Mode The asynchronous read operation of the W49S201 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Synchronous Burst Read Mode Beside being asynchronously controlled by CE and OE pins similarly as in the asynchronous read operations, the selected W49S201 Flash device when used in synchronous burst read operation mode ( MODE = VIL) requires the host to provide the initial random burst address by driving the ADV pin low at the rising edge of the clock (CLK) to latch the initial burst random address into the Flash device. Initial output data (at DQ pins) become available 2 clock cycles (or 3 clock cycles depending on starting address, refer to the timing waveforms for further details). By driving the ADV pin high at the rising edge of the clock enables the W49S201 device to read data from the next binary incremental address (linear burst mode). Sequential output data becomes available TKQV (15/17) nS of burst access time after the rising edge of the clock (always 2 CLK periods after the address increment started, i.e., ADV pin went high). There is no burst length limitation for the W49S201 device architecture, hence allowing the host to sequentially read out the entire memory Publication Release Date:June 1999 Revision A1 -3- Preliminary W49S201 data (128K words) with just one burst read operation. The W49S201 also supports full memory array linear wrap-around mode. The W49S201Q-15/17 can be used to operate at a system clock frequency as high as 50/40 MHz with only 3 initial wait-states (3-1-1-1) required for the initial random access depending on the host performance and capability on the starting & ending burst address selection. Refer to the timing waveforms for further details. Reset Operation The RESET input pin can be used in some application. When RESET pin is at high state, the device is in normal operation mode. When RESET pin is driven low for at least a period of TRP, it will halts the device and all outputs are at high impedance state. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to assure data integrity. As the high state reasserted to the RESET pin, the device will return to read or standby mode, it depends on the control signals. The system can read data TRH after the RESET pin returns to VIH. The other function for RESET pin is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be reprogrammed even though the boot block lockout function is enabled. Boot Block Operation There is one 8K-word boot block in this device, which can be used to store boot code. It is located in the first 8K words of the memory with the address range from 0000(hex) to 1FFF(hex). See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function will be disable. There is one condition that the lockout feature can be overrides. Just apply 12V to RESET pin, the lockout feature will temporary be inactivated and the block can be erased/programmed. Once the RESET pin returns to TTL level, the lockout feature will be activated again. In order to detect whether the boot block feature is set on the 8K-words block, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the output data in DQ0 is "0", the lockout feature is inactivated and the block can be erased or programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. Chip Erase Operation The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. The entire memory array will be erased to FF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the chip erase function will only erase the main memory block and the 2 parameter blocks, data in the boot block remains unchanged. The device will automatically return to normal read mode -4- Preliminary W49S201 after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Sector Erase Operation The three sectors, main memory and two parameters blocks, can be erased individually by initiating a six-word command sequence. Sector address is latched on the falling WE edge of the sixth cycle while the 30(hex) data input command is latched at the rising edge of WE. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. When the boot block lockout feature is inactivated, the boot block and the main memory block will be erased together. Once the boot block is locked, only the main memory block will be erased by the execution of sector erase operation. Program Operation The W49S201 is programmed on a word-by-word basis. Program operation can only change logical data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot block from "0" to "1" is needed before programming. The program operation is initiated by a 4-word command cycle (see Command Codes for Word Programming). The device will internally enter the program operation immediately after the wordprogram command is entered. The internal program timer will automatically time-out (50 S max. TBP) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. Hardware Data Protection The integrity of the data stored in the W49S201 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V typical. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. Data Polling (DQ7)- Write Status Detection The W49S201 includes a data polling feature to indicate the end of a program or erase cycle. When the W49S201 is in the internal program or erase cycle, any attempt to read DQ7 of the last word loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed. Note that is for asynchronous read mode only ( MODE = VIH). -5- Publication Release Date: June 1999 Revision A1 Preliminary W49S201 Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W49S201 provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. Note that is for asynchronous read mode only ( MODE = VIH). Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code, 00DA(hex). A read from address 0001(hex) outputs the device code, 0FAE(hex) if MODE = VIL, or 00AE(hex) if MODE = VIH. The product ID operation can be terminated by a three-word command sequence or an alternative one-word command sequence (see Command Definition table). In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts. Absolute Maximum Ratings PARAMETER Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential except A9 Transient Voltage (<20 nS ) on Any Pin to Ground Potential Voltage on A9 Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V C C V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. The above ratings are for maximum stress ratings only, functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this datasheet is not implied. TABLE OF OPERATING MODES Operating Mode Selection (VHH = 12V 0.5V) MODE Latch Burst Address Burst Address Increment Read CE VIL VIL OE X VIL WE VIH VIH RESET MODE ADV PINS CLK ADDRESS AIN X DQ. High Z/DOUT DOUT VIH VIH VIL VIL VIL VIH -6- Preliminary W49S201 Operating Mode Selection, continued MODE Read (Asynch.) Erase/Program Standby Erase/Program Inhibit Output Disable Product ID CE VIL VIL VIH X X X VIL OE VIL VIH X VIL X VIH VIL WE VIH VIL X X VIH X VIH RESET MODE ADV PINS CLK X X X X X X X ADDRESS AIN AIN X X X X A0 = VIL; A1-A15 = VIL; A9 = VHH A0 = VIH; A1-A15 = VIL; A9 = VHH A0 = VIH; A1-A15 = VIL; A9 = VHH X DQ. Dout Din High Z High Z/DOUT High Z/DOUT High Z Manufacturer Code 00DA (Hex) Device Code 0FAE (Hex) (Synch. Mode) Device Code 00AE (Hex) (Asynch. Mode) High Z VIH VIH VIH VIH VIH VIH VIH VIH X X X X X X X X X X X X X VIL VIL VIH VIH VIL X X VIL VIL VIH VIH VIH X X Reset X X X VIL X X X TABLE OF COMMAND DEFINITION COMMAND DESCRIPTION NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read Chip Erase Main Memory Erase Word Program Boot Block Lockout Product ID Entry Product ID Exit (1) Product ID Exit Notes: (1) 1 6 6 4 6 3 3 1 AIN DOUT 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 5555 80 5555 80 5555 A0 5555 80 5555 90 5555 F0 5555 AA 5555 AA AIN DIN 2AAA 55 5555 40 5555 AA 2AAA 55 2AAA 55 5555 10 SA 30 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA XXXX F0 1. Address Format: A14-A0 (Hex); Data Format: DQ15-DQ8 (Don't Care); DQ7-DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. SA: Sector Address SA = 03XXXh for Parameter Block1 SA = 05XXXh for Parameter Block2 SA = 1FXXXh - for Main Memory Block when Boot Block lockout feature is activated - for both Boot Block and Main Memory Block when Boot Block lockout feature is inactivated -7- Publication Release Date: June 1999 Revision A1 Preliminary W49S201 Command Codes for Word Program WORD SEQUENCE 0 Write 1 Write 2 Write 3 Write ADDRESS 5555H 2AAAH 5555H Programmed-address Pause TBP DATA AAH 55H A0H Programmed-data Word Program Flow Chart Word Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmedaddress Pause T BP Exit Notes for software program code: Data Format: DQ15-DQ8: Don't Care; DQ7-DQ0(Hex) Address Format: A14-A0 (Hex) -8- Preliminary W49S201 Command Codes for Chip Erase BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause TEC DATA AAH 55H 80H AAH 55H 10H Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause TEC Exit Notes for chip erase: Data Format: DQ15-DQ8: Don't Care; DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) -9- Publication Release Date: June 1999 Revision A1 Preliminary W49S201 Command Codes for Sector Erase BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH SA* Pause TEC DATA AAH 55H 80H AAH 55H 30H Sector Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address SA* Pause T EC Exit Notes for chip erase: Data Format: DQ15-DQ8: Don't Care; DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) SA = 03XXX for parameter block1 SA = 05XXX for parameter block2 SA = 1FXXX - for Main Memory Block when Boot Block lockout feature is activated - for both Boot Block and Main Memory Block when Boot Block lockout feature is inactivated - 10 - Preliminary W49S201 Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE ALTERNATE PRODUCT (6) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 1 Write 2 Write 3 Write 5555 2AAA 5555 Pause 10 S DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT (7) ADDRESS 5555H 2AAAH 5555H Pause 10 S DATA AAH 55H F0H Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit(7) Load data AA to address 5555 (2) Load data 55 to address 2AAA Read address = 0000 data = 00DA Load data 55 to address 2AAA Load data 90 to address 5555 (2) Read address = 0001 data = 0FAE if MODE = Lo data = 00AE if MODE = Hi Load data F0 to address 5555 Pause 10 S Read address = 0002 data in DQ0 =1/0 (4) Pause 10 S (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ15-DQ8 (Don't Care), DQ7-DQ0 (Hex); Address Format: A14-A0 (Hex) (2) A1-A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0 = 1, the boot block programming lockout feature is activated; if the output data in DQ0 = 0, the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. - 11 - Publication Release Date: June 1999 Revision A1 Preliminary W49S201 Command Codes for Boot Block Lockout Enable BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write BOOT BLOCK LOCKOUT FEATURE SET ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause TEC DATA AAH 55H 80H AAH 55H 40H Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause TEC Exit Notes for boot block lockout enable: Data Format: DQ15-DQ8 Don't Care), DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) - 12 - Preliminary W49S201 DC CHARACTERISTICS DC Operating Characteristics (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER SYM. TEST CONDITIONS LIMITS MIN. TYP. MAX. 75 UNIT VDD Asynch. Read Current ICCR1 CE = OE = VIL, WE = VIH, MODE = VIH, all DQs open, CLK & ADV = VIL/VIH, Address Inputs = VIL/VIH at f = 5 MHz ICCR2 CE = OE = VIL, WE = VIH, MODE = VIL, all DQs open, ADV = VIL/VIH, Address Inputs = VIL/VIH, CLK at f = FCLK (max.) ICCW Erase or Program Operation in Progress, all DQs open. ISB1 CE = VIH, all DQs open Other inputs = VIL/VIH ISB2 CE = VDD 0.3V, all DQs open Other Inputs = GND 0.3V or VDD 0.3V ILI ILO VIL VIH VOL VOH IOL = 2.1 mA IOH = -0.4 mA VIN = GND to VDD VOUT = GND to VDD - - 35 mA VDD Synch Burst Read Current - - 175 mA VDD Erase or Program Current Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage - 2 50 3 mA mA - 20 200 A A A V V V V -0.3 2.0 2.4 - 10 10 0.8 VDD +0.5 0.45 - Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS - 13 - Publication Release Date: June 1999 Revision A1 Preliminary W49S201 CAPACITANCE (VDD = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER I/O Pin Capacitance Input Capacitance SYMBOL CI/O CIN CONDITIONS VI/O = 0V VIN = 0V MAX. 12 6 UNIT pf pf AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3.0V < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF CONDITIONS AC Test Load and Waveform +5V 1.8K D OUT 30 pF (Including Jig and Scope) 1.3K Input 3V 1.5V 0V Test Point Output 1.5V Test Point - 14 - Preliminary W49S201 Asynchronous Read Cycle Timing Parameters (VCC = 5.0V 10%, VCC = 0V, TA = 0 to 70 C) PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output SYM. TRC TCE W49S201-15 MIN. 55 0 0 0 MAX. 55 55 25 20 20 - W49S201-17 MIN. 70 0 0 0 MAX. 70 70 35 25 25 - UNIT nS nS nS nS nS nS nS nS nS TAA TOE TCLZ TOLZ TCHZ TOHZ Output Hold Time TOH Note: The parameter of TCLZ, TOLZ, TCHZ, TOHZ are characterized only and is not 100% tested. Synchronous Burst Read Cycle Timing Parameters (VCC = 5.0V 10%, VCC = 0V, TA = 0 to 70 C) PARAMETER CLK Frequency CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time CE Setup Time to CLK SYM. FCLK TCYC TKH TKL TKLH TKHL TCES TAKS TAKH TADVS TADVH TMODS TMODH TKQV TKQH W49S201-15 MIN. 20 7 7 15 12 2 12 2 15 5 1 MAX. 50 2 2 15 - W49S201-17 MIN. 25 8 8 20 15 2 15 2 20 5 1 MAX. 40 3 3 17 - UNIT MHz nS nS nS nS nS nS nS nS nS nS nS nS nS nS Address Setup Time to CLK Address Hold Time From CLK ADV Setup Time to CLK ADV Hold Time From CLK MODE Setup Time to CLK MODE Hold Time From CLK CLK to Valid Output Output Hold Time From CLK Note: The parameter of TKQH is characterized only and is not 100% tested. - 15 - Publication Release Date: June 1999 Revision A1 Preliminary W49S201 AC Characteristics, continued Write Cycle Timing Parameters PARAMETER Address Setup Time Address Hold Time WE and CE Setup Time WE and CE Hold Time OE High Setup Time OE High Hold Time CE Pulse Width WE Pulse Width WE High Width SYMBOL TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBP TEC MIN. 0 50 0 0 0 0 70 70 100 50 10 - TYP. 10 0.1 MAX. 50 1 UNIT nS nS nS nS nS nS nS nS nS nS nS S S Data Setup Time Data Hold Time Word programming Time Erase Cycle Time Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. Data Polling and Toggle Bit Timing Parameters PARAMETER SYM. TOEP TCEP TOET TCET W49S201-15 MIN. OE to Data Polling Output Delay CE to Data Polling Output Delay OE to Toggle Bit Output Delay CE to Toggle Bit Output Delay MAX. 25 55 25 55 W49S201-17 MIN. MAX. 35 70 35 70 nS nS nS nS UNIT Hardware Reset Timing Parameters PARAMETER RESET Pin Low to Read or Write RESET Pulse Width RESET High Time Before Read(1) SYM. TREADY TRP TRH MIN. 500 50 MAX. 500 UNIT nS nS nS Note: 1. The parameters are characterized only and is not 100% tested. - 16 - Preliminary W49S201 TIMING WAVEFORMS Synchronous Burst Read Cycle Timing 1 (3-1-1-1 linear mode) (Starting Address is Even and Ending Address is Odd) 2n CLK TADVS ADV TMODS MODE TAKS A[16:0] 2n TKAH TADVH 2n+1 2n+2 2n+3 2k 2k 2k+1 2k+2 2k+3 TADVH Ending Burst Addr. is Odd (2n+3) TADVS Increment Address Counter Load Burst Address (Starting Address is Even 2n) Load Burst Address (Starting Address is Even 2k) TMODH TCYC 2k DQ's Valid 2 CLK periods TCES CE after loading (ADV=Low) DQ's Valid 2 CLK periods after loading (ADV=Low) TCLZ TOLZ OE TKQH DQ[15:0] High-Z TKQV 2n 2n+1 2n+2 TKQV Next DQ's Valid 2 CLK periods after Increment (ADV=Hi) TOH 2n+3 TKQV 2k 2k+1 2k+2 2k+3 DON'T CARE UNDEFINED Note: The above waveform is applicable to synchronous read mode with starting random address is always Even and ending address is always Odd address only. The ADV can be 1 CLK period pulse minimum, and the total wait states can be 3 CLK periods minimum. Initial output data DQ[15:0] become valid 2 CLK periods after the valid address loading started ( ADV = Low) & next sequential output data DQ[15:0] become valid 2 CLK periods after address increment started ( ADV = Hi). - 17 - Publication Release Date: June 1999 Revision A1 Preliminary W49S201 Synchronous Burst Read Cycle Timing 2 (4-1-1-1 linear mode) (Starting Address & Ending Address are both either Even or Odd) 2n+1 CLK TADVS ADV TMODS MODE TAKS A[16:0] TCES CE TCLZ 2n+1 2n+1 2n+2 2n+3 2k+1 2k+1 2k+1 2k+2 2k+3 TADVH Ending Addr. is Odd (2n+3) Load Burst Address (Starting Address is Odd 2n+1) TADVH TADVS Increment Address Counter Load Burst Address (Starting Address is Odd 2k+1) TMODH TKAH TCYC 2k+1 DQ's Valid 3 CLK periods after valid loading (ADV=Low) DQ's Valid 3 CLK periods after valid loading (ADV=Low) Next DQ's Valid 2 CLK periods TOLZ OE TKQH DQ[15:0] High-Z TKQV 2n+1 2n+2 TKQV 2n+3 after increment (ADV=Hi) TOH 2k+1 TKQV 2k+2 2k+3 DON'T CARE UNDEFINED Note: The above waveform is applicable to synchronous burst read mode with starting random address and ending burst address are both either Even or Odd only (shown above with Starting & Ending are Odd address). The ADV must be minimum 2 CLK period pulse, and the total wait states hence can be 4 CLK periods minimum. Initial output data DQ[15:0] become valid 3 CLK periods after the valid address loading started ( ADV = Low) & next sequential output data DQ[15:0] become valid 2 CLK periods after address increment started ( ADV = Hi). - 18 - Preliminary W49S201 Synchronous Burst Read Cycle Timing 3 (5-1-1-1 linear mode) (Starting Address & Ending Address can be Any Random Address) n CLK TADVS ADV TMODS MODE TAKS A[16:0] TCES CE TCLZ n n n n+1 n+2 n+3 k k k k k+1 k+2 k+3 TADVH TADVH TADVS Increment Address Counter Load Burst Address (n) Load Burst Address (k) TKAH TCYC k DQ's Valid 3 CLK periods after valid loading (ADV=Low) DQ's Valid 3 CLK periods after valid loading (ADV=Low) TOLZ OE TKQH DQ[15:0] High-Z TKQV DON'T CARE UNDEFINED n n+1 TKQV n+2 n+3 TKQV Next DQ's Valid 2 CLK periods after increment (ADV=Hi) k k+1 Note: The above waveform is applicable to synchronous burst read mode with any starting random address and any ending burst (can be either even or odd). The ADV must be minimum 3 CLK period pulse, and the total wait states hence can be 5 CLK periods minimum. Initial output data DQ[15:0] become valid 3 CLK periods after the valid address loading started ( ADV = Low) & next sequential output data DQ[15:0] become valid 2 CLK periods after address increment started ( ADV = Hi). Clock Input Timing Diagram TKHL TKH 3V 90% TKLH TKL CLK 0V 10% TCYC - 19 - Publication Release Date: June 1999 Revision A1 Preliminary W49S201 Asynchronous Read Cycle Timing Diagram T RC Address A16-0 TCE CE OE TOE VIH WE TOLZ T OHZ TCLZ High-Z TOH Data Valid TAA TCHZ High-Z Data Valid DQ15-0 WE Controlled Command Write Cycle Timing Diagram TAS Address A16-0 TAH CE TCS TOES TCH TOEH OE TWP TWPH WE TDS DQ15-0 Data Valid TDH - 20 - Preliminary W49S201 Timing Waveforms, continued CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A16-0 TCPH TCP CE TOES OE TOEH WE TDS DQ15-0 High Z Data Valid TDH Program Cycle Timing Diagram Word Program Cycle Address A16-0 5555 2AAA 5555 Address DQ15-0 AA 55 A0 Data-In CE OE TWP WE Word 0 T WPH TBP Word 1 Word 2 Word 3 Internal Write Start - 21 - Publication Release Date: June 1999 Revision A1 Preliminary W49S201 Timing Waveforms, continued DATA Polling Timing Diagram Address A16-0 WE TCEP CE TOEH OE TOEP DQ7 X X TBP or TEC X X TOES Toggle Bit Timing Diagram Address A16-0 WE CE TOEH OE TOES DQ6 TBP orTEC - 22 - Preliminary W49S201 Timing Waveforms, continued Boot Block Lockout Enable Timing Diagram Six-word code for Boot Block Lockout Feature Enable Address A16-0 5555 2AAA 5555 5555 2AAA 5555 DQ15-0 XXAA XX55 XX80 XXAA XX55 XX40 CE OE WE TWP TWPH SW0 SW1 SW23 SW3 SW4 SW5 TEC Chip Erase Timing Diagram Six-word code for 5V-only software chip erase Address A16-0 5555 2AAA 5555 5555 2AAA 5555 DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 CE OE TWP WE TWPH SW0 SW1 SW2 SW3 SW4 SW5 Internal Erase starts TEC - 23 - Publication Release Date: June 1999 Revision A1 Preliminary W49S201 Timing Waveforms, continued Sector Erase Timing Diagram Six-word code for 5V-only software Main Memory Erase Address A16-0 5555 2AAA 5555 5555 2AAA SA DQ15-0 CE XXAA XX55 XX80 XXAA XX55 XX30 OE WE TWP TWPH SW0 SW1 SW2 SW3 SW4 SW5 TEC Internal Erase starts SA = Sector Address Reset Timing Diagram CE OE TRH RESET TRP TREADY - 24 - Preliminary W49S201 ORDERING INFORMATION PART NO. ACCESS TIME TKQV (nS) W49S201Q-15B W49S201Q-17B W49S201Q-15C W49S201Q-17C Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. POWER SUPPLY CURRENT MAX. (mA) 75 75 75 75 STANDBY VDD CURRENT MAX. (A) 200 (CMOS) 200 (CMOS) 200 (CMOS) 200 (CMOS) PACKAGE CYCLE 15 17 15 17 48-pin TSOP (12 mm x 20 mm) 48-pin TSOP (12 mm x 20 mm) 48-pin TSOP (12 mm x 20 mm) 48-pin TSOP (12 mm x 20 mm) 10K 10K 100K 100K - 25 - Publication Release Date: June 1999 Revision A1 Preliminary W49S201 PACKAGE DIMENSIONS 48-pin TSOP (12 mm x 20 mm) 1 48 Dimension in mm Symbol Dimension in Inches MIN. NOM. MAX. e A A1 E b A2 D HD E b c e L A2 L L1 A1 A Y L1 Y MIN. NOM. MAX. 1.20 0.05 0.95 18.3 19.8 11.9 0.17 0.10 0.50 0.50 0.60 0.80 0.70 0.10 0 5 0 1.00 18.4 20.0 12.0 0.22 1.05 18.5 20.2 12.1 0.27 0.21 0.002 0.037 0.039 0.720 0.724 0.780 0.787 0.468 0.472 0.007 0.004 0.020 0.020 0.024 0.031 0.009 0.047 0.041 0.728 0.795 0.476 0.011 0.008 0.028 0.004 5 c D HD - 26 - Preliminary W49S201 VERSION HISTORY VERSION A0 A1 DATE Nov. 1998 Jun. 1999 PAGE DESCRIPTION Advance Information only, some parameters & waveforms are to be determined. Updated Product Number to W49S201, Device Codes, and some AC parameters. Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 27 - Publication Release Date: June 1999 Revision A1 |
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