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W24L11 128K x 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L11 is a normal-speed, very low-power CMOS static RAM organized as 131072 x 8 bits that operates on a wide voltage range from 3.0V to 3.6V power supply. This device is manufactured using Winbond's high performance CMOS technology.
FEATURES
* * * * *
Low power consumption: - Active: 144 mW (max.) Access time: 70 nS Single 3.3V power supply Fully static operation All inputs and outputs directly TTL compatible
* * * *
Three-state outputs Battery back-up operation capability Data retention voltage: 2V (min.) Packaged 450 mil SOP, standard type one, TSOP (8 mm x 20 mm), small type one and TSOP (8 mm x 13.4 mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
CLK GEN. A16 A14 PRECHARGE CKT.
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
VDD A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4
A12 A4 A3 A2 A7 A6 A5 A9 I/O1 : I/O8
R O W D E C O D E R
CORE CELL ARRAY 1024 ROWS 128 X 8 COLUMNS
32-pin SOP
DATA CNTRL. CLK GEN.
25 24 23 22 21 20 19 18 17
I/O CKT. COLUMN DECODER
WE CS1 CS2 OE
A15 A13 A8 A1 A0 A11A10
PIN DESCRIPTION
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
A11 A9 A8 A13 WE CS2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SYMBOL A0-A16 I/O1-I/O8 CS1, CS2 WE OE VDD VSS NC
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground No Connection
32-pin TSOP
-1-
Publication Release Date: May 2000 Revision A2
W24L11
TRUTH TABLE
CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L MODE Not Selected Not Selected Output Disable Read Write I/O1-I/O8 High Z High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 ISB, ISB1 IDD IDD IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature L/LL LE RATING -0.5 to +4.6 -0.5 to VDD +0.5 1.0 -65 to +150 0 to 70 -20 to 85 UNIT V V W C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Operating Characteristics
(VDD = 3.0V to 3.6V; VSS = 0V; TA (C) = 0 to 70 for LL, -20 to 85 for LE)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current
SYM. VIL VIH ILI ILO
TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD, CS1 = VIH (min.) or CS2 = VIL (max.) or OE = VIH (min.) or WE = VIL (max.) IOL = +2.1 mA IOH = -1.0 mA
CS1 = VIL (max.) and CS2 = VIH (min.), I/O = 0 mA, Cycle = min. Duty = 100%
MIN. -0.5 +2.0 -1 -1
MAX. +0.6 VDD +0.5 +1 +1
UNIT V V
A A
Output Low Voltage Output High Voltage Operating Power Supply Current
VOL VOH IDD
2.2 -
0.4 40
V V mA
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W24L11
Operating Characteristics, continued
PARAMETER Standby Power Supply Current
SYM. ISB
TEST CONDITIONS
MIN. -
MAX. 1
UNIT mA
ISB1
CS1 = VIH (min.) or CS2 = VIL (max.) Cycle = min. Duty = 100% LL/LE CS1 VDD -0.2V or
CS2 0.2V L
-
50 100
A
Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 3.3V
CAPACITANCE
(VDD = 3.3 V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 6 8
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC Characteristics
AC Test Conditions PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load AC Test Loads and Waveform
1 TTL OUTPUT 100 pF Including Jig and Scope OUTPUT 5 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 3.0 V 0V 5 nS
90% 90% 10% 10%
CONDITIONS 0V to 3.0V 5 nS 1.5V See the drawing below
1 TTL
5 nS
-3-
Publication Release Date: May 2000 Revision A2
W24L11
AC Characteristics, continued (VDD = 3.0V to 3.6 V; VSS = 0V; TA (C) = 0 to 70 for LL, -20 to 85 for LE)
Read Cycle
PARAMETER SYMBOL W24L11-70L/LL/LE MIN. Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change
These parameters are sampled but not 100% tested
UNIT
MAX. 70 70 35 30 30 nS nS nS nS nS nS nS nS nS
TRC TAA TACS TAOE TCLZ* TOLZ* TCHZ* TOHZ* TOH
70 10 5 10
Write Cycle
PARAMETER SYMBOL W24L11-70L/LL/LE MIN. Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write These parameters are sampled but not 100% tested
CS1, CS2, WE
UNIT
MAX. 25 25 nS nS nS nS nS nS nS nS nS nS nS
TWC TCW TAW TAS TWP TWR TDW TDH TWHZ* TOHZ* TOW
70 55 55 0 50 0 45 0 5
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W24L11
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
TRC Address TOH DOUT TAA TOH
Read Cycle 2
(Chip Select Controlled)
CS1
CS2 TACS TCLZ D OUT TCHZ
Read Cycle 3
(Output Enable Controlled)
TRC Address TAA OE TAOE TOLZ CS1 TOH
CS2
TACS DOUT TCLZ
TCHZ
TOHZ
-5-
Publication Release Date: May 2000 Revision A2
W24L11
Timing Waveforms, continued
Write Cycle 1
TWC Address TWR OE
TCW CS1
CS2 TAW WE TAS TOHZ DOUT TDW DIN TDH (1, 4) TWP
Write Cycle 2
(OE = VIL Fixed)
T WC Address TCW CS1 TWR
CS2 TAW WE TAS TWP TWHZ (1, 4) TOH (2) TOW (3)
D OUT
TDW DIN
TDH
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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W24L11
DATA RETENTION CHARACTERISTICS
(TA (C) = 0 to 70 for LL, -20 to 85 for LE)
PARAMETER VDD for Data Retention
SYM. VDR
TEST CONDITIONS CS1 VDD -0.2V or CS2 0.2V CS1 VDD -0.2V or CS2 0.2V, VDD = 3V See data retention waveform
MIN. 2.0
TYP. -
MAX. -
UNIT V
Data Retention Current
IDDDR
-
-
50
A
Chip Deselect to Data Retention Time Operation Recovery Time * Read Cycle Time
TCDR TR
0 TRC*
-
-
nS nS
DATA RETENTION WAVEFORM
VDD
0.9VDD TCDR
VDR > 2V =
0.9 VDD TR
CS1
> CS1 = VDD - 0.2V
CS2
0V < CS2 < 0.2V = =
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Publication Release Date: May 2000 Revision A2
W24L11
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 70 70 70 70 70 70 70 70 70 OPERATING VOLTAGE (V) 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V OPERATING TEMPERATURE (C) -20 to 85 -20 to 85 -20 to 85 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 STANDBY CURRENT MAX. (A) 50 50 50 50 50 50 100 100 100 PACKAGE
W24L11S-70LE W24L11T-70LE W24L11Q70LE W24L11S-70LL W24L11T-70LL W24L11Q-70LL W24L11S-70L W24L11T-70L W24L11Q-70L
Notes:
450 mil SOP Standard type one TSOP Small type one TSOP 450 mil SOP Standard type one TSOP Small type one TSOP 450 mil SOP Standard type one TSOP Small type one TSOP
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
-8-
W24L11
BONDING PAD DIAGRAM
6 6 A5 7 A4 5 A6 4 3 2 1 33 32 31 30 29 28 27 26 A9 25 A11 A7 A12 A14 A16 VDD VDD A15 CS2 WEB A13 A8
AC5405
Y
X
8 A3 9 A2 10 A1 11 A0 12 13 14 15 16 17 18 19 20 21 22 23
24 OEB
I/O0 I/O1 I/O2 VSS VSS I/O3 I/O4 I/O5 I/O6 I/O7 CS1B A10
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
X -485.31 -1200.87 -1341.05 -1480.80 -1622.21 -1767.47 -1993.03 -1990.55 -1789.57 -1556.20 -1405.83 -1169.73 -870.28 -567.65 -336.94 -112.55 224.85 497.55 772.25 1044.95 1319.65 1537.77 1773.94 1985.78 1987.47 1669.63 1451.03 1196.59 956.65 219.67 79.47 -145.06 -353.56
Y 2376.64 2376.64 2376.64 2376.64 2376.64 2376.64 2228.49 -2275.79 -2382.05 -2382.05 -2382.05 -2383.00 -2383.00 -2383.00 -2385.00 -2385.00 -2383.00 -2383.00 -2383.00 -2383.00 -2383.00 -2382.05 -2382.05 -2297.62 2221.27 2376.64 2376.64 2376.64 2376.64 2376.64 2376.64 2343.58 2343.58
Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout.
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Publication Release Date: May 2000 Revision A2
W24L11
PACKAGE DIMENSIONS
32-pin SOP Wide Body
Dimension in Inches Dimension in mm
Symbol
17
Min.
32
Nom.
Max.
0.118
Min.
0.10
Nom.
Max.
3.00
e1
E HE
L
Detail F
1 16
b
A A1 A2 b c D E e HE L LE S y
0.004 0.101 0.014 0.006 0.106 0.016 0.008 0.805 0.440 0.044 0.546 0.023 0.047 0.445 0.050 0.556 0.031 0.055 0.111 0.020 0.012 0.817 0.450 0.056 0.556 0.039 0.063 0.036 0.004 0 10
2.57 0.36 0.15
2.69 0.41 0.20 20.45
2.82 0.51 0.31 20.75 11.43 1.42 14.38 0.99 1.60 0.91 0.10
11.18 1.12 13.87 0.58 1.19
11.30 1.27 14.12 0.79 1.40
Notes:
D e1 c A2 S y e A1 LE A
0
10
1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches 5. General appearance spec should be based on final visual inspection spec.
See Detail F
Seating Plane
32-pin Standard Type One TSOP
HD
Symbol
Dimension in Inches Min. Nom. Max. 0.047 0.002 0.037 0.007
Dimension in mm Min. Nom. Max. 1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20
D c 1
A A1 A2 b
__
__ __
0.039 0.008 0.006 0.041 0.009 0.007
__
0.05 0.95 0.17 0.12
__ __
1.00 0.20 0.15
M
e E
c D E HD e L L1
0.005 0.006 0.720 0.724 0.311 0.780 0.315
0.10(0.004)
0.728 18.30 18.40 0.319 7.90 8.00
b
0.787 0.795 19.80 20.00 0.020 0.020 0.031
__
0.016
__
0.024
__
0.50 0.40 0.50 0.80
__
0.60
__
0.000 1
__
0.004 5
__
0.00 1
__
0.10 5
A A2 L L1 A1
Y Y
__
3
__
3
Controlling dimension: Millimeters
- 10 -
W24L11
Package Dimensions, continued
32-pin Small Type One TSOP
HD
Symbol
Dimension in Inches Min. Nom. Max. 0.049 0.002
Dimension in mm Min. Nom. Max. 1.25 0.15 1.00 0.20 0.15 1.05 0.27 0.16
D c
1
A A1 A2 b c D E HD e L L1
0.006 0.05 0.95
e
E
0.037 0.039 0.041
0.007 0.008 0.009 0.17 0.0056 0.0059 0.0062 0.14
b
0.461 0.465 0.469 11.70 11.80 11.90 0.311 0.315 0.319 7.90 8.00 8.10
0.520 0.528 0.536 13.20 13.40 13.60 0.020 0.012 0.020 0.028 0.027 0.000 0 3 0.004 5 0.50 0.30 0.50 0.675 0.00 0 3 0.10 5 0.70
A A
2
L L1
A1
Y
Y
Controlling dimension: Millimeters
- 11 -
Publication Release Date: May 2000 Revision A2
W24L11
VERSION HISTORY
VERSION A1 A2 DATE Oct. 1999 May 2000 PAGE 1, 2, 8, 9 Initial Issued Delete 32-pin P-DIP Package; Add LE in Operating Characteristics, Data Retention Characteristics & Ordering Info. 9 Add in Bonding Pad Diagram DESCRIPTION
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change withou t notice.
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