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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
D D D D D D D D D D D D
21:3 Data Channel Compression at up to 196 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI 21 Data Channels Plus Clock In Low-Voltage TTL Inputs and 3 Data Channels Plus Clock Out Low-Voltage Differential Signaling (LVDS) Outputs Operates From a Single 3.3-V Supply and 89 mW (Typ) Ultralow-Power 3.3-V CMOS Version of the SN75LVDS84. Power Consumption About One Third of the 'LVDS84 Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20 Mil Terminal Pitch Consumes Less Than 0.54 mW When Disabled Wide Phase-Lock Input Frequency Range: 31 MHz to 75 MHz No External Components Required for PLL Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard SSC Tracking Capability of 3% Center Spread at 50-kHz Modulation Frequency Improved Replacement for SN75LVDS84 and NSC's DS90CF363A 3-V Device
DGG PACKAGE (TOP VIEW)
D4 VCC D5 D6 GND D7 D8 VCC D9 D10 GND D11 D12 NC D13 D14 GND D15 D16 D17 VCC D18 D19 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
D3 D2 GND D1 D0 NC LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D20
NC - Not Connected
description
The SN75LVDS84A FlatLink transmitter contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A. When transmitting, data bits D0 - D20 are each loaded into registers of the 'LVDS84A upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The 'LVDS84A requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low level. The SN75LVDS84A is characterized for operation over ambient free-air temperatures of 0C to 70C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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1
SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
functional block diagram
Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD CLK Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD CLK Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD CLK Y2P Y2M Y1P Y1M
7 D0 - D6
Y0P Y0M
7 D7 - D13
7 D14 - D20
Control Logic SHTDN
PLL CLKOUTP CLKIN CLK CLKINH CLKOUTM
schematics of input and output
EQUIVALENT OF EACH INPUT VCC EQUIVALENT OF EACH OUTPUT VCC
7V
D or SHTDN
180
YnP or YnM
5V
7V
2
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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Input and output voltage ranges, VI, VO (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Electrostatic discharge: ESD machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V ESD human-body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6000 V ESD charged-device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING
DGG 1316 mW 13.1 mW/C 726 mW This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
recommended operating conditions
MIN Supply voltage, VCC High-level input voltage, VIH Low-level input voltage, VIL Differential load impedance, ZL Operating free-air temperature, TA 90 0 3 2 0.8 132 70 NOM 3.3 MAX 3.6 UNIT V V V C
timing requirements
MIN tc tw tt tsu th Input clock period Pulse duration, high-level input clock Transition time, input signal Setup time, data, D0 - D20 valid before CLKIN (See Figure 2) Hold time, data, D0 - D20 valid after CLKIN (See Figure 2) 3 1.5 13.3 0.4 tc NOM tc MAX 32.4 0.6 tc 5 UNIT ns ns ns ns ns
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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VIT |VOD| |VOD| VOC(SS) VOC(PP) IIH IIL IOS IOZ Input threshold voltage Differential steady-state output voltage magnitude Change in the steady-state differential output voltage magnitude between opposite binary states Steady-state common-mode output voltage Peak-to-peak common-mode output voltage High-level input current Low-level input current Short-circuit Short circuit output current High-impedance output current VIH = VCC VIL = 0 VO(Yn) = 0 VOD = 0 VO = 0 to VCC Disabled, All inputs at GND Enabled, RL = 100 (4 places) ( ) Gray-scale pattern (see Figure 4) Enabled, RL = 100 , (4 places) ,( ) Worst-case pattern (see Figure 5) CI Input capacitance All typical values are at VCC = 3.3 V, TA = 25C. f = 65 MHz f = 75 MHz f = 65 MHz f = 75 MHz -6 -6 15 27 30 28 31 2 RL = 100 , See Figure 3 1.125 80 RL = 100 , See Figure 3 247 TEST CONDITIONS MIN TYP 1.4 454 50 1.375 150 20 10 24 12 10 150 35 38 mA 36 39 pF MAX UNIT V mV mV V mV A A mA mA A A
ICC(AVG) ( )
Quiescent supply current (average)
4
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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER td0 td1 td2 td3 td4 td5 td6 tsk(o) Delay time, CLKOUT to serial bit position 0 Delay time, CLKOUT to serial bit position 1 Delay time, CLKOUT to serial bit position 2 Delay time, CLKOUT to serial bit position 3 Delay time, CLKOUT to serial bit position 4 Delay time, CLKOUT to serial bit position 5 Delay time, CLKOUT to serial bit position 6 Output skew, t n tc = 15.38 ns ( 0.2%), |Input clock jitter| < 50 ps, See Figure 6 1t 7c TEST CONDITIONS MIN - 0.2 TYP MAX 0.2 UNIT
* 0.2 2 t * 0.2 7c * 0.2 4 t * 0.2 7c
3t 7c
* n tc 7
tc = 15.38 ns ( 0.2%), |Input clock jitter| < 50 ps, See Figure 6 tc = 13.33 ns ~ 32.25 ns ( 0.2%), |Input clock jitter| < 50 ps, See Figure 6 tc = 15.38 + 0.308 sin (2500E3t) 0.05 ns, See Figure 7 tc = 15.38 + 0.308 sin (23E6t) 0.05 ns, See Figure 7
* 0.2 6 t * 0.2 7c
5t 7c - 0.2 2.7
) 0.2 2 t ) 0.2 7c 3 t ) 0.2 7c 4 t ) 0.2 7c 5 t ) 0.2 7c
1t 7c 6t 7c
ns
) 0.2
0.2 ns
td7
Delay time, CLKIN to CLKOUT time
ns 1 62 ps 121 4t 7c ns 1500 ps ms ns 4.5
tc(o) C cle time output clock jitter ( ) Cycle time, o tp t
tw tt ten tdis
Pulse duration, high-level output clock Transition time, differential output voltage (tr or tf) Enable time, SHTDN to phase lock (Yn valid) Disable time, SHTDN to off state (CLKOUT low) See Figure 3 See Figure 8 See Figure 9
700 1 6.5
All typical values are at VCC = 3.3 V, TA = 25C. |Input clock jitter| is the magnitude of the change in the input clock period. Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles.
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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
D0
CLKIN
CLKOUT
Previous Cycle
Current Cycle
D3 D2
Y0
D0-1
D6
D5
D4
Y1
D7-1
D13
D12
D11
D10
D9
Y2
D14-1
D20
D19
D18
D17
D16
Figure 1. Typical Load and Shift Sequences
tsu Dn th
CLKIN
NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Definition
6
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IIII IIII
II II
D1 D0 D8 D7 D15 D14
II II IIII IIII IIII
IIIIII IIIIII
III III
II II III III III
Next Cycle
D6+1
D13+1
D20+1
SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
YP
49.9 1% (2 Places)
VOD VOC CL = 10 pF Max (2 Places) NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output is similarly loaded. (a) SCHEMATIC
YM
100% VOD(H) 0V VOD(L) 20% 0% tf tr 80%
VOC(PP)
VOC(SS)
VOC(SS)
0V (b) WAVEFORMS
Figure 3. Test Load and Voltage Definitions for LVDS Outputs
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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
CLKIN D0, 6, 12 D1, 7, 13 D2, 8, 14 D3, 9, 15 D18, 19, 20 All others NOTES: A. The 16-grayscale test-pattern test device power consumption for a typical display pattern. B. VIH = 2 V and VIL = 0.8 V
Figure 4. 16-Grayscale Test-Pattern Waveforms
tc CLKIN Even Dn Odd Dn NOTES: A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. B. VIH = 2 V and VIL = 0.8 V
Figure 5. Worst-Case Test-Pattern Waveforms
8
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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
td7 CLKIN
CLKOUT
td0
Yn
td1
td2
td3 td4 td5 td6 VOD(H) CLKIN 1.4 V CLKOUT or Yn 0V VOD(L) td7 td0 - td6
Figure 6. Timing Definitions
Reference
+
+
VCO
Modulation V(t) = A sin (2 f(mod) t)
HP8665A Synthesized Signal Generator 0.1 MHz - 4200 MHz RF Output
HP8133A Pulse Generator
Device Under Test
OUTPUT Ext. Input
CLKIN
CLKOUT
Figure 7. Clock Jitter Test Setup
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II II II II II II III III
Device Under Test Tek TDS794D Digital Scope Input 9
II II II II II II II II II II
II II II II
SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
CLKIN Dn ten SHTDN
Yn
CLKIN tdis SHTDN CLKOUT
I CC - Average Supply Current - mA
29 VCC = 3.6 V 27 25 VCC = 3.3 V 23 VCC = 3 V 21 19 17 15 30
Peak-To-Peak OutpuT Jitter (Normalized)
10
IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII
Invalid
Valid
Figure 8. Enable Time Waveforms
Figure 9. Disable Time Waveforms
AVERAGE SUPPLY CURRENT vs CLOCK FREQUENCY
31
PEAK-TO-PEAK OUTPUT JITTER (NORMALIZED) vs MODULATION FREQUENCY
10
1
0.1 0.1 35 40 45 50 55 60 65 70 75 fc - Clock Frequency - MHz
1 f(mod) - Modulation Frequency - MHz
10
Figure 10. Grayscale Input Pattern
Figure 11. Output Period Jitter vs Modulation Frequency
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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
APPLICATION INFORMATION
Host Graphics Controller 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK 44 45 47 48 1 3 4 6 7 9 10 12 13 15 16 18 19 20 22 23 25 26 SN75LVDS84A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKIN Y0M 41 100 Y0P 40 9 A0P 8 Cable Flat Panel Display SN75LVDS86/86A A0M
Y1M
39 100
10
A1M
Y1P
38
11
A1P
Y2M
35 100
14
A2M
Y2P
34
15
A2P
CLKOUTM
33 100
16
CLKINM
CLKOUTP
32
17
CLKINP
NOTES: A. The five 100- terminating resistors are recommended to be 0603 types. B. NA - not applicable, these unused inputs should be left open.
Figure 12. Color Host to LCD Panel Application
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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
APPLICATION INFORMATION
Host Graphics Controller 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK 44 45 47 48 1 3 4 6 7 9 10 12 13 15 16 18 19 20 22 23 25 26 SN75LVDS84A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKIN Y0M 41 100 Y0P 40 10 A0P 9 Cable Flat Panel Display SN75LVDS82 A0M
Y1M
39 100
11
A1M
Y1P
38
12
A1P
Y2M
35 100
15
A2M
Y2P
34
16
A2P
CLKOUTM
33 100
CLKINM
CLKOUTP
32
CLKINP
A3M 100 A3P NOTES: A. The four 100- terminating resistors are recommended to be 0603 types. B. NA - not applicable, these unused inputs should be left open.
Figure 13. 18-Bit Color Host to 24-Bit LCD Display Panel Application
12
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SN75LVDS84A FLATLINKTM TRANSMITTER
SLLS354D - MAY 1999 - REVISED AUGUST 2000
MECHANICAL INFORMATION
DGG (R-PDSO-G**)
48 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,50 48
0,27 0,17 25
0,08 M
6,20 6,00
8,30 7,90
0,15 NOM
Gage Plane 0,25 0- 8 A 0,75 0,50
1
24
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
48
56
64
12,60
14,10
17,10
A MIN
12,40
13,90
16,90 4040078 / F 12/97
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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