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| TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 D D D Low rDS(on) . . . 0.3 Typ High Voltage Output . . . 60 V Extended ESD Capability . . . 4000 V D D Pulsed Current . . . 10 A Per Channel Fast Commutation Speed description The TPIC5401 is a monolithic gate-protected power DMOS array that consists of four N-channel enhancement-mode DMOS transistors, two of which are configured with a common source. Each transistor features integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-k resistor. The TPIC5401 is offered in a 16-pin thermally enhanced dual-in-line (NE) package and a 20-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature range of - 40C to 125C. NE PACKAGE (TOP VIEW) DW PACKAGE (TOP VIEW) DRAIN2 SOURCE2/GND GATE2 GND GND GATE4 SOURCE4/GND DRAIN4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SOURCE1 DRAIN1 GATE1 GND GND GATE3 DRAIN3 SOURCE3 GND SOURCE4/GND GATE4 NC DRAIN4 SOURCE3 DRAIN3 GATE3 NC NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SOURCE2/GND GATE2 NC NC DRAIN2 SOURCE1 DRAIN1 GATE1 NC NC NC - No internal connection schematic DRAIN1 Q1 GATE1 ZC1b ZC1a SOURCE1 DRAIN2 Q2 GATE2 ZC2b ZC2a Z2 Z4 ZC4b ZC4a GND, SOURCE2, SOURCE4 NOTE: For correct operation, no terminal pin may be taken below GND. Q4 GATE4 Z1 D1 D2 Z3 ZC3b ZC3a SOURCE3 DRAIN4 Q3 GATE3 DRAIN3 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1994, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 absolute maximum ratings over operating case temperature range (unless otherwise noted) Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Source-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage (Q2, Q4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 9 V to 18 V Continuous drain current, each output, TC = 25C: DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 A NE package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Continuous source-to-drain diode current, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Pulsed drain current, each output, Imax, TC = 25C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . 10 A Continuous gate-to-source zener-diode current, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Pulsed gate-to-source zener-diode current, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Single-pulse avalanche energy, EAS, TC = 25C (see Figures 4, 15, and 16) . . . . . . . . . . . . . . . . . . . . . . 21 mJ Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms, duty cycle = 2% DISSIPATION RATING TABLE PACKAGE DW NE TC 25C POWER RATING 1389 mW 2075 mW DERATING FACTOR ABOVE TC = 25C 11.1 mW/C 16.6 mW/C TC = 125C POWER RATING 279 mW 415 mW 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 electrical characteristics, TC = 25C (unless otherwise noted) PARAMETER V(BR)DSX VGS(th) V(BR)GS V(BR)SG V(BR) VDS(on) VF(SD) VF IDSS IGSSF IGSSR Ilk lkg Drain-to-source breakdown voltage Gate-to-source threshold voltage Gate-to-source breakdown voltage Source-to-gate breakdown voltage Reverse drain-to-GND breakdown voltage (across D1, D2) Drain-to-source on-state voltage TEST CONDITIONS ID = 250 A, ID = 1 mA, See Figure 5 IGS = 250 A ISG = 250 A Drain-to-GND current = 250 A ID = 2 A, See Notes 2 and 3 VGS = 10 V, VGS = 0 VDS = VGS, MIN 60 1.5 18 9 100 0.6 0.7 1.85 2.2 TYP MAX UNIT V V V V V V Forward on-state voltage, source-to-drain IS = 2 A, VGS = 0 (Z1, Z2, Z3, Z4), See Notes 2 and 3 and Figure 12 ID = 2 A (D1, D2), See Notes 2 and 3 VDS = 48 V, , VGS = 0 VGS = 15 V, VSG = 5 V, VDGND = 48 V VGS = 10 V, ID = 2 A, , See Notes 2 and 3 and Figures 6 and 7 TC = 25C TC = 125C VDS = 0 VDS = 0 TC = 25C TC = 125C TC = 25C TC = 125C 1.6 1 1.2 V Forward on-state voltage, GND-to-drain Zero-gate-voltage Zero gate voltage drain current Forward-gate current, drain short circuited to source Reverse-gate current, drain short circuited to source Leakage current, drain-to-GND current drain to GND 7.5 0.05 0.5 20 10 0.05 0.5 0.3 0.47 1.9 220 275 150 125 1 10 200 100 1 10 0.35 V A nA nA A rDS( ) DS(on) Static drain-to-source on-state resistance drain to source on state 0.5 S gfs Ciss Coss Crss Forward transconductance Short-circuit input capacitance, common source Short-circuit output capacitance, common source Short-circuit reverse-transfer capacitance, common source VDS = 15 V, ID = 1 A, See Notes 2 and 3 and Figure 9 VDS = 25 V, f = 1 MHz, VGS = 0, See Figure 11 120 100 pF F NOTES: 2. Technique should limit TJ - TC to 10C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain and GND-to-drain diode characteristics, TC = 25C PARAMETER trr Reverse-recovery time IS = 1 A, 0, VGS = 0 See Figures 1 and 14 QRR Total diode charge VDS = 48 V, A/s, di/dt = 100 A/s TEST CONDITIONS Z1 and Z3 Z2 and Z4 D1 and D2 Z1 and Z3 Z2 and Z4 D1 and D2 MIN TYP 120 280 260 0.12 0.9 2.2 C ns MAX UNIT POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 resistive-load switching characteristics, TC = 25C PARAMETER td(on) td(off) tr tf Qg Qgs(th) Qgd Ld Ls Rg Turn-on delay time Turn-off delay time Rise time Fall time Total gate charge Threshold gate-to-source charge Gate-to-drain charge Internal drain inductance Internal source inductance Internal gate resistance VDS = 48 V, V See Figure 3 ID = 1 A, A VGS = 10 V, V VDD = 25 V, , t dis = 10 ns, RL = 25 , , See Figure 2 ten = 10 ns, , TEST CONDITIONS MIN TYP 32 40 15 25 6.6 0.8 2.6 5 5 0.25 MAX 65 80 30 50 8 1 3.2 nH nC ns UNIT thermal resistances PARAMETER RJA RJB RJP Junction to ambient thermal resistance (see Note 4) Junction-to-ambient Junction-to-board thermal resistance Junction-to-pin Junction to pin thermal resistance DW NE DW DW NE All outputs with equal power TEST CONDITIONS MIN TYP 90 60 53 30 25 C/W MAX UNIT NOTE 4: Package mounted on an FR4 printed-circuit board with no heatsink. PARAMETER MEASUREMENT INFORMATION 2 VDS = 48 V VGS = 0 TJ = 25C Z1 and Z3 I S - Source-to-Drain Diode Current - A 1 Reverse di/dt = 100 A/s 0 25% of IRM -1 Shaded Area = QRR -2 -3 IRM trr(SD) -4 0 200 400 600 Time - ns 800 1000 1200 IRM = maximum recovery current The above waveform is representative of Z2, Z4, D1, and D2 in shape only. Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 PARAMETER MEASUREMENT INFORMATION VDD = 25 V ten RL Pulse Generator VGS DUT Rgen 50 50 CL 30 pF (see Note A) VDS td(on) tf VDS VGS 0V td(off) tr VDD VDS(on) tdis 10 V VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms Current Regulator 12-V Battery 0.2 F 50 k 0.3 F VDD VDS DUT VGS Gate Voltage Time WAVEFORM IG CurrentSampling Resistor TEST CIRCUIT ID CurrentSampling Resistor Same Type as DUT Qg 10 V Qgs(th) Qgd 0V IG = 100 A Figure 3. Gate-Charge Test Circuit and Waveform POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 PARAMETER MEASUREMENT INFORMATION VDD = 25 V tw VGS 0V IAS (see Note B) ID 0V 50 VDS V(BR)DSX = 60 V Min tav 15 V 354 H Pulse Generator (see Note A) 50 Rgen VDS ID VGS DUT 0V VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration (tw) is increased until peak current IAS = 10 A. I V t av AS (BR)DSX Energy test level is defined as E 21 mJ. AS 2 + + Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VGS(th) - Gate-to-Source Threshold Voltage - V 2.5 VDS = VGS 2 ID = 1 mA 1.5 ID = 100 A 1 r DS(on) - Static Drain-to-Source 0.4 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 0.5 ID = 2 A VGS = 10 V On-State Resistance - 0.3 VGS = 15 V 0.2 0.5 0.1 0 - 40 - 20 0 20 40 60 80 100 120 140 160 0 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ - Junction Temperature - C TJ - Junction Temperature - C Figure 5 Figure 6 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 1 0.9 0.8 0.7 r DS(on) - Static Drain-to-Source 0.6 0.5 0.4 VGS = 10 V 0.3 I D - Drain Current - A On-State Resistance - 5 TJ = 25C 4 VGS = 10 V VGS = 15 V DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE nVGS = 0.2 V TJ = 25C (unless otherwise noted) 3 VGS = 4 V 2 0.2 VGS = 15 V 1 VGS = 3 V 0.1 0.01 0 0.10 1 ID - Drain Current - A 10 0 2 4 6 8 10 12 14 16 18 VDS - Drain-to-Source Voltage - V 20 Figure 7 Figure 8 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE 10 9 8 I D - Drain Current - A 7 6 5 4 3 2 TJ = 150C TJ = - 40C TJ = 25C TJ = 75C TJ = 125C DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 30 Total Number of Units = 1040 VDS = 15 V ID = 1 A TJ = 25C 25 Percentage of Units - % 20 15 10 5 1 1.825 1.875 1.925 1.975 1.85 1.95 1.8 1.9 2 0 0 0 1 2 3 4 5 6 7 8 9 10 VGS - Gate-to-Source Voltage - V gfs - Forward Transconductance - S Figure 9 Figure 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 TYPICAL CHARACTERISTICS CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 500 450 400 Capacitance - pF 350 300 250 200 150 100 50 0 0 10 20 30 40 VDS - Drain-to-Source Voltage - V Coss Crss Ciss I SD - Source-to-Drain Diode Current - A f = 1 MHz VGS = 0 TJ = 25C 10 VGS = 0 6 4 SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE 2 1 0.6 0.4 TJ = 150C 0.2 TJ = 75C 0.1 0.1 1 VSD - Source-to-Drain Voltage - V 10 TJ = 125C TJ = - 40C TJ = 25C Figure 11 DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE 60 ID = 1 A TJ = 25C See Figure 3 VDD = 20 V VDD = 30 V 8 12 400 350 VGS - Gate-to-Source Voltage - V 10 trr - Reverse-Recovery Time - ns 300 250 Figure 12 REVERSE-RECOVERY TIME vs REVERSE di/dt VDS = 48 V VGS = 0 IS = 1 A TJ = 25C See Figure 1 VDS - Drain-to-Source Voltage - V 50 40 Z2 and Z4 200 150 100 50 0 0 100 200 300 400 Reverse di/dt - A/s 500 600 Z1 and Z3 30 6 20 VDD = 48 V 10 VDD = 20 V 0 0 1 2 3 4 5 6 7 Qg - Gate Charge - nC 4 2 0 Figure 13 Figure 14 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 100 I AS - Maximum Peak Avalanche Current - A TC = 25C I D - Maximum Drain Current - A 30 See Figure 4 MAXIMUM PEAK-AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 10 1 s 10 10 ms 1 ms 500 s 1 TC = 25C TC = 125C AA AA AA DW Pkg NE Pkg DC Conditions 1 10 VDS - Drain-to-Source Voltage - V 100 0.1 0.1 1 0.01 0.1 1 10 100 tav - Time Duration of Avalanche - ms Less than 2% duty cycle Figure 15 Figure 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 THERMAL INFORMATION NE PACKAGE NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE vs PULSE DURATION 10 RJA - Normalized Junction-to-Ambient Thermal Resistance - C/W DC Conditions 1 d = 0.5 d = 0.2 d = 0.1 0.1 d = 0.05 d = 0.02 d = 0.01 0.01 Single Pulse 0.001 tw ID 0 tc 0.0001 0.0001 0.001 0.01 0.1 1 10 tw - Pulse Duration - s Device mounted on FR4 printed-circuit board with no heatsink. NOTE A: ZJA(t) = r(t) RJA tw = pulse duration tc = cycle time d = duty cycle = tw/tc Figure 17 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A - DECEMBER 1993 - REVISED MARCH 1994 THERMAL INFORMATION DW PACKAGE JUNCTION-TO-BOARD THERMAL RESISTANCE vs PULSE DURATION 100 DC Conditions RJB - Junction-to-Board Thermal Resistance - C/W d = 0.5 d = 0.2 10 d = 0.1 d = 0.05 d = 0.02 1 d = 0.01 tc tw ID 0 Single Pulse 0.1 0.0001 0.001 0.01 0.1 1 10 tw - Pulse Duration - s Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink. NOTE B: ZJB(t) = r(t) RJB tw = pulse duration tc = cycle time d = duty cycle = tw/tc Figure 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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