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THS1030/31EVM Evaluation Module for the THS1030/THS1031 10 Bit ADC
User's Guide
2000
AAP Data Conversion
SLAU040
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
How to Use This Manual
Preface
Read This First
About This Manual
This manual describes the physical characteristics, functions, modes of operation, and configuration of the THS1030/31EVM evaluation module (EVM).
How to Use This Manual
-
Chapter 1 - Overview Chapter 2 - Physical Description Chapter 3 - Circuit Description Chapter 4 - Modes of Operation
Read This First
iii
iv
Running Title--Attribute Reference
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 THS1030/31EVM Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-2 1-2 1-3
2
Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Parts LIst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 THS1031 Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-6 3-6 3-7 3-7 3-7 3-7 3-8
3
4
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
Figures
2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 4-4 4-5 4-6 4-7 Silk Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silk Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inner 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inner 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Schematic Diagram - DIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Schematic Diagram - LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Schematic Diagram - THS1031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Schematic Diagram - POWER_&_REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Mode Input VREF/2 - 1Vp-p Input Span (top/bottom mode) . . . . . . . . . . . . . . . . Common Mode Input VREF/2 - 2Vp-p Input Span (top/bottom mode) . . . . . . . . . . . . . . . . External Common Mode Input - 1Vp-p Input Span (center span mode) . . . . . . . . . . . . . . External Common Mode Input - 2Vp-p Input Span (center span mode) . . . . . . . . . . . . . . Differential Input - 1Vp-p Input Span (differential input mode) . . . . . . . . . . . . . . . . . . . . . . . Differential Input - 2Vp-p Input Span (differential input mode) . . . . . . . . . . . . . . . . . . . . . . . External Reference - Input Span and Bias Set by on Board Reference Circuit (potentiometer P2 sets EXT_T, potentiometer P3 sets EXT_B) . . . . . . . . . . . . . . . . 2-2 2-3 2-4 2-5 2-6 2-7 3-2 3-3 3-4 3-5 3-6 4-2 4-2 4-3 4-3 4-4 4-4 4-5
vi
Running Title--Attribute Reference
Tables
2-1 3-1 4-1 4-2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Connector J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Jumper Settings for Various Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jumper Settings for Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 3-8 4-6 4-7
Contents
vii
viii
Chapter 1
Overview
This chapter gives a general overview of the THS1030/31EVM evaluation module (EVM), and describes some of the factors that must be considered in using this module.
Topic
1.1 1.2 1.3 1.4
Page
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 THS1030/31 Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Overview
1-1
Purpose
1.1 Purpose
The THS1030/31EVM evaluation module (EVM) provides a platform for evaluation of the THS1030 and THS1031 10-bit analog-to-digital converters (ADC) under various signal, reference, and supply conditions. Unless stated explicitly, the functionality described in this user's guide applies to both THS1030 and THS1031 devices.
1.2 EVM Basic Functions
Analog input to the THS1030/31 is provided via an external SMA connector. The input can be configured onboard to be ac, dc, or transformer coupled to the input of the device. An external SMA connector is provided on the THS1031 for the clamp input. This allows external digital control of the ADC's clamping function. The ADC can be clamped to either the device reference or to ground via an onboard jumper. The EVM provides an external SMA connection for ADC clock input. This can be configured to be either ac or dc coupled. Space is reserved on the board for a crystal oscillator to perform this function, and can be populated when required. In addition to the internal reference from the THS1030/31 device, options are provided on the EVM to allow adjustment of the ADC reference via an onboard reference circuit. Output from the EVM is via a 40-pin header connector. The digital lines from the THS1030/31 are buffered using the SN74LVCC4245A before going to the header. This allows the THS1030/31 supplies to be varied without affecting the output signal levels. Power connections to the EVM are via 4-mm banana sockets. Separate input connectors are provided for the analog and digital supply to the device, and for the reference and output buffer circuits. The THS1031 has a number of programmable registers that can be programmed using DIL switches on the EVM.
1.3 Power Requirements
The EVM has 4 dc-power supply connections: 5 V for the output buffers, 2.7 V to 5 V for the analog and digital supplies to the ADC, and 2.7 V to 5 V for the reference circuit. Each of these supplies is independent, but it should be noted that the input thresholds of the ADC will vary dependent on the digital and analog supply voltages, as per the datasheet specification.
1-2
THS1030/31EVM Operational Procedure
Voltage Limits Exceeding the 5-V maximum can damage EVM components. Undervoltage may cause improper operation of some or all of the EVM components.
1.4 THS1030/31EVM Operational Procedure
The THS1030/31EVM provides a flexible means of evaluating the THS1030 and THS1031 in a number of modes of operation. These are described more fully in chapter 4. The following basic setup procedure can be used as a boardconfidence check:
-
Verify all jumper settings against the following schematic jumper table:
Jumper Table (connection) H1 pin 2-3, H2 pin 2-3, H3 pin 1-2, H4 pin 2-3, H6 pin 1-2, H8 pin 1-2, H9 pin 1-2, H10 pin 1-2, H11 pin 1-2, LINK4, LINK6, LINK10, LINK11, LINK12, LINK13, LINK14, LINK16. H1 pin 2-3, H2 pin 2-3, H3 pin 1-2, H4 pin 2-3, H6 pin 1-2, H8 pin 2-3, H9 pin 1-2, H10 pin 1-2, H11 pin 2-3, LINK4, LINK6, LINK10, LINK11, LINK12, LINK13, LINK14, LINK16.
Device THS1030
THS1031
-
Check that T1 is unpopulated. Connect supplies to the EVM: 5 V on J9, J6, J7, and J8; GND on J10 and J11. Switch power supplies on. Use a DVM to monitor the voltage from TP24 to TP21. Use a potentiometer adjusting tool to adjust P2 such that the DVM reads 2.5 V. Use a DVM to monitor the voltage from TP26 to TP21. Use a potentiometer adjusting tool to adjust P3 such that the DVM reads 0.5 V. Use a function generator with 50- output to input a 10-MHz, 2.5-V offset, 5-Vp-p amplitude signal into J2. Use a function generator with 50- output to input a 50-kHz, 1.5-V offset, 1.5-Vp-p amplitude signal into J3. The digital pattern on the output header J4 should now represent a sine wave, and can be monitored using a logic analyzer.
Overview
1-3
1-4
Chapter 2
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM, and lists the components used on the module.
Topic
2.1 2.1
Page
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Physical Description
2-1
PCB Layout
2.1 PCB Layout
The EVM is constructed on a 4-layer, 151-mm (5.94I) x 115-mm (4.54I), 1.57-mm (0.062I) thick PCB using FR-4 material. Figures 2-1 through 2-6 show the individual layers.
Figure 2-1. Silk Top
2-2
PCB Layout
Figure 2-2. Silk Bottom
Physical Description
2-3
PCB Layout
Figure 2-3. Top
2-4
PCB Layout
Figure 2-4. Inner 1
Physical Description
2-5
PCB Layout
Figure 2-5. Inner 2
2-6
PCB Layout
Figure 2-6. Bottom
Physical Description
2-7
Parts LIst
2.2 Parts LIst
Table 2-1 lists the parts used in constructing the EVM.
Table 2-1. Parts List
Qty 1 1 4 Reference Description D1 U4 U6 U8 U9 U10 Description LT1004-1.2 voltage reference SN74AHC14D hex inverter SN74LVCC4245ADW bus transceiver Manufacturer TI TI TI Part Number LT1004CD-1-2 SN74AHC14D SN74LVCC4245AD W TLV2464CD IQXO-100C 4MHz B3F1000 100-103
1 1 1 6
U7 U11 SW1 TP5, TP6, TP19, TP20, TP21, TP22 TP2, TP3, TP4, TP7, TP8, TP9, TP10, TP11, TP12, TP14, TP15, TP16, TP17, TP18, TP23, TP24, TP25, TP26 TP1 SW3 J2, J3, J5 P1 P2, P3 J6, J7, J8, J9, J10, J11 C38
TLV2464CD quad opamp CMOS Dil 14 oscillator, 4-MHz 6x6 mm flat push-button switch 1.32-mm test pin, black
TI IQD Omron W Hughes
18
1.32-mm test pin, red
W Hughes
100-107
1 1 3 1 2 6 1
1.32-mm test pin, green 0.1I spacing TH 8 way Dil switch SMB connector vertical PCB 2-k 3296Y potentiometer 10-k potentiometer 4-mm panel socket 470-pF 0805 SMD ceramic capacitor NPO 0.1I spacing 1X2 header
W Hughes Multicomp MACOM Bourns Bourns Hirschmann AVX
100-108 MCDS08 B65N07G999X 3296Y-001-202 3296Y-001-106 BO10 08051A471JAT00J
16
LNK1, LNK2, LNK3, LNK4, LNK5, LNK6, LNK7, LNK8, LNK9, LNK10, LNK11, LNK12, LNK13, LNK14, LNK15, LNK16 H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11 SW4 R7, R10, R59 R74 R8, R9, R16 R55 L1, L2, L3, L4
Harwin
M20-9990206
11
0.1I spacing 1X3 header straight
Harwin
M20-9990306
1 3 1 3 1 4
0.1I spacing TH 10 way Dil switch 51R 0805 thick-film resistor 5% 2K 0805 thick-film resistor 1% 5K1 0805 thick-film resistor 5% 11K 0805 thick-film resistor 5% 0R 1206 thick-film resistor
Multicomp Multicomp Multicomp Multicomp Multicomp Multicomp
DS10 CR10510JT CR10202JT CR10512JT CR10113JT CR8XXXJTZ32
2-8
Parts LIst
Table 2-1. Parts List (Continued)
Qty 14 Reference Description R5, R6, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71 R11, R12 R53, R58 R47, R57 R17, R56 R13 R14 R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34 R3, R4, R54, R75, R76, R15 R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R48, R49, R50, R51, R52 J4 Description 39R 0805 thick-film resistor 1% Manufacturer Multicomp Part Number CR10390FT
2 2 2 2 1 1 17
100R 0805 thick-film resistor 1% 180R 0805 thick-film resistor 1% 330R 0805 thick-film resistor 1% 820R 0805 thick-film resistor 1% 1-k 0805 thick-film resistor 1% 1K5 0805 thick-film resistor 1% 4K7 0805 thick-film resistor 1%
Multicomp Multicomp Multicomp Multicomp Multicomp Multicomp Multicomp
CR10101FT CR10181FT CR10331FT CR10821FT CR10102FT CR10152FT CR10472FT
5 1 17
10-k 0805 thick-film resistor 1% 15-k 0805 thick-film resistor 1% 100-k 0805 thick-film resistor 1%
Multicomp Multicomp Multicomp
CR10103FT CR10153FT CR10104FT
1
40-way male PCB mounting header, 0.05" cable pitch, 90-deg 0.1" spacing 2X5 header straight 10-F case B SMD tantalum capacitor, 16-V
Multicomp
9.18541E+11
1 12
J1 C15, C18, C19, C22, C30, C32, C34, C37, C40, C43, C44, C47 C29
Elco Multicomp
008380010000010 TAJB10M16RFX
1
47-F case D SMD tantalum capacitor, 16-V 0.1-F 0805 SMD ceramic capacitor, X7R, 16-V
Multicomp
TAJD47M16RFX
29
C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C16, C17, C20, C21, C23, C24, C25, C26, C28, C31, C33, C35, C36, C39, C41, C42, C45, C46, C48 Q2
AVX
08053C104KA800J
1
2N3904 SOT23 transistor
General Semiconductor General Semiconductor Mini Circuits TI Vantis
IMBT3904
1
Q1
2N3906 SOT23 transistor
IMBT3906
1 1 1
T1 U2 U1
TT1-6-X65 RF transformer THS1031CDB ADC Vantis Mach4_32_32_44TQFP
TT1-6-X65 THS1031CDB M4-32/32-15VC
Physical Description
2-9
2-10
Chapter 3
Circuit Description
This chapter contains the EVM schematic diagram and discusses the various functions on the EVM.
Topic
3.1 3.2
Page
Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Circuit Description
3-1
Schematic Diagram
3.1 Schematic Diagram
Figures 3-1 through 3-5 show the schematic diagram for the EVM. The following paragraphs describe the EVM circuits.
Figure 3-1. EVM Schematic Diagram
DIPS DAC[9:0] PGA[2:0] POWERDOWN IECLAMP +5 V BIN2OUT AGND CLAMPDIS LOGIC DAC[9:0] PGA[2:0] POWERDOWN IECLAMP IO[9:0] BIN2OUT LWR CLAMPDIS LOEB OVR CLK +5V DRVDD AGND THS1031 IO[9:0] LWR LOEB OVR EXT_T EXT_B COM POWER_&_REF EXT_T EXT_B COM AVDD DRVDD +5V + 3 V to 5 VA AGND
DRVDD AVDD AGND
CLK
3-2
R25 R26 4 k7 R28 4 k7 R30 4 k7 R32 4 k7 R34 4 k7 R24 4 k7 R22 4 k7 R20 4 k7 R18 4 k7 R35 R36 R37 R38 R39 R40 R46 100 k 100 k 100 k 100 k 100 k 100 k 100 k R45 R44 R43 R42 R41 R52 R51 R50 R49 R48 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k R23 4 k7 R21 4 k7 R19 4 k7 4 k7 R27 4 k7 R29 4 k7 R31 4 k7 R33 4 k7
DAC9 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 DAC[9:0] CLAMPDIS BIN2OUT IECLAMP POWERDOWN PGA2 PGA1 PGA0 PGA[2:0]
+5V 20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
Figure 3-2. EVM Schematic Diagram - DIPS
SW4
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
SW3
Circuit Description
Schematic Diagram
3-3
Schematic Diagram
3-4
DRVDD +5 V TP5 TP3 R60 CCLK 39R TP4 R61 39R R70 R69 39R R67 CCLK 39R R63 COVR 39R R65 CIO[9:0] 39R R71 39R CIO[9:0] CIO9 CIO8 39R R64 39R R66 39R R62 39R 39R R68 COVR DRVDD CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 OEB4245 CLK OVR IO9 IO8 OEB4245 DRVDD Ribbon Connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 J4 CIO9 CIO8 CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 +5 V +5 V 6 17 28 39 LIO[9:0] LIO7 LIO6 LIO5 LIO4 LIO3 LIO2 LIO1 LIO0 DRVDD IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 +5 V OEBLOGIC 14 8 7 JATAG PORT 2X5 Header 1 2 3 4 5 6 LOG_CLK 7 8 9 10 J1 C48 0.1 F D [9:0] AC +5 V PGA2 U1 PROG_ST TP6 +5 V PGA[2:0] C4 0.1 F C3 0.1 F C5 0.1 F C6 0.1 F C9 0.1 F C10 0.1 F C8 0.1 F C7 0.1 F LIO0 LIO1 LIO2 LIO3 LIO4 LIO5 LIO6 LIO7 LIO8 LIO9 WR1031 OEB4245 OEBLOGIC OEB1031 PGA0 PGA1 OEB1031 LIO9 WR1031 LIO8 LOEB LWR IO9 IO8 +5 V OEBLOGIC LOG_CLK PROG_ST DAC9 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CLAMPDIS BIN2OUT IECLAMP POWERDOWN 37 36 35 34 33 32 31 30 25 24 23 22 21 20 19 18 15 16 38 7 26 4 29 5 27 40 41 42 43 44 1 2 3 8 9 10 11 12 13 14 R74 TP2 2k SW1 MACH4 32/32 VCC GND VCC GND GND TCK GND TMS TDI TDO CLK0/10 CLK1/11 I/O31 I/O30 I/O0 I/O19 I/O1 I/O28 I/O2 I/O27 I/O3 I/O26 I/O4 I/O25 I/O5 I/O24 I/O6 I/O23 I/O7 I/O22 I/O8 I/O21 I/O9 I/O20 I/O10 I/O19 I/O11 I/O18 I/O12 I/O17 I/O13 I/O16 I/O14 I/O15 74LVCC 4245A 1 11 24 VCCA GND 12 VCCB GND 13 GND 10 A7 B7 14 9 A6 B6 15 8 A5 B5 16 7 A4 B4 17 6 B3 18 5 A3 B2 19 4 A2 B1 20 3 A1 A0 B0 21 23 NC T/R 2 OE 22 +5 V U6 74LVCC 4245A 1 GND 11 24 VCCA GND 12 VCCB GND 13 10 A7 B7 14 9 A6 B6 15 8 A5 16 B5 17 7 A4 B4 18 6 A3 B3 19 5 A2 B2 20 4 A1 B1 21 3 A0 B0 23 NC T/R 2 OE 22 +5 V U8 74LVCC 4245A 1 GND 11 24 VCCA GND 12 VCCB GND 13 10 A7 B7 14 9 A6 B6 15 8 A5 16 B5 17 7 A4 B4 18 6 A3 B3 19 5 A2 B2 20 4 A1 B1 21 3 A0 B0 23 NC T/R 2 OE 22 +5 V U9 74LVCC 4245A 11 1 24 VCCA GND 12 VCCB GND 13 GND 10 A7 14 B7 15 9 A6 B6 16 8 A5 B5 17 7 A4 B4 18 6 A3 B3 19 5 A2 B2 20 4 A1 B1 21 3 A0 B0 23 NC T/R 2 OE 22 U10 +5 V DRVDD IO[9:0] C2 0.1 F C1 0.1 F
Figure 3-3. EVM Schematic Diagram - LOGIC
+5 V
OSC U11
+5 V
Press Switch to Write Dip Switch Settings to THS1031
DRVDD AD VD AGND H1 EXT_B AGND REFBS C11 C12 UNPOP UNPOP COM CT 6 PRI SEC T1 R12 100R CT 1 REFBS C13 UNPOP LNK10 LNK11 AGND AVDD REFBF C16 0.1 F REFTF C21 0.1 F AGND AVDD LNK12 AVDD_CLK H3 R9 5k1 H4 P1 2k R8 5k1 ADC_CLK AVDD LNK4 AGND J2 R2 UNPOP AGND AGND Populate With or For THS1030 H8 R72 CLAMPIN UNPOP AGND R73 CLAMP UNPOP AGND AGND THS1030 OEB Option THS1030 STBY Option H11 LWR WR DRVDD H10 R75 10 k AGND OSC U3 14 8 7 AGND AVDD_CLK C25 0.1 F AGND C26 0.1 F AGND AVDD_CLK R7 51R H2 AVDD_CLK T 14 P R5 DUT_CLK 39R LNK3 AGND AGND C 24 0.1uF TP12 R6 CLK C20 0.1 F AGND TP7 AVDD LNK8 J5 MODE R3 10 k LNK7 CLAMP TP8 H5 VREF CLAMPIN AGND LNK1 VREF LNK2 REFSENSE R1 UNPOP C15 10 F AGND REFTS EXT_T LNK5 LNK6 R4 10 k LNK15 AGND R59 51R AGND C18 10 F C17 0.1 F C19 10 F C23 0.1 F C22 10 F H7 47 F DC_IN TP1 R11 100R RL C C26 0.1 F C14 UNPOP 5 TP10 2 H6 TP11 LNK13 AGND C28 AIN TP9 TT1-6-X65 4 PRI SEC 3
J3 R10 51R AGND
IO[9:0] ROVR EXT_T U2 DRVDD
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 LNK9 REFTS LNK16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 AIN VREF REFBS REFBF MODE REFTF REFTS CLAMPIN CLAMP REFSENSE WR OEB DUT_CLK
THS1031 AGND AVDD DRVDD AIN I/O0 VREF I/O1 REFBS I/O2 REFBF MODE I/O3 REFTF I/O4 REFTS I/O5 CLAMPIN I/O6 CLAMP I/O7 I/O8REFSENSE WR I/O9 OEB OVR CLK DGND 28 27 26 25 24 23 22 21 20 19 18 17 16 15
AGND LNK14 0.1 F C29
Figure 3-4. EVM Schematic Diagram - THS1031
1 2 3 4 5 6 7
39R AVDD_CLK 74AHC14 IN 1 VCC 14 OUT 1 IN 6 13 12 IN 2 OUT 6 11 OUT 2 IN 5 10 IN 3 OUT 5 9 OUT 3 IN 4 8 GND OUT 4 U4 AGND
Circuit Description
LOEB OEB DRVDD R76 H9 10 k
Schematic Diagram
3-5
Circuit Function
Figure 3-5. EVM Schematic Diagram - POWER_&_REF
+3TO5VA R13 4MM Sockets TP15 L1 J9 ? C41 0.1 F TP16 L2 ? J6 C42 0.1 F C43 10 F C40 10 F LT1004-1.2 4 AGND +5 V 1k 68 D1 P2 10 k R14 1 k5 C30 10 F AGND AGND +3TO5VA VDD 4 U7.A 3+ 1 2- TLV2464 11 GND AGND R15 R16 15 k 5 k1 AGND +3TO5VA VDD C47 10 F AGND L3 J7 ? C45 0.1 F AGND C44 10 F AGND AGND C39 0.1 F AGND C38 470 pF P3 10 k AGND C34 10 F AGND AGND R55 R54 11 k 10k 4 12 + TLV2464 14 13 - U7.D 11 GND AGND 11 GND TLV2464 9 - 8 10 + U7.C 4 VDD +3TO5VA +3TO5VA VDD 4 U7.B + 7 - TLV2464 11 GND AGND +3TO5VA
TP23
R47 330R R17 820R C31 0.1 F Q1 2N3906 TP24 EXT_T C32 R53 180R 10 F AGND TP25 COM C33 0.1 F
5 6
DRVDD
R58 180R C37 Q1 10 F 2N3904 R47 330R AGND
TP26 EXT_B
L4 ? J8 AGND C46 0.1 F
R17 820R C31 0.1 F
C36 0.1 F
AGND +3TO5VA
Mounting Holes TP19 TP20 TP21 TP22 J10 AGND J11 MO1 1 MO3 1 MO2 1 MO4 1
3.2 Circuit Function
The following paragraphs describe the function of individual circuits. Refer to Chapter 4 for jumper configurations for various modes of operation, and to the relevant data sheet for device operating characteristics.
3.2.1
Inputs
The EVM has one analog input via SMA connector J3. The path from this connector to the THS1030/31 AIN pin can be configured to cater to different operating modes and input signal levels. The main operating modes are ac, dc, and transformer coupled. Note: The transformer should be removed from the board in modes that do not use the signal path through it. The THS1031 has a clamp input that can be fed in directly via SMA connector J5. This affords external digital control of the ADC's clamping function. The ADC can be clamped (via the clamping pin) to either the device reference or to ground using a jumper on H5. SMA Connector J2 can be used to input a clock signal to the board from an external source. If the source does not have the correct dc level for input to the
3-6
Circuit Function
74AHC14 hex inverter IC (U4), then it should be ac-coupled through C24, with its dc level trimmed using potentiometer P1 if necessary.
3.2.2
Clock Options
The EVM provides flexibility as to the source of the ADC conversion clock: this can come from an external source as described above, or from a crystal-oscillator module when U3 is populated with a standard DIL14 HCMOS. Note: Care should be taken when selecting a crystal oscillator module to make sure that it operates at the AVDD supply voltage being used. To synchronize the output data from the ADC to external circuitry, a buffered version of the conversion clock is provided to output header J4 via U4 and U8. The phase relationship between the conversion clock and the output clock can be selected using header H3.
3.2.3
References
In addition to the capability to configure the on-chip reference via jumpers, a reference circuit has been included on the EVM. This uses a 1.2-V shunt reference diode (D1) as its primary source, and allows adjustment of the REFTS and REFBS signals to the ADC using potentiometers P2 and P3, respectively. The ranges of the external reference signals are: REFTS, 0.60 V to 2.68 V on a 2.7-V supply, and 0.60 V to 4.85 V on a 5-V supply; REFBS, 0 V to 1.79 V on a 2.70-V supply, and 0V to 2.00V on a 5 V supply. See Chapter 4 for further details on the jumper settings required to use this mode.
3.2.4
Power
Power is supplied to the EVM via 4-mm banana sockets. Separate input connectors are provided for the analog (J8) and digital (J6) supplies to the device, and for the reference (J7) and output buffer (J9) circuits. The supply for J9 should be 5 V, with the supply for J6, J7, and J8 being between 2.7 V and 5.5 V. Power-supply return paths (GND) are via connectors J10 and J11. Each of these supplies is independent, but it should be noted that the input thresholds of the ADC will vary depending on the digital and analog supply voltages, in accordance with the data sheet specifications.
3.2.5
Outputs
The data outputs from the ADC are buffered using SN74LVCC4245A before going to header J4. This allows the supplies on the THS1030/31 to be varied without affecting the output signal levels. Header J4 is a standard 40-pin device on a 100-mil grid, and allows easy connection to a logic analyzer. The connector test points are listed in Table 3-1.
Circuit Description
3-7
Circuit Function
Table 3-1. Output Connector J4
J4 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OVR CLK Output Function GND NC GND NC GND NC GND GND CLK GND GND GND GND GND GND GND OVR GND GND GND J4 Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 Output I/O9 Function DATA GND DATA GND DATA GND DATA GND DATA GND DATA GND DATA GND DATA GND DATA GND DATA GND
3.2.6
THS1031 Register Write
The THS1031 has a number of registers that can be written to put the device into various modes of operation (see data sheet). This can be accomplished easily on the EVM using the two banks of DIL switches SW3 and SW4. A write operation to the THS1031 is performed as follows : 1) Set the DIL switches to the value to be programmed into the THS1031 registers. Each DIL switch refers to a register bit in either clamp register1, clamp register2, or in the control register. DAC0 DIL switch refers to bit 0 of clamp register1, BIN2O DIL switch refers to bit 5 of the control register. A DIL switch in the on position represents a logic 1. 2) Press and release the push button switch SW1. 3) The THS1031 registers are now programmed with the DIL switch values. Note: After first application of power, the values on the DIL switches only represent what is programmed into the THS1031 after switch SW1 has been pressed. Prior to this, the device is in its default power-up state.
3-8
Chapter 4
Modes of Operation
The EVM can be easily configured, via jumper connections, to operate the THS1030/31 in various modes of operation. Figures 4-1 to 4-7 depict various modes of operation, with Tables 4-1 and 4-2 listing the corresponding jumper settings. For further information on these modes of operation, please refer to the relevant device data sheet.
Modes of Operation
4-1
Figure 4-1. Common Mode Input VREF/2 - 1Vp-p Input Span (top/bottom mode)
1V 0V AIN REFTS REFBS MODE AVDD ADC REF VREF REFSENSE
+ _
THS1030/31 SHA PGA A/D
REFTF 0.1 F 0.1 F REFBF 10 F 0.1 F
-+ 1V
Figure 4-2. Common Mode Input VREF/2 - 2Vp-p Input Span (top/bottom mode)
2V 0V
AIN REFTS REFBS MODE AVDD SHA
THS1030/31 PGA A/D
REFTF ADC REF 0.1 F 0.1 F REFBF 10 F 0.1 F
VREF REFSENSE
+ _
-+ 1V
4-2
Figure 4-3. External Common Mode Input - 1Vp-p Input Span (center span mode)
2V 1V AIN REFTS 1.5 V REFBS MODE AVDD/2 ADC REF
+ _
THS1030/31 SHA PGA A/D
REFTF 0.1 F 0.1 F REFBF 10 F 0.1 F
-+ 1V
VREF REFSENSE
Figure 4-4. External Common Mode Input - 2Vp-p Input Span (center span mode)
2.5 V 0.5 V AIN REFTS 1.5 V REFBS MODE AVDD ADC REF VREF REFSENSE
+ _
THS1030/31 SHA PGA A/D
REFTF 0.1 F 0.1 F REFBF 10 F 0.1 F
-+ 1V
Modes of Operation
4-3
Figure 4-5. Differential Input - 1Vp-p Input Span (differential input mode)
1 VPP AIN COM = AVDD/2 REFTS REFBS MODE AVDD/2 ADC REF
+ _
THS1030/31 SHA PGA A/D
REFTF 0.1 F 0.1 F REFBF 10 F 0.1 F
-+ 1V
VREF REFSENSE
Figure 4-6. Differential Input - 2Vp-p Input Span (differential input mode)
2 VPP AIN COM = AVDD/2 REFTS REFBS MODE AVDD/2 ADC REF
+ _
THS1030/31 SHA PGA A/D
REFTF 0.1 F 0.1 F REFBF 10 F 0.1 F
-+ 1V
VREF REFSENSE
4-4
Figure 4-7. External Reference - Input Span and Bias Set by on Board Reference Circuit (potentiometer P2 sets EXT_T, potentiometer P3 sets EXT_B)
THS1030/31 REFBF AIN 2 VPP SHA PGA A/D REFTF
MODE ADC REF
+ _
REFTF
EXT_T 0.1 F 10 F EXT_B 0.1 F
-+ 1V
VREF REFSENSE AVDD
0.1 F REFBF
Modes of Operation
4-5
4-6
Table 4-1. Board Jumper Settings for Various Modes of Operation
Mode : Top/Bottom (1V) Int Top/Bottom (2V) Int Cent. Span (1V) Int Cent. Span (2V) Int Differential (1V) Int Differential (2V) Int Ext. Ref. Ext. Only
Modes of Operation
Reference:
Refbs/bf Refts/tf Clampin Clamp Header/link H1 H6 H7 H8 H9 H 10 H 11 LINK 1 LINK 2 LINK 3 LINK 4 LINK 5 LINK 6 LINK 7 LINK 8 1-2 1-2 NO 2-3 1-2 1-2 2-3 YES YES NO NO YES NO NO YES
- - H5 J5
- - H5 J5
POT P3 - H5 J5
POT P3 - H5 J5
- - H5 J5
- - H5 J5
POT P3 POT P2 H5 J5 THS1031 only THS1031 only
1-2 1-2 NO 2-3 1-2 1-2 2-3 YES NO YES NO YES NO NO YES
2-3 1-2 NO 2-3 1-2 1-2 2-3 YES YES NO NO NO NO YES NO
2-3 1-2 NO 2-3 1-2 1-2 2-3 NO NO YES NO NO NO YES NO
NO 2-3 NO 2-3 1-2 1-2 2-3 YES YES NO NO NO NO YES NO
NO 2-3 NO 2-3 1-2 1-2 2-3 NO NO YES NO NO NO YES NO
2-3 1-2 NO 2-3 1-2 1-2 2-3 NO NO NO YES NO YES NO NO
LINK 9 LINK 10 LINK 11 LINK 13 LINK 14 LINK 15 LINK 16
NO NO NO YES YES NO NO Figure 4-1
NO NO NO YES YES NO NO Figure 4-2
YES NO NO YES YES NO NO Figure 4-3
YES NO NO YES YES NO NO Figure 4-4
YES NO NO NO NO NO NO Figure 4-5
YES NO NO NO NO NO NO Figure 4-6
NO YES YES YES YES NO YES Figure 4-7
Table 4-2. Jumper Settings for Clock Options
Clock Options H2 H3 H4 LINK 12 Onboard Oscillator 1-2 1-2, 2-3 2-3 YES External AC coupled Via J2 1-2 1-2, 2-3 1-2 YES External DC coupled Via J2 2-3 1-2, 2-3 2-3 YES
Modes of Operation
4-7
4-8
Modes of Operation

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