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TLC5540/TLC5510/TLC5510A/ TL V5540/TL V5510
Evaluation Module
User's Guide
1999
Mixed-Signal Products
SLAU007C
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated
Information About Cautions and Warnings
Preface
Read This First
About This Manual
The purpose of this user's guide is to serve as a reference book for the TLC5540/TLC5510/TLC5510A/TLV5510/TLV5540 devices. This document provides information to assist managers and hardware / software engineers in application development.
How to Use This Manual
This document contains the following chapters:
-
Chapter 1 Overview Chapter 2 Circuit Description Chapter 3 Physical Description
Information About Cautions and Warnings
This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you.
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
Read This First
iii
Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
The following documents may be ordered by contacting the Texas Instruments Product Information Center at one of the numbers listed on the next page, or, they may be downloaded at: http://www-s.ti.com/sc/docs/psheets/pids2.htm
TLC5510/TLC5510A Data Sheet ( literature number SLAS095 ) contains electrical specifications, available temperature options, general overview of the device, and application information. TLC5540 Data Sheet ( literature number SLAS105 ) contains electrical specifications, available temperature options, general overview of the device, and application information. TLV5510 Data Sheet ( literature number SLAS124 ) contains electrical specifications, available temperature options, general overview of the device, and application information. TLV5540 Data Sheet ( literature number SLAS192 ) contains electrical specifications, available temperature options, general overview of the device, and application information.
CE/FCC Warnings
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules.This device has been tested and found to comply with the limits for a CISPRII Group 1 and the following directives: EMC Directive 89/336/EEC amending directive 92/31/EEC and 93/68/EEC as per ENV50204:1995, EN55011: 1995 Class A, EN61000-4-4: 1995, and EN6100-4-3: 1993. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.
iv
Running Title--Attribute Reference
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 EVM Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Direct Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Amplifier Input, DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 Amplifier Input, AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.4 Input Bias Operational Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.5 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.6 User Supplied Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Board Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Board Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Part Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 2-2 2-3 2-3 2-4 2-4 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-6
2
3
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
Figures
2-1 3-1 3-2 3-3 3-4 3-5 Board Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Board Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Board Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Board Layer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Board Layer 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 3-2 3-3 3-4 3-5 3-6
Tables
1-1 2-1 2-2 2-3 3-1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplifier Input Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2-3 2-4 2-4 3-7
vi
Chapter 1
Overview
This chapter gives an overview of the TLC5540/TLC5510/TLC5510A/ TLV5540/TLV5510 evaluation module (EVM).
Topic
1.1 1.2
Page
Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 EVM Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Overview
1-1
Purpose
1.1 Purpose
The TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 evaluation module (EVM) provides a platform for lab prototype evaluation of the Texas Instruments TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 8-bit, high-speed analog-to-digital converters. Since practical operation can be acheived in excess of 40 MHz, the circuit layout is critical and does not lend itself to classic breadboarding techniques. In fact, proper operation requires use of surface-mount components.
1-2
Overview
Power Supply Requirements
1.2 Power Supply Requirements
The TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 EVM is designed to be powered by regulated lab power supplies. Three lab supplies are required for the best performance.
Table 1-1. Power Supplies
If Amp Used Connector J2 J3 J8 Supply Positive analog supply Negative analog supply Digital supply TLC5540/5510/ 5510A 5 V 10% -5 V 10% 5 V 10% TLV5540/5510 3.6 V MIN -3.6 MIN 3.6 V - 3.3 V By-pass Amp TLC5510/ 5540/5510A 5 V 10% N/A 5 V 10% TLV5510/5540 3.6 V - 2.7 V N/A 3.6 V - 2.7 V
The 5 V/3.6 V and -5 V/-3.6 V analog supplies share an analog ground plane. The digital supply uses an isolated ground plane. The two ground planes can be easily connected by soldering jumpers from E21 to E22 or from E13 to E14. This allows the user to adapt the EVM to various grounding conditions that can exist in an evaluation circuit interface.
Overview
1-3
1-4
Overview
Chapter 2
Circuit Description
This chapter describes the EVM circuit and its operation.
Topic
2.1 2.2 2.3 2.4
Page
EVM Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Board Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Circuit Description
2-1
EVM Analog Input
2.1 EVM Analog Input
The EVM analog input signal is applied to BNC connector J4 by one of four methods:
2.1.1 Direct Input
Direct Amplifier input (dc coupled) Amplifier input (ac coupled) User supplied input
To route the signal directly to the TLC5540/TLC5510/TLC5510A/ TLV5540/TLV5510 input, solder jumpers from E7 to E8 and from E23 to E12. This provides a 50-Ohm load (R5) at input connector J4. The input signal must be dc biased to the specifications defined by the data sheet. The TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 is connected using its internal bias resistors. Jumper J6 bypasses one of the internal bias resistors and thus alters the input bias range required by the input signal. With J6 installed, the voltage range of the TLC5540/TLC5510 is 0 V - 2.28 V and TLV5540/TLV5510 is 0 V - 2.74 V (at 3.3 VDDA). The TLC5510A uses only the center internal bias resistor with an externallyapplied regulated 4-V reference to generate the device reference voltage. Hence the input signal range applied to J4 can be between 0 V - 4 V. The input signal is bandlimited to 12 MHz by the LC filter consisting of FB5, R15, and C5. For a bandwidth of 20 MHz, select a value for C5 in the 15 pF to 33 pF range.
2-2
Circuit Description
EVM Analog Input
2.1.2
Amplifier Input, DC Coupled
A THS3001 high-speed transconductance operational amplifier provides buffering for dc-coupled amplifier-input signals. The amplifier circuit provides a flat response to 300 MHz with a gain of two. It can drive a low impedance load. The values of R6 and R8 set the amplifier gain to two. The gain can be reduced to one by removing R6. Since the inverting input is a low-impedance current-controlled input, R8 must remain in the circuit, and its value must be changed to 1 k. This resistance value is critical because it controls the high frequency response of the circuit. The TLC5510A amplifier gain is set to one. The output roll-off filter, consisting of R4 and C14, provides a small amount of filtering against frequencies in excess of 20 MHz (fs/2). The value of C14 can be altered to change the filter characteristics, or C14 can be removed entirely. In most cases, R4 should be retained to lower the direct capacitive load on the operational amplifier, thereby avoiding high frequency peaking of the output signal. Resistor R7 also provides isolation against a direct capacitive load (such as a scope probe) on the test point terminal. The amplifier output circuit is connected to the TLC5540/TLC5510/ TLC5510A/TLV5540/TLV5510 by soldering a jumper between terminals E10 and E12. The amplifier input can be either dc coupled or ac coupled to the input. Table 2-1 shows the jumpers required to select either input coupling method.
Table 2-1. Amplifier Input Coupling
Coupling dc ac Jumper Terminals E3 to E4 E1 to E2
2.1.3
Amplifier Input, AC Coupled
Potentiometer R2 controls the dc input bias for amplifier ac-coupled inputs. This allows the bias to be varied from near ground to near 5 V/3.6 V (analog). With an amplifier gain of two, the output approaches the positive power supply when the bias potentiometer approaches 2.5 V for the TLC5510/TLC5560 and 1.8 V for the TLV5510/TLV5540. For a 4-V input and a gain of 1 (R6 removed and R8 set to 1 k for optimum settling time and minimum ringing) bias potentiometer R2 is adjusted such that E1 is at 2 V and the amplifier output swing is 0 V to 4 V at TP2. With an amplifier supply voltage of +5 V the output positive peak will be distorted slightly; therefore, it is necessary to adjust the 5-V supply to 5.56 V in order to prevent clipping of the amplifier output voltage.
Circuit Description
2-3
EVM Analog Input
The low frequency response pole is dominated by the 4.7-F capacitor (C6) and the resistance setting of the potentiometer.
2.1.4
Input Bias Operational Range
Jumper J6 determines the signal input range (0 to full scale) at the analog input of the TLC5540/TLC5510/TLC5510A/TLV5570/TLV5540. Table 2-2 shows the effects of J6.
Table 2-2. Input Voltage Setting
TLC5540/TLC5510 Input Voltage Jumper J6 Range @ 5 VDDA Removed 0.6 V to 2.6 V TLV5540/TLV5510 Input Voltage Range @ 3.3 VDDA 0.66 V to 2.87 V TLC5510A Input Voltage Range @ 5 VDDA 0 V to 4 V (J11 and J16 installed) 0 V to 4 V (J11 and J16 installed)
Installed
0 V to 2.28 V
0 V to 2.74 V
Other output ranges can be configured. See the TLC5540/TLC5510/ TLC5510A/TLV5540/TLV5510 data sheets.
2.1.5
Test Points
Test points TP1 and TP2 provide an oscilloscope connection to monitor the output of the analog input conditioning amplifier stage as follows:
Table 2-3. Test Points
Test Point TP1 TP2 Connection Analog ground Analog output of THS3001
2.1.6
User Supplied Input Circuit
A breadboarding area allows the use of custom input filters or other signal conditioning circuits. To route the input signal to the breadboarding area (terminal E24), solder a jumper between terminals E5 and E6. To route the signal from the breadboard area (terminal E25) to the TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 input, solder a jumper between terminals E11 and E12. Only one of the above configurations should be used at one time to prevent excessive capacitance on the signal path. This excessive capacitance can degrade the input signal quality at high frequencies.
2-4
Circuit Description
Digital Output
2.2 Digital Output
An octal high-speed latch (U4) provides buffered digital data. The factory configuration uses this latch as a buffer to drive the 22-ohm line damping resistors. Pin 24 on the output connector (J5) can be used to drive the U4 output to a high impedance (3-state) allowing a bus interface to external circuitry. To do so, the jumper between terminals E17 and E18 must be removed to remove the ground connection. Logic 1 applied to J5 pin 24 makes the latch output a 3-state output. This latch can be transparent by using external circuitry to drive the strobe input (pin 11). The jumper at E19 and E20 must be removed and the external drive be connected to E19. A logic 0 on this input captures and holds the input data on the output. A logic 1 allows the outputs to follow the inputs.
Circuit Description
2-5
Clock Circuit
2.3 Clock Circuit
An external clock of up to 40 MHz is required for operation. The clock source is required to drive the 50-ohm BNC input J1. If the clock signal comes from a DSP or microcontroller, resistor R1 should be removed from the circuit. The clock is buffered by inverters (U1) and provides a true (noninverted) output to the TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 and a true equivalent output at pin 22 of the output connector J5. This provides the user a buffered reference clock output for external circuitry.
2-6
Circuit Description
Board Schematic
2.4 Board Schematic
Figure 2-1 shows the EVM board schematic.
Circuit Description
2-7
2-8
5 VD R1 U1A R7 5 VA R12 C8 R4 456 7 74AC11004B See Note C 3 2 -5 VA R8 10 1 11 C 10 E11 C16 E23 R6 E10 - C19 + C14 C7 GND TP1 + 11 10 74AC11004B U1F E20 E19 ANALOG OUT 1 2 TP2 5 VD See Note 4 20 1 74AC11004B 15 16 C4 12 9 U1E R10 U2 7 THS3001 6 + _ 4 J5 8 R13H 9 D1 7 R13G 10 D2 6 R13F 11 D3 5 R13E 12 D4 4 R13D 13 D5 3 R13C 14 D6 2 R13B 15 D7 C15 5 VD VDD VDD REFBS DGND AGND AGND DGND 11 13 + 2 24 C13 C11 C12 5 VD 1 R13A 16 D8 U4 74AC573 GND GND OC FB5 FB1 C5 FB2 FB3 + 5 VA + C9 J10 REFT REFB R3 1 J12 2 C21 20 21 C20 C24 C23 R9 1 J7 2 U5 R14 J6-1 J6-2 1 2 See Note 4 19 See Note 5 1 J13 2 JP3 18 E14 See Note 5 1 J14 E21 JP4 2 E22 See Note 5 13 1 J15 2 74AC11004B U1D 8 E33 TLC5510 TLV5510 TLC5540 TLV5540 TLC5510A JP1, JP2, JP3, JP4, (J6-1-J6-2), J13, J14, J15, (E15-E16), (E17-E18), (E19-E20),J10, J11, C24, C23 JP1, JP2, JP3, JP4, (J6-1-J6-2), J13, J14, J15, (E15-E16), (E17-E18), (E19-E20), J10, J11, C24, C23 74AC11004B U1C 3 74AC11004B U1B 2 FB4 4V 22 + J16 + J11 1 23 OE 1 1 17 C10 REFTS C17 C18 C25 C22 C26 16 + + Breadboard Area E24 E25 R15 U3 JP2 See Note 3 TLC5540/TLC5510/TLC5510A/ E12 TLV5540/TLV5510 12 CLOCK 19 3 ANALOG IN D1 4 D2 14 5 D3 VDDA 6 D4 15 7 VDDA D5 8 D6 18 9 VDDA D7 J9 10 1 D8 9 8 7 6 5 4 3 2 D8 D7 D6 D5 D4 D3 D2 D1 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 VCC 12 13 14 15 16 17 18 19 20 GND D1 GND D2 GND D3 GND D4 GND D5 GND D6 GND D7 GND D8 GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 X 19 20 X 21 22 23 24 GND CLOCK OUT GND OE See Note 4 E27 1 2 E15 E16 1 2 See Note 4 E17 E18 E13 See Option Table See Note 3 E30 DEVICE OPTION TABLE INSTALL JP1, JP2, JP3, JP4, (J6-1-J6-2), J13, J14, J15, (E15-E16), (E17-E18), (E19-E20), J11, J7, J12, R14, R9, R3, U5, J9 AND J16
Figure 2-1. Board Schematic
J1 BNC
CLOCK IN
Board Schematic
R11
R2 POT
5 VA
ANALOG IN
C6
JP1
J4 BNC
+
E1 E2
E3 E4
R5
E5 E6
E7 E8
See Note 6
J8
5 VD
+
5 V dc GND
1 2
C27
J2
5 VA
+
5 V dc GND
1 2
C1
+
GND -5 V dc
J3 2 1
C27
-5 VA
Notes:
1) Unless otherwise specified capacitors are in F, 20%, 50 Vdc.
2) Unless otherwise specified resistors are in ohms, 5%.
3) JP1, JP2, JP3, JP4 are jumper wires that are installed at the factory.
4) (J6-1-J6-2), (E15-E16), (E17-E18), and (E19-E20) are 1" center headers with removable jumpers.
5) E-26, E28, and E30 inverter inputs should be tied to J13-2, J14-2, and J15-2, respectively, if not being used.
6) FB5, R15 and C5 are optional LP filter components.
Chapter 3
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module.
Topic
3.1 3.2 3.3
Page
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Board Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Part Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Physical Description
3-1
Board Layout
3.1 Board Layout
Figure 3-1 shows the EVM board layout.
Figure 3-1. EVM Board Layout
3-2
Physical Description
Board Layers
3.2 Board Layers
Figures 3-2 through 3-5 show the EVM board layers.
Figure 3-2. EVM Board Layer 1
Physical Description
3-3
Board Layers
Figure 3-3. EVM Board Layer 2
3-4
Physical Description
Board Layers
Figure 3-4. EVM Board Layer 3
Physical Description
3-5
Board Layers
Figure 3-5. EVM Board Layer 4
3-6
Physical Description
Part Descriptions
3.3 Part Descriptions
Table 3-1 lists and describes the EVM parts. C2 and E9 are not used.
Table 3-1. Part Descriptions
Quantity 11 13 1 1 3 2 3 1 4 4 1 1 2 1 1 2 1 1 1 2 4 1 1 1 1 1 1 Reference C4, C7, C11 C13, C15, C16, C17, C20, C23, C25, C26 C1, C3, C6, C8-C10, C12, C18, C19, C21, C22, C24, C27 C5 C14 FB1-FB5 J1, J4 J2, J3, J8 J5 J6, (E15, E16), (E17, E18), (E19, E20) R1, R4, R5, R7 R2 R3 R6, R8 R9 R10 R11, R12 R13 R14 R15 TP1, TP2 P6, (P15, P16), (P17, P18), (P19, P20) U1 U2 U3 U4 U5 PCB1 Description 0.1 F capacitor, 50 V, 10%, COG, SMD, size 1206 4.7 F capacitor, tantalum electrolytic, SMD, size A 68 pF capacitor, 50 V, 5%, NPO, SMD, size 1210 100 pF (TLC5540)/150 pF(TLC5510/TLC5510A) capacitor, 50 V, 5%, NPO, SMD, size 0805 Ferrite bead, SMD, size 1206, Murata BLM31B601SPT Connector, BNC, 50 , vertical, PC mount Screw terminal, 2 pin, vertical
12, 0.025 inch square pins, 0.1 inch centers Header, 1 2, 0.025 inch square pins, 0.1 inch centers
Header, 2 Resistor, 49.9 , 1/8 W, 1 %, SMD, size 0805 Potentiometer, 10 k, multiturn SMD Resistor, 20 , 1/4 W, SMD, size 1210 Resistor, 750 , 1/10 W, 1 %, SMD, size 0805 Resistor, 15K, 1/10 W, 1%, SMD, size 1210 Resistor, 22 , 1/10 W, 5%, SMD, size 0805 Resistor, 1 k, 1/10 W, 5 %, SMD, size 0805 Resistor pack, 22
8, 1/8 W, 5%, SMD, SOIC-16
Resistor, 24.9K, 1/10 W, 1%, SMD, size 1210 Resistor, 10 , 1/10 W, 1%, SMD, size 1210 Test point terminal Jumper, for 0.025 inch, square pins, 0.1 inch centers IC, (SN)74AC11004DW inverter, SOIC-16 IC, THS3001CD operational amplifier, SOIC-8 IC, TLC5540INSLE/TLC5510INSLE/TLC5510AINSLE/ TLV5540INSLE/TLV5510INSLE ADC IC, SN74AC573DW octal transparent latch, SOIC-20 IC, TL431AID or TLV431AIDBV5, SOIC-8, SOT-23 PCB, TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510
C5, FB5 and R15 not on REV C PCB
Physical Description
3-7

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