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TLV5639C, TLV5639I 2.7-V TO 5.5-V LOW-POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
SLAS189A - MARCH 1999 - REVISED JUNE 2000
D D D D D D D D D D D D
12-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time vs Power Consumption 1 s in Fast Mode 3.5 s in Slow Mode Compatible With TMS320 Differential Nonlinearity . . . <0.5 LSB Typ Voltage Output Range . . . 2x the Reference Voltage Monotonic Over Temperature
DW OR PW PACKAGE (TOP VIEW)
D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
D1 D0 CS WE LDAC REG AGND OUT REF VDD
applications
Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices
description
The TLV5639 is a 12-bit voltage output digital-to-analog converter (DAC) with a microprocessor compatible parallel interface. It is programmed with a 16-bit data word containing 4 control and 12 data bits. Developed for a wide range of supply voltages, the TLV5639 can be operated from 2.7 V to 5.5 V. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. Because of its ability to source up to 1 mA, the internal reference can also be used as a system reference. With its on-chip programmable precision voltage reference, the TLV5639 simplifies overall system design. The settling time and the reference voltage can be chosen by the control bits within the 16-bit data word. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in 20-pin SOIC and TSSOP packages in standard commercial and industrial temperature ranges.
AVAILABLE OPTIONS PACKAGE TA 0C to 70C - 40C to 85C SOIC (DW) TLV5639CDW TLV5639IDW TSSOP (PW) TLV5639CPW TLV5639IPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
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TLV5639C, TLV5639I 2.7-V TO 5.5-V LOW-POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
SLAS189A - MARCH 1999 - REVISED JUNE 2000
functional block diagram
REF AGND VDD
PGA With Output Enable Voltage Bandgap D(0-11) Power-On Reset 4 4-Bit Control Latch 12 12 12 Powerdown and Speed Control 2 x2 OUT
REG CS WE
Interface Control
12-Bit DAC Holding Latch
12-Bit DAC Register
LDAC
Terminal Functions
TERMINAL NAME AGND CS D0 - D11 LDAC OUT REG REF VDD WE NO. 14 18 1 - 10, 19, 20 16 13 15 12 11 17 I/O/P P I I I O I I/O P I Ground Chip select. Digital input active low, used to enable/disable inputs Data input Load DAC. Digital input active low, used to load DAC output DAC analog voltage output Register select. Digital input, used to access control register Analog reference voltage input/output Positive power supply Write enable. Digital input active low, used to latch data DESCRIPTION
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5639C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5639I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage VDD voltage, Power on threshold voltage, POR High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REF terminal Reference voltage, Vref to REF terminal Load resistance, RL Load capacitance, CL Operating free-air temperature, TA free air temperature TLV5639C TLV5639I 0 -40 VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) VDD = 5 V VDD = 3 V 4.5 2.7 0.55 2 0.8 AGND AGND 2 100 70 85 2.048 1.024 VDD -1.5 VDD - 1.5 NOM 5 3 MAX 5.5 3.3 2 UNIT V V V V V V V k pF C
NOTE 1: Due to the x2 output buffer, a reference input voltage VDD/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used.
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electrical characteristics over recommended operating free-air temperature range, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted)
power supply
PARAMETER TEST CONDITIONS REF on VDD = 5 V IDD Power supply current No load, All inputs = AGND or VDD, DAC latch = 0x800 VDD = 3 V REF off Power down supply current PSRR Power supply rejection ratio Zero scale, See Note 2, External reference Full scale, See Note 3, External reference REF off REF on Fast Slow Fast Slow Fast Slow Fast Slow MIN TYP 2.3 1.3 1.9 0.9 2.1 1.2 1.8 0.9 0.01 -60 -60 MAX 2.8 1.6 2.4 1.2 2.6 1.5 2.3 1.1 1 UNIT mA mA mA mA mA mA mA mA A dB
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) - EG(VDDmin))/VDDmax]
static DAC specifications
PARAMETER Resolution INL DNL EZS EZS TC EG Integral nonlinearity, end point adjusted Differential nonlinearity Zero-scale error (offset error at zero scale) Zero-scale-error temperature coefficient Gain error RL = 10 k, CL = 100 pF, See Note 4 RL = 10 k, CL = 100 pF, See Note 5 See Note 6 See Note 7 See Note 8 20 0.3 TEST CONDITIONS MIN TYP 12 1.2 0.3 3 0.5 12 MAX UNIT bits LSB LSB LSB ppm/C % full scale V
EG TC Gain error temperature coefficient See Note 9 20 ppm/C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero (see text). 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/2Vref x 106/(Tmax - Tmin). 8. Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 k excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/2Vref x 106/(Tmax - Tmin).
output specifications
PARAMETER VO Output voltage Output load regulation accuracy TEST CONDITIONS RL = 10 k VO = 4.096 V, 2.048 V RL = 2 k MIN TYP MAX VDD-0.4 0.29 UNIT V % full scale V
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electrical characteristics over recommended operating free-air temperature range, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) (Continued)
reference pin configured as output (REF)
PARAMETER Vref(OUTL) Vref(OUTH) Iref(source) Iref(sink) PSRR Low reference voltage High reference voltage Output source current Output sink current Power supply rejection ratio -1 -48 VDD > 4.75 V TEST CONDITIONS MIN 1.003 2.027 TYP 1.024 2.048 MAX 1.045 2.069 1 UNIT V V mA mA dB
reference pin configured as input (REF)
PARAMETER VI RI CI Input voltage Input resistance Input capacitance Fast Reference input bandwidth REF = 0 2 Vpp + 1.024 V dc 0.2 1 024 10 kHz H i distortion, reference f Harmonic di t ti in ut input REF = 1 Vpp + 2.048 V dc, VDD = 5 V 50 kHz 100 kHz Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) Slow Fast Slow Fast Slow Fast TEST CONDITIONS MIN 0 10 5 900 500 -87 -77 -74 -61 -66 - 80 kHz dB dB dB dB TYP MAX VDD-1.5 UNIT V M pF
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER IIH IIL Ci High-level digital input current Low-level digital input current Input capacitance TEST CONDITIONS VI = VDD VI = 0 V MIN -1 8 TYP MAX 1 UNIT A A pF
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operating characteristics over recommended operating free-air temperature range, Vref = 2.048 V, and Vref = 1.024 V, (unless otherwise noted)
analog output dynamic performance
PARAMETER ts(FS) (FS) ts(CC) (CC) SR Output settling time, full scale time Output settling time, code to code time Slew rate Glitch energy SNR SINAD THD SFDR Signal-to-noise ratio Signal-to-noise + distortion Total harmonic distortion Spurious free dynamic range fs = 480 kSPS, fout = 1 kHz, kHz, RL = 10 k, fB = 20 kHz k CL = 100 pF F TEST CONDITIONS RL = 10 k, , See Note 11 RL = 10 k, , See Note 12 RL = 10 k, , See Note 13 DIN = 0 to 1, CS = VDD CL = 100 pF, , CL = 100 pF, , CL = 100 pF, , Fast Slow Fast Slow Fast Slow fCLK = 100 kHz, 73 61 63 6 1.2 MIN TYP 1 3.5 0.5 1 10 1.7 5 78 67 -69 74 -62 dB MAX 3 7 1.5 2 UNIT s s V/s nV-S
NOTES: 11. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF or 0xFDF to 0x020. 12. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN tsu(CS-WE) tsu(D) tsu(R) th(DR) tsu(WE-LD) twH(WE) tw(LD) Setup time, CS low before negative WE edge Setup time, data ready before positive WE edge Setup time, REG ready before positive WE edge Hold time, data and REG held valid after positive WE edge Setup time, positive WE edge before LDAC low Pulse duration, WE high Pulse duration, LDAC low 15 10 20 5 5 20 23 NOM MAX UNIT ns ns ns ns ns ns ns
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PARAMETER MEASUREMENT INFORMATION
D(0-7) X Data X
REG
X
Reg tsu(D)
X
CS
tsu(R)
th(DR)
tsu(CS-WE) WE
twH(WE)
tsu(WE-LD)
tw(LD)
LDAC
Figure 1. Timing Diagram
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TYPICAL CHARACTERISTICS
DNL - Differential Nonlinearity - LSB
DIFFERENTIAL NONLINEARITY ERROR
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 Digital Code 2560 3072 3584 4096
Figure 2
INTEGRAL NONLINEARITY ERROR
INL - Intergral Nonlinearity - LSB 3 2 1 0 -1 -2 -3 0 512 1024 1536 2048 Digital Code 2560 3072 3584 4096
Figure 3
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TYPICAL CHARACTERISTICS
MAXIMUM OUTPUT VOLTAGE vs LOAD CURRENT
2.04 2.0395 2.039 VO - Output Voltage - V VO - Output Voltage - V 2.0385 2.038 Fast Mode, Source VDD = 3 V, Vref = Int. 1 V, Input Code = 0xFFF 4.08 4.0795 4.079 4.0785 4.078 Fast Mode, Source VDD = 5 V, Vref = Int. 2 V, Input Code = 0xFFF
MAXIMUM OUTPUT VOLTAGE vs LOAD CURRENT
2.0375 2.037 Slow Mode, Source
4.0775 4.077 Slow Mode, Source
2.0365 2.036 2.0355 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Load Current - mA
4.0765 4.076
4.0755 0 0.5 1 1.5 2 2.5 3 Load Current - mA 3.5 4 4.5
Figure 4
MINIMUM OUTPUT VOLTAGE vs LOAD CURRENT
0.25 Fast Mode, Sink 0.2 VO - Output Voltage - V VO - Output Voltage - V 0.2 0.25
Figure 5
MINIMUM OUTPUT VOLTAGE vs LOAD CURRENT
Fast Mode, Sink
0.15
0.15
0.1 Slow Mode, Sink 0.05 VDD = 5 V, Vref = Int. 2 V, Input Code = 0x000
0.1 Slow Mode, Sink 0.05 VDD = 3 V, Vref = Int. 1 V, Input Code = 0x000 0 0.5 1 1.5 2 2.5 3 Load Current - mA 3.5 4 4.5
0
0 0 0.5 1 1.5 2 2.5 3 Load Current - mA 3.5 4 4.5
Figure 6
Figure 7
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION vs FREQUENCY
VDD = 5 V, REF = 1 V dc + 1 V pp Sinewave, Output Full Scale THD+N - Total Harmonic Distortion and Noise - dB 0 THD - Total Harmonic Distortion - dB -10 -20 -30 -40 -50 -60 -70 -80 Fast Mode -90 -100 100 1000 10000 100000 Slow Mode 0 -10 -20 -30 -40 -50 -60 Slow Mode -70 -80 -90 -100 100 1000 10000 100000 Fast Mode VDD = 5 V, REF = 1 V dc + 1 V pp Sinewave, Output Full Scale
TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY
f - Frequency - Hz
f - Frequency - Hz
Figure 8
POWER DOWN SUPPLY CURRENT vs TIME
1 0.9 0.8 I DD - Supply Current - mA 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 40 50 60 t - Time - s 70 80 90
Figure 9
Figure 10
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APPLICATION INFORMATION general function
The TLV5639 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel interface, a speed and power down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A poweron reset initially puts the internal latches to a defined state (all bits zero).
parallel interface
The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written to the DAC holding latch or the control register depends on REG. REG = 0 selects the DAC holding latch, REG = 1 selects the control register. LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update is not necessary. However, to control the DAC using the load feature, there should be approximately a 5 ns delay after the positive WE edge before driving LDAC low.
TMS320C2XX, 5X A(0-15) TLV5639 REG IS Address Decoder CS LDAC WE WE D(0-11) D(0-15) D(0-15) TCLK0 R/W IOSTROBE D(0-11) >=1 Address Decoder TMS320C3X A(0-15) TLV5639 REG CS LDAC WE
Figure 11
data format
The TLV5639 writes data either to the DAC holding latch or to the control register, depending on the level of the REG input. Data destination: REG = 0 DAC holding latch REG = 1 control register
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APPLICATION INFORMATION
The following table lists the meaning of the bits within the control register:
D11 X X D10 X X D9 X X D8 X X D7 X X D6 X X D5 X X D4 REF1 0 D3 REF0 0 D2 X X D1 PWR 0 D0 SPD 0
Default values X: don't care SPD: Speed control bit PWR: Power control bit
1 fast mode 1 power down
0 slow mode 0 normal operation
REF1 and REF0 determine the reference source and the reference voltage.
REFERENCE BITS REF1 0 0 1 1 REF0 0 1 0 1 REFERENCE External 1.024 V 2.048 V External
If an external reference voltage is applied to the REF pin, external reference must be selected. linearity, offset, and gain error using single end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 12.
Output Voltage
0V Negative Offset DAC Code
Figure 12. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full scale code and the lowest code that produces a positive output voltage.
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APPLICATION INFORMATION TLV5639 interfaced to TMS320C203 DSP
hardware interface Figure 13 shows an example of the connection between the TLV5639 and the TMS320C203 DSP. The only other device that is needed in addition to the DSP and the DAC is the 74AC138 address decoding circuit . Using this configuration, the DAC data is at address 0x0084 and the DAC control word is at address 0x0085 within the I/O memory space of the TMS320C203. LDAC is tied low so that the output voltage is updated on the rising WE edge.
TMS320C203 A2 A3 A4 74AC138 A B C Y1
5V G1 G2A G2B TLV5639 CS REG 12 D(0-11) WE To Other Devices Requiring Voltage Reference LDAC REF OUT RLOAD
A6 IS
A0 D(0-11) WE
Figure 13. TLV5639 to TMS320C203 DSP Interface Connection software Writing data or control information to the TLV5639 is done using a single command. For example, the line of code which reads: out 62h, dac_ctrl writes the contents of address 0x0062 to the I/O address equated to dac_ctrl (0x0085, the address where the DAC control register has been mapped). The following code shows how to set the DAC up to use the internal reference and operate in FAST mode by a write to the control register. Timer interrupts are then enabled and repeatedly generated every 205 s to provide a timebase for synchronizing the waveform generation. In this example, the waveform is generated by simply incrementing a counter and outputting the counter value to the DAC data word once every timer interrupt. This results in a saw waveform.
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APPLICATION INFORMATION
; ; ; ; File: Function: Processors: (c) 1999 Texas RAMP.ASM ramp generation with TLV5639 TMS320C203 Instruments and memory mapped regs --------------- "regs.asm" 0084h 0085h
;---------- I/O .include dac_data .equ dac_ctrl .equ
;------------- vectors ------------------------------- .ps 0h b start b INT1 b INT23 b TIM_ISR ----------Main Program---------- .ps 1000h .entry start: ldp #0 ; set data page to 0 ; disable interrupts setc INTM ; disable maskable interrupts splk #0ffffh, IFR splk #0004h, IMR ; set up the timer splk #0000h, 60h splk #0042h, 61h out 61h, PRD out 60h, TIM splk #0c2fh, 62h out 62h, TCR ; SPD=1 splk #0011h, 62h ; set up the DAC (FAST mode) and ; REF1=1 (2.048 V internal ref enable) out 62h, dac_ctrl clrc ; loop forever! next idle b next ---------- Interrupt Service Routines---------- INT1: ret ; do nothing and return INT23: ret ; do nothing and return TIM_ISR: ; timer interrupt handler add #1h ; increment accumulator sacl 60h out 60h, dac_data ; write to DAC clrc intm ; re-enable interrupts ret ; return from interrupt .END INTM ; enable interrupts
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MECHANICAL DATA
DW (R-PDSO-G**)
16 PIN SHOWN 0.050 (1,27) 16 0.020 (0,51) 0.014 (0,35) 9
PLASTIC SMALL-OUTLINE PACKAGE
0.010 (0,25) M
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** DIM A MAX 0.004 (0,10)
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24) 4040000 / D 02/98
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
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MECHANICAL DATA
PW (R-PDSO-G**)
14 PIN SHOWN 0,30 0,19 14 8
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,05 MIN 0,10
PINS ** DIM A MAX 8 14 16 20 24 28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60 4040064 / E 08/96
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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Price & Availability of SLAS189A

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