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SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR
SDFS031A - D3693, JANUARY 1991 - REVISED OCTOBER 1993
* * * * *
High-Speed fmax of 100 MHz Typical Parallel Asynchronous Load for Modulo-N Count Lengths Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
D OR N PACKAGE (TOP VIEW)
description
B QB QA DOWN UP QC QD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC A CLR BO CO LOAD C D
The SN74F193A is a synchronous, 4-bit binary up/down counter. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count /clock (UP or DOWN) input. The direction of the count is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the LOAD input and entering the desired data at the data (D) inputs. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent of the count and load inputs. These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the carry (CO) output produces a low-level pulse while the count is 15 (all Q outputs high) and the UP input is low. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs, respectively, of the succeeding counter. The SN74F193A is characterized for operation from 0C to 70C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR
SDFS031A - D3693, JANUARY 1991 - REVISED OCTOBER 1993
logic symbol
14 5 4 11 15 1 10 9 CTRDIV16 CT = 0 2+ G1 1- G2 C3 3D 3 2 6 7 QA QB QC QD 1CT = 15
state diagram
0 12 CO 15 2CT = 0 13 BO 14 6 5 1 2 3 4
CLR UP DOWN LOAD A B C D
13
7
12 Count up Count down
11
10
9
8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR
SDFS031A - D3693, JANUARY 1991 - REVISED OCTOBER 1993
logic diagram (positive logic)
14 CLR 12 CO
LOAD
11
13
BO
UP DOWN
5 4 S 15 R S C1 1D R 3
A
QA
1 B S 2 C1 1D R QB
C
10 S 6 C1 1D R QC
D
9
S C1 1D R
7
QD
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2-3
SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR
SDFS031A - D3693, JANUARY 1991 - REVISED OCTOBER 1993
typical clear, load, and count sequence
Illustrated below is the following sequence: 1. Clear outputs to zero 2. Load (preset) to binary thirteen 3. Count up to fourteen, fifteen (carry), zero, one, and two 4. Count down to one, zero (borrow), fifteen, fourteen, and thirteen
CLR LOAD A B C D UP DOWN QA QB Outputs QC QD CO BO 0 Sequence Illustrated Clear Preset 13 14 15 0 Count Up 1 2 1 15 14 0 Count Down 13
Data Inputs
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR
SDFS031A - D3693, JANUARY 1991 - REVISED OCTOBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 mA to 5 mA Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input-voltage ratings may be exceeded if the input-current ratings are observed.
recommended operating conditions
MIN VCC VIH VIL IIK IOH IOL TA Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature 0 4.5 2 0.8 18 -1 20 70 NOM 5 MAX 5.5 UNIT V V V mA mA mA C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL IOS ICC VCC = 4.5 V, VCC = 4.5 V, VCC = 4.75 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5 5 V 5.5 V, VCC = 5.5 V, VCC = 5.5 V, TEST CONDITIONS II = - 18 mA IOH = - 1 mA IOH = - 1 mA to 3 mA IOL = 20 mA VI = 7 V VI = 2.7 V VI = 0 5 V 0.5 VO = 0 Outputs open UP Others - 60 34 MIN 2.5 2.7 0.3 0.5 0.1 20 - 1.8 - 0.6 - 150 54 TYP 3.4 MAX - 1.2 UNIT V V V mA A mA mA mA
All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2-5
SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR
SDFS031A - D3693, JANUARY 1991 - REVISED OCTOBER 1993
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC = 5 V, TA = 25C MIN fclock Clock frequency CLR high tw Pulse duration LOAD low UP or DOWN high UP or DOWN low Data before LOAD inactive tsu th Setup time Hold time CLR inactive before UP or DOWN LOAD inactive before UP or DOWN Data after LOAD inactive 0 4 5.5 4 6 3.5 5 7.5 2.5 MAX 85 VCC = 4.5 V to 5.5 V, TA = MIN to MAX MIN 0 4 5.5 4 6 3.5 5 7.5 2.5 ns ns ns MAX 85 MHz UNIT
switching characteristics (see Note 2)
FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 , TA = 25C MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPLH tPHL 85 2.5 UP or DOWN UP or DOWN A, B, C, A B C or D CO or BO Any Q Any Q Any Q Any Q CLR CLR LOAD A, B, C, A B C or D CO BO CO or BO CO or BO 3 2.5 5 2 6 4.5 5.5 5 6 5 6 6 5.5 4.5 TYP 100 8.5 8 8.5 12 7 13.5 10 12 11 12 11 13.5 12.6 13 12.5 MAX VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 , TA = MIN to MAX MIN 85 2.5 3 2.5 5 1.5 5 4 5 5 5.5 5 6 6 5 4.5 9 9 9 13 8 15 11 13 12 13 12 15 13.8 14 13.5 MAX MHz ns ns ns ns ns ns ns ns
PARAMETER
UNIT
LOAD
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 2: Load circuits and waveforms are shown in Section 1.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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