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DSR QPSK-Demodulator
SDA 6310X
Preliminary Data
Bipolar IC
Features
q Internal reference voltage source. q Automatic gain control (AGC) with integrated AGC q q q q q
q
amplifier. Output for adjustable delayed tuner AGC. Oscillator circuitry for VCO with external varicaps. Symmetrical demodulator output for inphase arm. Open collector counter output for measurement of oscillator frequency. Phase detector circuitry with offset adjust and turn off facility, including arm filters to suppress high frequency terms. Data separator for inphase and quadrature arm, output voltage levels TTL input compatible.
P-DSO-20-1
Type SDA 6310X
Ordering Code Q67000-A5089
Package P-DSO-20-1 (SMD)
The SDA 6310 is an integrated circuit for amplification and demodulation of QPSK-modulated signals.
Semiconductor Group
57
08.93
SDA 6310X
Pin Configuration (top view)
P-DSO-20-1
Semiconductor Group
58
SDA 6310X
Pin Definitions and Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol GND D GND A IN 1 IN 2 DT OUT PD OFF D OUT 1 D OUT 2 I MON 1 I MON 2 Function Digital GND Analog GND QPSK input 1 QPSK input 2, inverse polarity Delayed Tuner AGC output Phase Detector off input Data output 1 Data output 2 Inphase monitor output 1 Inphase monitor output 2 Counter frequency output Reference Voltage Source Phase Detector offset adjust input Phase Detector output Oscillator pin 2 Oscillator pin 1 Delayed Tuner AGC adjust input Analog supply voltage Digital supply voltage Automatic Gain Control
fcounter VREF
PDADJ PD OUT OSC 2 OSC 1 DTADJ
VS A VS D
AGC
Semiconductor Group
59
SDA 6310X
Pin Description Pin No. 1 2 Description Digital GND (counter, data separator, automatic gain control unit). Analog GND (AGC amplifier, oscillator, phase detector, reference voltage source). Reference point for input signal, input filter, PLL loop filter and offset adjust, oscillator, and AGC voltage. Short connection to digital GND required. QPSK input 1. QPSK input 2, inverse polarity. Delayed tuner AGC output, open collector. Phase detector off input, high level switches the phase detector output to high impedance state. Data output 1, inphase arm. Data output 2, quadrature arm. Inphase monitor output 1, inverse polarity. Inphase monitor output 2. Counter frequency output, open collector output (fcounter = fcarr/256). Reference voltage source output, DC reference point for phase detector output, phase detector offset adjust, and delayed tuner AGC adjust. Phase detector offset adjust input. Phase detector output, PLL loop filter. Oscillator pin 2, inverse polarity. Oscillator pin 1 (Oscillator pins 1 and 2 may be used as inputs to force the oscillator). Delayed tuner AGC adjust input. If no delayed tuner AGC is used, connect to digital supply voltage. Analog supply voltage (AGC amplifier, oscillator, phase detector, reference voltage source). Digital supply voltage (counter, data separator, automatic gain control unit). Automatic gain control filter pin, low voltage corresponds to maximum gain of the QPSK input amplifier.
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Semiconductor Group
60
SDA 6310X
Block Diagram Semiconductor Group 61
SDA 6310X
Circuit Description Power Supply, Reference Voltage Source The SDA 6310 has separated power supplies for digital and analog parts. A temperature stable reference voltage source is used for the operating points. QPSK Input Amplifier, AGC The input amplifier is a variable gain amplifier with symmetrical input. The gain control voltage is derived from a level detector at the amplifier output. If the input level exceeds an adjustable value, a sink current is generated which may be used to reduce the tuner output level. Oscillator The symmetrical oscillator contains a divider by 2 to generate the 0 and 90 signals used for the demodulation of the inphase and the quadrature component. For frequency measurement there is a counter output with carrier frequency divided by 256. Phase Detector There is an inphase and a quadrature arm consisting of AM demodulator and armfilter to suppress high frequency terms. The demodulated and filtered inphase and quadrature components are passed to the data separator and the multiplier/adder circuitry. The muliplier/adder circuitry is used to produce a phase detector characteristic with 4 stable points. The phase detector offset current is adjustable, the output can be turned off to high impedance state. The demodulated and filtered inphase component can be monitored at a symmetrical output. Data Separator 2 data streams are separated from the analog inphase and quadrature component signals and converted to TTL input compatible voltage levels.
Semiconductor Group
62
SDA 6310X
Absolute Maximum Ratings TA = - 40 C to 85 C Parameter Analog GND QPSK input 1 QPSK input 2 Delayed tuner AGC output Phase detector off input Data output 1 Data output 2 Inphase monitor output 1 Inphase monitor output 2 Counter frequency output Counter frequency output Reference voltage source Symbol min. Limit Values max. 0.1 6 6 13.2 13.2 5 5 0.5 0.5 5 13.2 1 V V V V V mA mA mA mA mA V mA except capacitive load current at power on - 0.1 0 0 0 0 -5 -5 -5 -5 0 0 -5 Unit Remarks
V2 V3 V4 V5 V6 I7 I8 I9 I10 I11 V11 I12
Phase detector offset adjust input Phase detector output Oscillator pin 2 Oscillator pin 1 Delayed tuner AGC adjust input Analog supply voltage Digital supply voltage Automatic gain control Junction temperature Storage temperature Thermal resistance ESD-Voltage, HBM
V13 V14 V15 V16 V17 V18 V19 V20 TJ TS Rth SA VESD
0 0 0 0 0 0 0 0 - 40 - 40 -4
V12 V18 - 1.5
5 5
V V V V V V V V C C K/W kV 100 pF, 1500
V12
13.2 13.2
V19
150 125 90 4
Semiconductor Group
63
SDA 6310X
Absolute Maximum Ratings (cont'd) Parameter Symbol min. Operating Range Analog supply voltage Digital supply voltage Oscillator frequency QPSK carrier frequency Data rate Data output load Reference source DC current Ambient temperature Limit Values max. Unit Remarks
V18 V19 f15, 16 f3, 4 DR7, 8 C7, 8 I12, DC TA
10.8 10.8 70 35 0 0 - 2.5 -5 0
13.2 13.2 240 120 15 10 0.5 1 70
V V MHz MHz Mbit/s pF mA mA C
Reference source peak current I12
Semiconductor Group
64
SDA 6310X
AC/DC-Characteristics TA = - 25 C; VS = 12 V Parameter Total supply current Power Supply Digital supply current Analog supply current Symbol Limit Values min. typ. 50 max. 65 mA Unit Test Condition
IS
I18 + I19
I19 I18
18 32
25 45
mA mA
Reference Voltage Source Reference voltage Line regulation Load regulation Temperature reg. AGC Unit Input Amplifier f3, 4 = 40.15 MHz inp. imp. resistive inp. imp. capacitive AGC low voltage AGC high voltage Minimum input level Maximum input level
V12
V12 V12 V12
5.5 0 0 - 60
6 30 20 0
6.5 60 60 60
V mV mV mV
V18, 19 = 10.8 13.2 V IR = - 5 to 1 mA TA = 0 C to 70 C
R3, R4 C3 , C4 V20 L V20 H V3, 4 min V3, 4 max
0.7 0.2 2.7 98
1 1 0.7 3.2 49 102
1.3 1.2 3.7 52 106
k pF V V
V3, 4 = 52 dB/V1) V3, 4 = 98 dB/V
dB/V V20 = 0.2 V dB/V V20 = 5 V
AGC Load Characteristic
f3, 4 = 40.15 MHz, reference level V3, 4 = 86 dB/V
AGC load current AGC sink current AGC load character.
1) Note 1 (see page 72)
I20 load I20 load
I20
- 30 10 - 11
- 20 20 -8
- 15 25 -5
A A
V3, 4 = 96 dB/V1) V3, 4 = 76 dB/V
A/dB V3, 4 = 85 87 dB/V
Semiconductor Group
65
SDA 6310X
AC/DC-Characteristics (cont'd) Parameter Symbol Limit Values min. Delayed Tuner AGC (DTAGC) V17 = 2 V, V5 = 5 V DTAGC ON current DTAGC OFF current DTAGC characteristic DTAGC DC volt. range typ. max. Unit Test Condition
I5 ON I5 OFF
3
6 0.05 30 0.5 45
mA mA mA/V V
V20 = V17 + 0.1 V2) V20 = V17 - 0.2 V V20 = V17 - 10 mV...V17 + 10 mV
I5/V20 20
V17
0
V12
Frequency Response reference frequency 40.15 MHz high level upper limit high level lower limit low level upper limit low level lower limit
fmax H fmin H fmax L fmin L
130
150 20 25
MHz MHz MHz 30 MHz
V3, 4 = 98 dB/V,
- 3 dB I MON 1,2
V3, 4 = 98 dB/V,
- 3 dB I MON 1,2
130
180 25
V3, 4 = 52 dB/V,
- 3 dB I MON 1,2
V3, 4 = 52 dB/V,
- 3 dB I MON 1,2
Input Amplifier f3, 4 = 118 MHz AGC low voltage AGC high voltage Minimum input level Maximum input level
V20 L V20 H V3, 4 min V3, 4 max
0.5 2.7 98
1 3.2 46 105
1.5 3.7 52 109
V V
V3, 4 = 52 dB/V V3, 4 = 98 dB/V
dB/V V20 = 0.2 V dB/V V20 = 5 V
2) Note 2 (see page 73)
Semiconductor Group
66
SDA 6310X
AC/DC-Characteristics (cont'd) Parameter Symbol Limit Values min. Phase Detector (PD) PD Gain PD DC range PD large signal offset current PD DC-offset current PD offset adjust current range PD offset adjust characteristic PD offset adjust input impedance Leakage current PD OFF PD source resistor Input voltage PD OFF Input voltage PD ON PD OFF threshold Low input current High input current Monitor Output Monitor DC voltage Monitor AC voltage typ. max. Unit Test Condition
PDG V14
700 2.5
950
1200 A/ rad
3)
V12
V18 - V
1.5
I14/12 I14/12 I14/12 I14/12
I14/ V13
- 30 - 30 - 90 5 30 3.5
0 0 - 30 30 40 5
30 30 -5 90 50 6.5 0.2
A A A A A/V k A k V
4)
V3, 4 = 0 V13 = 1.5 V V13 = 4.5 V V13 = 2.5 3.5 V
I14/12 R14 V6 OFF V6 ON V6 thr I6 L I6 H
- 0.2 0 300 2.0 400
V14 = V12, V6 = V12
0.8 0.8 - 10 0 1.4 0.05 2.0 1 - 0.6 0
V V A A
V6 = 0 V6 = V18
V9 = , V10 = V10~ - V9~
V18 - V18 _ V18 - V
4 350 3.5 500 3 650 mVpp
3) Note 3 (see page 74) 4) Note 4 (see page 75)
Semiconductor Group
67
SDA 6310X
AC/DC-Characteristics (cont'd) Parameter Symbol Limit Values min. Data Separator Separator offset Output low level Output high level Fall time 2.0 V 0.8 V Oscillator5) Oscillator input threshold PD-Gain linearity Oscillator input admittance Real part Imag. part Real part Imag. part Oscillation level -5 0 0.3 2.4 3.0 18 18 30 30 5 0.6 % V V ns ns typ. max. Unit Test Condition
V7, 8 L V7, 8 H t7, 8 fall
Rise time 0.8 V 2.0 V t7, 8 rise
C7, 8 = 10 pF C7, 8 = 10 pF
V15, 16
PDG
Y = G + jB, SIE = 1/
97 -1 0
102 1
dB/V PDG = - 3 dB dB
V15, 16 = 107 113 dB/V
G15, 16 B15, 16 G15, 16 B15, 16
-5 -3 -5 5 107 107 110 110
-3 -1 113 113
mS mS mS mS
f = 80.3 MHz f = 80.3 MHz f = 236 MHz f = 236 MHz
VOSC VOSC
dB/V f = 80.3 MHz dB/V f = 236 MHz
Counter Frequency Output fcounter = fcarr/256 = fosc/512 Low level voltage Rise time 10 90 % Fall time 90 10 %
V11 L t11 rise t11 fall
500 10
0.4 0.1 800 200
V A ns ns
I11 = 3 mA V11 = 5 V R11 = 10 k (5 V), Cload = 10 pF R11 = 10 k (5 V), Cload = 10 pF
High level leakage curr. I11 H
5) Note 5 (see page 75)
Semiconductor Group
68
SDA 6310X
Test Circuit Semiconductor Group 69
SDA 6310X
Application Circuit 40.15 MHz Semiconductor Group 70
SDA 6310X
Application Circuit 118 MHz Semiconductor Group 71
SDA 6310X
Note 1 AGC Characteristics
Input Amplifier
Load Characteristic
Semiconductor Group
72
SDA 6310X
Note 2 Delayed Tuner AGC Characteristic
Semiconductor Group
73
SDA 6310X
Note 3 Definition of Phase Detector Gain (PDG)
Theorie: V() = Vp sin sign (cos) - Vp cos sign (sin) PD-GainPDG = 1 0.5Vpp/R -------- (not exact because of non ideal waveform) rad 1 0.816Vpp PDG = 1.15 0.5Vpp/R -------- = ----------------------rad R rad 2 1 2.56Vrms PDG = 1.09 ----------- Vrms/R -------- = -----------------------2 rad R rad Application hint: PD-Gain is lower with data modulation on, typ. - 8 dB.
Approximations:
Semiconductor Group
74
SDA 6310X
Note 4 PD OFF Input Characteristic
Note 5 Application Circuit for use of Internal Oscillator (not subject to production testing)
Center Freq. 80.3 MHz 236 MHz
Remarks Coil Ceramic Capacitor Ceramic Capacitor Resistor
L C1 C2 Rp
330 nH 12 pF 12 pF 2 k
36 nH 8.2 pF 8.2 pF 1 k
Semiconductor Group
75

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