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SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS418E - JUNE 1998 - REVISED JUNE 2000
D D D D D D
EPICTM (Enhanced-Performance Implanted CMOS) Process Inputs Are TTL-Voltage Compatible True Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
SN54AHCT367 . . . J OR W PACKAGE SN74AHCT367 . . . D, DB, DGV, N, OR PW PACKAGE (TOP VIEW)
1OE 1A1 1Y1 1A2 1Y2 1A3 1Y3 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 2OE 2A2 2Y2 2A1 2Y1 1A4 1Y4
SN54AHCT367 . . . FK PACKAGE (TOP VIEW)
1A1 1OE NC VCC 2OE 1Y1 1A2 NC 1Y2 1A3
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
description
The 'AHCT367 devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
2A2 2Y2 NC 2A1 2Y1
NC - No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54AHCT367 is characterized for operation over the full military temperature range of -55C to 125C. The SN74AHCT367 is characterized for operation from -40C to 85C.
FUNCTION TABLE (each buffer/driver) INPUTS OE H L L A X H L OUTPUT Y Z H L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 2000, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
1Y3 GND NC 1Y4 1A4
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SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS418E - JUNE 1998 - REVISED JUNE 2000
logic symbol
1 1OE 2 4 6 10 EN 3 5 7 9
1A1 1A2 1A3 1A4
1Y1 1Y2 1Y3 1Y4
15 2OE 12 14
EN 11 13
2A1 2A2
2Y1 2Y2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
logic diagram (positive logic)
1OE 1 2OE 15
1A1
2
3
1Y1
2A1
12
11
2Y1
To Three Other Channels Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
To One Other Channel
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS418E - JUNE 1998 - REVISED JUNE 2000
recommended operating conditions (see Note 3)
SN54AHCT367 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 5.5 VCC -8 8 20 0 0 MAX 5.5 SN74AHCT367 MIN 4.5 2 0.8 5.5 VCC -8 8 20 MAX 5.5 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II IOZ ICC ICC Ci Co TEST CONDITIONS IOH = -50 mA IOH = -8 mA IOL = 50 mA IOL = 8 mA VI = VCC or GND VI = VCC or GND, VO = VCC or GND, OE = VIH VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND VI = VCC or GND VCC 4.5 45V 4.5 45V 0 V to 5.5 V 5.5 V 5.5 V 5.5 V 5V 2.5 MIN 4.4 3.94 0.1 0.36 0.1* 0.25 4 1.35 10 TA = 25C TYP MAX 4.5 SN54AHCT367 MIN 4.4 3.8 0.1 0.44 1* 2.5 40 1.5 10 MAX SN74AHCT367 MIN 4.4 3.8 0.1 0.44 1 2.5 40 1.5 10 MAX UNIT V V
mA mA mA
mA pF pF
VO = VCC or GND 5V 5 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS418E - JUNE 1998 - REVISED JUNE 2000
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A TO (OUTPUT) Y Y Y Y Y Y LOAD CAPACITANCE CL = 15 pF CL = 15 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF MIN TA = 25C TYP MAX 2.5* 2.5* 3.5* 2.8* 3.1* 2.8* 3.5 3.3 4.5 3.7 4.1 3.6 4.8* 4.8* 8* 7* 8* 7* 5.8 5.8 9 8 9 8 SN54AHCT367 MIN 1* 1* 1* 1* 1* 1* 1 1 1 1 1 1 MAX 6.5* 6.5* 9.5* 8.5* 9.5* 8.5* 7.5 7.5 10.5 9.5 10.5 9.5 SN74AHCT367 MIN 1 1 1 1 1 1 1 1 1 1 1 1 MAX 5.5 5.5 8.5 7.5 8.5 7.5 6.5 6.5 9.5 8.5 9.5 8.5 UNIT ns ns ns ns ns ns
OE OE A
OE OE
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25C (see Note 4)
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 2 0.8 SN74AHCT367 MIN TYP 0.4 -0.4 4.7 MAX UNIT V V V V V
VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load, f = 1 MHz TYP 22 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS418E - JUNE 1998 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS 3V Timing Input 1.5 V 0V 3V tsu Data Input 0V 1.5 V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V 1.5 V tPZL 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) 50% VCC 1.5 V 0V tPLZ VCC VOL + 0.3 V VOL tPHZ VOH - 0.3 V VOH 0 V
tw
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
1.5 V
1.5 V 0V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL
Output Control
Output Waveform 1 S1 at VCC (see Note B)
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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