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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
D D D D D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25C 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports 8-Bit Serial-In, Parallel-Out Shift Shift Register Has Direct Clear Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J)
SN54LV595A . . . J OR W PACKAGE SN74LV595A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW)
QB QC QD QE QF QG QH GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC QA SER OE RCLK SRCLK SRCLR QH
SN54LV595A . . . FK PACKAGE (TOP VIEW)
QC QB NC VCC QA QD QE NC QF QG
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
SER OE NC RCLK SRCLK
QH
GND NC QH
The 'LV595A devices are 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54LV595A is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV595A is characterized for operation from -40C to 85C.
NC - No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
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SRCLR
description
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
FUNCTION TABLE INPUTS SER X X X L H X X X SRCLK X X X X X SRCLR X X L H H H X X RCLK X X X X X X OE H L X X X X X X FUNCTION Outputs QA-QH are disabled. Outputs QA-QH are enabled. Shift register is cleared. First stage of the shift register goes low. Other stages store the data of previous stage, respectively. First stage of the shift register goes high. Other stages store the data of previous stage, respectively. Shift-register state is not changed. Shift-register data is stored in the storage register. Storage-register state is not changed.
logic symbol
OE RCLK 13 12 EN3 C2 SRG8 R C1/ 14 15 1D 2D 3 1 2 3 4 5 6 2D 3 7 9
10 SRCLR SRCLK 11
SER
QA QB QC QD QE QF QG QH QH
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
logic diagram (positive logic)
OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D Q C1 R 3D C3 Q
15
QA
2D Q C2 R
3D C3 Q
1
QB
2D Q C2 R
3D C3 Q
2
QC
2D Q C2 R
3D C3 Q
3
QD
2D Q C2 R
3D C3 Q
4
QE
2D Q C2 R
3D C3 Q
5
QF
2D Q C2 R
3D C3 Q
6
QG
2D Q C2 R
3D C3 Q
7
QH QH
9
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH'
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IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
recommended operating conditions (see Note 4)
SN54LV595A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 High or low state 3-state VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 0 0 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC 5.5 -50 -2 -8 -16 50 2 8 16 200 100 0 0 0 0 0 MAX 5.5 SN74LV595A MIN 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC 5.5 -50 -2 -8 -16 50 2 8 16 200 100 ns/V mA A mA V V MAX 5.5 UNIT V
VIH
High-level High level input voltage
VIL
Low-level Low level input voltage
VI VO
Input voltage Output voltage
V V A
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V 0 20 0 20 TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A IOH = -2 mA VOH QH QA-QH QH QA-QH IOH = -6 mA IOH = -8 mA IOH = -12 mA IOH = -16 mA IOL = 50 A IOL = 2 mA VOL QH QA-QH QH QA-QH II IOZ ICC Ioff Ci IOL = 6 mA IOL = 8 mA IOL = 12 mA IOL = 16 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND IO = 0 VI or VO = 0 to 5.5 V VI = VCC or GND SN54LV595A VCC 2 V to 5.5 V 2.3 V 3V 4.5 45V 2 V to 5.5 V 2.3 V 3V 4.5 45V 0 V to 5.5 V 5.5 V 5.5 V 0V 3.3 V 3.5 MIN VCC-0.1 2 2.48 2.48 3.8 3.8 0.1 0.4 0.44 0.44 0.55 0.55 1 5 20 5 3.5 TYP MAX SN74LV595A MIN VCC-0.1 2 2.48 2.48 3.8 3.8 0.1 0.4 0.44 0.44 0.55 0.55 1 5 20 5 A A A A pF V V TYP MAX UNIT
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX SRCLK high or low tw Pulse duration RCLK high or low SRCLR low SER before SRCLK tsu SRCLK before RCLK Setup time SRCLR low before RCLK SRCLR high (inactive) before SRCLK 7 7 6 2.5 8 8.5 4 SN54LV595A MIN MAX 7.5 7.5 6.5 3 9 9.5 4 SN74LV595A MIN MAX 7.5 7.5 6.5 3 9 9.5 4 ns ns UNIT
th Hold time SER after SRCLK 1.5 1.5 1.5 ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX SRCLK high or low tw Pulse duration RCLK high or low SRCLR low SER before SRCLK tsu SRCLK before RCLK Setup time SRCLR low before RCLK SRCLR high (inactive) before SRCLK 5.5 5.5 5 3.5 8 8 3 SN54LV595A MIN MAX 5.5 5.5 5 3.5 8.5 9 3 SN74LV595A MIN MAX 5.5 5.5 5 3.5 8.5 9 3 ns ns UNIT
th Hold time SER after SRCLK 1.5 1.5 1.5 ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX SRCLK high or low tw Pulse duration RCLK high or low SRCLR low SER before SRCLK tsu SRCLK before RCLK Setup time SRCLR low before RCLK SRCLR high (inactive) before SRCLK 5 5 5.2 3 5 5 2.5 SN54LV595A MIN MAX 5 5 5.2 3 5 5 2.5 SN74LV595A MIN MAX 5 5 5.2 3 5 5 2.5 ns ns UNIT
th Hold time SER after SRCLK 2 2 2 ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ RCLK SRCLK SRCLR OE OE RCLK SRCLK SRCLR OE OE QA-QH Q QH QH QA-QH Q QA-QH Q QA-QH Q QH QH QA-QH Q QA-QH Q CL = 50 pF CL = 15 pF FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN 65* 60 TA = 25C TYP MAX 80* 70 8.4* 8.4* 9.4* 9.4* 8.7* 8.2* 10.9* 8.3* 9.2* 11.2 11.2 13.1 13.1 12.4 10.8 13.4 12.2 14 14.2* 14.2* 19.6* 19.6* 14.6* 13.9* 18.1* 13.7* 15.2* 17.2 17.2 22.5 22.5 18.8 17 21 18.3 20.9 SN54LV595A MIN 45* 40 1* 1* 1* 1* 1* 1* 1* 1* 1* 1 1 1 1 1 1 1 1 1 15.8* 15.8* 22.2* 22.2* 16.3* 15* 20.3* 15.6* 16.7* 19.3 19.3 25.5 25.5 21.1 18.3 23 19.5 22.6 MAX SN74LV595A MIN 45 40 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15.8 15.8 22.2 22.2 16.3 15 20.3 15.6 16.7 19.3 19.3 25.5 25.5 21.1 18.3 23 19.5 22.6 ns ns MAX UNIT MHz
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ RCLK SRCLK SRCLR OE OE RCLK SRCLK SRCLR OE OE QA-QH Q QH QH QA-QH Q QA-QH Q QA-QH Q QH QH QA-QH Q QA-QH Q CL = 50 pF CL = 15 pF FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN 80* 55 TA = 25C TYP MAX 120* 105 6* 6* 6.6* 6.6* 6.2* 6* 7.8* 6.1* 6.3* 7.9 7.9 9.2 9.2 9 7.8 9.6 8.1 9.3 11.9* 11.9* 13* 13* 12.8* 11.5* 11.5* 14.7* 14.7* 15.4 15.4 16.5 16.5 16.3 15 15 15.7 15.7 SN54LV595A MIN 70* 50 1* 1* 1* 1* 1* 1* 1* 1* 1* 1 1 1 1 1 1 1 1 1 13.5* 13.5* 15* 15* 13.7* 13.5* 13.5* 15.2* 15.2* 17 17 18.5 18.5 17.2 17 17 16.2 16.2 MAX SN74LV595A MIN 70 50 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 13.5 13.5 15 15 13.7 13.5 13.5 15.2 15.2 17 17 18.5 18.5 17.2 17 17 16.2 16.2 ns ns MAX UNIT MHz
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ RCLK SRCLK SRCLR OE OE RCLK SRCLK SRCLR OE OE QA-QH Q QH QH QA-QH Q QA-QH Q QA-QH Q QH QH QA-QH Q QA-QH Q CL = 50 pF CL = 15 pF FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN 135* 120 TA = 25C TYP MAX 170* 140 4.3* 4.3* 4.5* 4.5* 4.5* 4.3* 5.4* 2.4* 2.7* 5.6 5.6 6.4 6.4 6.4 5.7 6.8 3.5 3.4 7.4* 7.4* 8.2* 8.2* 8* 8.6* 8.6* 6* 5.1* 9.4 9.4 10.2 10.2 10 10.6 10.6 10.3 10.3 SN54LV595A MIN 115* 95 1* 1* 1* 1* 1* 1* 1* 1* 1* 1 1 1 1 1 1 1 1 1 8.5* 8.5* 9.4* 9.4* 9.1* 10* 10* 7.1* 7.2* 10.5 10.5 11.4 11.4 11.1 12 12 11 11 MAX SN74LV595A MIN 115 95 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8.5 8.5 9.4 9.4 9.1 10 10 7.1 7.2 10.5 10.5 11.4 11.4 11.1 12 12 11 11 ns ns MAX UNIT MHz
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 5)
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 2.31 0.99 SN74LV595A MIN TYP 0.3 -0.2 2.8 MAX UNIT V V V V V
VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation ca acitance dissi ation capacitance TEST CONDITIONS CL = 50 pF F, f = 10 MHz VCC 3.3 V 5V TYP 111 114 UNIT pF F
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS414E - APRIL 1998 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC 0V VCC tsu Data Input 0V 50% VCC th VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC 50% VCC tPZL Output Waveform 1 S1 at VCC (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B) 50% VCC 50% VCC 50% VCC 0V tPLZ VCC VOL + 0.3 V VOL tPHZ VOH - 0.3 V VOH 0 V
tw
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
50% VCC
50% VCC 0V tPHL
Output Control
50% VCC
VOH 50% VCC VOL tPLH
50% VCC
VOH 50% VCC VOL
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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