 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CD54/74HC597, CD74HCT597 Data sheet acquired from Harris Semiconductor SCHS191A January 1998 - Revised May 2000 High Speed CMOS Logic 8-Bit Shift Register with Input Storage Description The 'HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL is high. Features * Buffered Inputs [ /Title (CD74 HC597 , CD74 HCT59 7) /Subject High peed MOS * Asynchronous Parallel Load * Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH Ordering Information PART NUMBER CD54HC597F3A CD74HC597E CD74HC597M CD74HCT597E CD74HCT597M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC Pinout CD54HC597 (CERDIP) CD74HC597, CD74HCT597 (PDIP, SOIC) TOP VIEW D1 1 D2 2 D3 3 D4 4 D5 5 D6 6 D7 7 GND 8 16 VCC 15 D0 14 DS 13 PL 12 STCP 11 SHCP 10 MR 9 Q7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) 2000, Texas Instruments Incorporated 1 CD54/74HC597, CD74HCT597 Functional Diagram DS D0 D1 D2 PARALLEL DATA INPUTS D3 D4 D5 D6 D7 STCP SHCP PL MR 15 1 2 3 8 F/F STORAGE REG. 5 4 6 7 12 11 13 10 9 Q7 8-BIT SHIFT REG. 14 FUNCTION TABLE STCP No Clock Edge X SHCP X X X X PL X L L L MR X H H L FUNCTION Data Loaded to Input Flip-Flops Data Loaded from Inputs to Shift Register Data Transferred from Input Flip-Flops to Shift Register Invalid Logic, State of Shift Register Indeterminate when Signals Removed Shift Register Cleared Shift Register Clocked Qn = Qn-1, Q0 = DS X X X H H L H NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care, = Transition from Low to High CP Level 2 CD54/74HC597, CD74HCT597 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA Thermal Information Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 V V V V V V V V V V V V V V V V V V A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS 3 CD54/74HC597, CD74HCT597 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) 0 25oC MIN TYP MAX 8 -40oC TO 85oC -55oC TO 125oC MIN MAX 80 MIN MAX 160 UNITS A VCC (V) 6 -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 0 0 - 5.5 5.5 4.5 to 5.5 100 0.1 8 360 - 1 80 450 - 1 160 490 A A A HCT Input Loading Table INPUT DS Dn PL, MR STCP, SHCP UNIT LOADS 0.2 0.3 1.5 1.5 NOTE: Unit load is ICC limit specified in DC Electrical Specifications Table, e.g., 360A max. at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER HC TYPES SHCP Frequency fMAX 2 4.5 6 6 30 35 5 25 29 4 20 23 MHz MHz MHz SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN TYP MAX -55oC TO 125oC MIN TYP MAX UNITS 4 CD54/74HC597, CD74HCT597 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER SHCP Pulse Width SYMBOL tW VCC (V) 2 4.5 6 STCP Pulse Width tW 2 4.5 6 MR Pulse Width tW 2 4.5 6 PL Pulse Width tW 2 4.5 6 STCP to SHCP Setup Time tSU 2 4.5 6 DS to SHCP Setup Time Dn to STCP Setup Time tSU 2 4.5 6 STCP to SHCP Setup Time tH 2 4.5 6 DS to SHCP Hold Time Dn to STCP Hold Time tH 2 4.5 6 MR to SHCP Removal Time tREM 2 4.5 6 HCT TYPES SHCP Frequency SHCP Pulse Width STCP Pulse Width MR Pulse Width PL Pulse Width STCP to SHCP Setup Time fMAX tW tW tW tW tSU 4.5 4.5 4.5 4.5 4.5 4.5 25 20 13 18 16 24 20 25 16 23 20 30 16 30 20 27 24 36 MHz ns ns ns ns ns MIN 80 16 14 60 12 10 80 16 14 70 14 12 100 20 17 50 10 9 0 0 0 3 3 3 3 3 3 TYP MAX -40oC TO 85oC MIN 100 20 17 75 15 13 100 20 17 90 18 15 125 25 21 65 13 11 0 0 0 3 3 3 3 3 3 TYP MAX -55oC TO 125oC MIN 120 24 20 90 18 15 120 24 20 105 21 18 150 30 26 75 15 13 0 0 0 3 3 3 3 3 3 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 CD54/74HC597, CD74HCT597 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER DS to SHCP Setup Time Dn to STCP Setup Time STCP to SHCP Hold Time DS to SHCP Hold Time Dn to STCP Hold Time MR to SHCP Removal Time SYMBOL tH tH tH tREM VCC (V) 4.5 MIN 10 TYP MAX -40oC TO 85oC MIN 13 TYP MAX -55oC TO 125oC MIN 15 TYP MAX UNITS ns 4.5 4.5 0 3 - - 0 3 - - 0 3 - - ns ns 4.5 10 - - 13 - - 15 - - ns Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay SHCP to Q7 CL =15pF CL = 50pF PL to Q7 tPLH, tPHL CL = 50pF SYMBOL tPLH, tPHL TEST CONDITIONS CL = 50pF 25oC VCC (V) 2 4.5 5 6 2 4.5 CL =15pF CL = 50pF STCP to Q7 tPLH, tPHL CL = 50pF 5 6 2 4.5 CL =15pF CL = 50pF MR to Q7 tPLH, tPHL CL = 50pF 5 6 2 4.5 CL =15pF CL = 50pF Output Transition Time tTLH, tTHL CL = 50pF 5 6 2 4.5 6 Input Capacitance Power Dissipation Capacitance, (Notes 4, 5) HCT Propagation Delay SHCP to Q7 tPLH, tPHL CL = 50pF CL = 15pF PL to Q7 tPLH, tPHL CL = 50pF CL = 15pF STCP to Q7 tPLH, tPHL CL = 50pF CL = 15pF 4.5 5 4.5 5 4.5 5 16 20 23 38 48 56 48 60 70 57 72 84 ns ns ns ns ns ns CI CPD CL = 50pF 5 MIN TYP 14 17 20 14 13.5 MAX 175 35 30 200 40 34 240 48 41 175 35 30 75 15 13 10 -40oC to 85oC -55oC to 125oC MIN MAX 220 44 37 250 50 43 300 60 51 220 44 37 95 19 16 10 MIN MAX 265 53 45 300 60 51 360 72 61 265 53 45 110 22 19 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF 6 CD54/74HC597, CD74HCT597 Switching Specifications Input tr, tf = 6ns PARAMETER MR to Q7 SYMBOL tPLH, tPHL (Continued) 25oC VCC (V) 4.5 5 4.5 5 MIN TYP 18 18.5 MAX 44 15 10 -40oC to 85oC -55oC to 125oC MIN MAX 55 19 10 MIN MAX 66 22 10 UNITS ns ns ns pF pF TEST CONDITIONS CL = 50pF CL = 15pF Output Transition Time Input Capacitance Power Dissipation Capacitance, (Notes 4, 5) NOTES: tTLH, tTHL CI CPD CL = 50pF CL = 50pF - 4. CPD is used to determine the dynamic power consumption, per package. 5. PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = Input Frequency, fo = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms trCL CLOCK 90% 10% tfCL tWL + tWH = I fCL VCC 50% 10% tWL 50% 50% GND tWH CLOCK trCL = 6ns tWL + tWH = tfCL = 6ns 2.7V 0.3V I fCL 3V 1.3V 0.3V tWL 1.3V 1.3V GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr = 6ns INPUT 90% 50% 10% tf = 6ns VCC tr = 6ns INPUT GND 2.7V 1.3V 0.3V tf = 6ns 3V GND tTLH 90% tTHL tTLH 90% 50% 10% tPHL tPLH tTHL INVERTING OUTPUT INVERTING OUTPUT tPHL tPLH 1.3V 10% FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 7 CD54/74HC597, CD74HCT597 Test Circuits and Waveforms (Continued) trCL CLOCK INPUT 90% 10% tH(H) tfCL VCC 50% GND tH(L) VCC DATA INPUT tSU(H) CLOCK INPUT trCL 2.7V 0.3V tH(H) tfCL 3V 1.3V GND tH(L) 3V 1.3V 1.3V 1.3V tSU(L) tTLH tTHL 90% 1.3V 10% tPHL GND DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL 50% GND OUTPUT 90% 1.3V tPLH 50% GND tREM 3V SET, RESET OR PRESET 1.3V GND IC CL 50pF IC CL 50pF FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 8 CD54/74HC597, CD74HCT597 Timing Diagram SHIFT CLOCK SHCP SERIAL DATE DS MASTER RESET MR PARALLEL LOAD PL STORAGE CLOCK STCP D0 H L L D1 L L L D2 H L L PARALLEL DATA INPUTS D3 L L L D4 H L H D5 H L H L D6 L L D7 H H H Q7 RESET SHIFT REGISTER L L H L H H L H L H L H L L L H L H H SERIAL SHIFT PARALLEL LOAD SHIFT REGISTER SERIAL SHIFT LOAD FLIP-FLOPS SERIAL SHIFT PARALLEL LOAD SHIFT REGISTER SERIAL SHIFT PARALLEL LOAD FLIP-FLOPS AND SHIFT REGISTER LOAD FLIP-FLOPS 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
Price & Availability of SCHS191A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |