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SN74GTLPH32945 32-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES293 - OCTOBER 1999
D D D D D D
Bidirectional Interface Between GTL+ Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant Identical to '32245 Function Medium-Drive GTL+ Outputs (50 mA) LVTTL Outputs (-24 mA/24 mA) GTL+ Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity
D D D D
Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND-Pin Configuration Minimizes High-Speed Switching Noise Packaged in Plastic Fine-Pitch Ball Grid Array Package
NOTE: For tape and reel order entry: The GKER package is abbreviated to KR.
description
The SN74GTLPH32945 is a medium-drive 32-bit bus transceiver that provides LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level translation. It is partitioned as four 8-bit transceivers and is identical to the '16245 function. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL+ signal levels. High-speed (about two times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output edge control (OECTM). Improved GTLP OEC circuits minimize bus settling time and have been designed and tested using several backplane models. The medium drive is suitable for driving double-terminated backplanes. GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The AC specification of the SN74GTLPH32945 is given only at the preferred higher noise margin GTL+, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74GTLPH32945 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 1999, Texas Instruments Incorporated
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* DALLAS, TEXAS 75265
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PRODUCT PREVIEW
SN74GTLPH32945 32-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES293 - OCTOBER 1999
GKE PACKAGE (TOP VIEW)
1 A B C D E F G H J K L M N P R T
2
3
4
5
6
terminal assignments
1 A B C D E F G H J K L M N P R T 1A2 1A3 1A5 1A7 2A1 2A3 2A5 2A7 3A2 3A3 3A5 3A7 4A1 4A3 4A5 4A7 2 1A1 1A4 1A6 1A8 2A2 2A4 2A6 2A8 3A1 3A4 3A6 3A8 4A2 4A4 4A6 4A8 3 1DIR GND 1VCC GND GND 1VCC GND 2DIR 3DIR GND 2VCC GND GND 2VCC GND 4DIR 4 1OE GND 1BIAS VCC GND GND 1VREF GND 2OE 3OE GND 2BIAS VCC GND GND 2VREF GND 4OE 5 1B1 1B4 1B6 1B8 2B3 2B4 2B6 2B8 3B1 3B4 3B6 3B8 4B2 4B4 4B6 4B8 6 1B2 1B3 1B5 1B7 2B1 2B3 2B5 2B7 3B2 3B3 3B5 3B7 4B1 4B3 4B5 4B7
PRODUCT PREVIEW
functional description
The SN74GTLPH32945 is a medium-drive (50 mA) 32-bit bus transceiver partitioned as four 8-bit segments, providing standard '245 functionality, and is designed for asynchronous communication between data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input. OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting. For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When OE is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that for A to B, but OE is low and DIR is low.
FUNCTION TABLE INPUTS OE L L H DIR L H X OUTPUT B data to A port A data to B port Z MODE Transparent Transparent Isolation
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SN74GTLPH32945 32-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES293 - OCTOBER 1999
logic diagram (positive logic)
1DIR A3 A4 A5
1OE 1B1
1A1
A2
F4
1VREF
To Seven Other Channels
2DIR
H3 H4 E6
2OE 2B1
2A1
E1
To Seven Other Channels 1VCC and 1BIAS VCC are associated with these channels.
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PRODUCT PREVIEW
SN74GTLPH32945 32-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES293 - OCTOBER 1999
logic diagram (positive logic) (continued)
3DIR J3 J4 J5
3OE 3B1
3A1
J2
P4
2VREF
To Seven Other Channels
4DIR
T3 T4 N6
PRODUCT PREVIEW
4OE 4B1
4A1
N1
To Seven Other Channels 2VCC and 2BIAS VCC are associated with these channels.
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SN74GTLPH32945 32-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES293 - OCTOBER 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1):A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Notes 4 through 6)
MIN VCC, BIAS VCC VTT VREF VI VIH VIL IIK IOH IOL Supply voltage Termination voltage Supply voltage Input voltage High-level High level input voltage Low-level Low level input voltage Input clamp current High-level output current Low-level Low level output current A port A port B port GTL GTL+ GTL GTL+ B port Except B port B port Except B port B port Except B port VREF+0.05 2 VREF-0.05 0.8 -18 -24 24 50 3.15 1.14 1.35 0.74 0.87 NOM 3.3 1.2 1.5 0.8 1 MAX 3.45 1.26 1.65 0.87 1.1 VTT VCC UNIT V V V V V V mA mA mA
TA Operating free-air temperature -40 85 C NOTES: 4. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Normal connection sequence is GND first, BIAS VCC = 3.3 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. However, if the B-port I/O precharge is not required, the acceptable connection sequence is GND first and VCC = 3.3 V, BIAS VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. When VCC is connected, the BIAS VCC circuitry is disabled. 6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings. Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT.
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PRODUCT PREVIEW
SN74GTLPH32945 32-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES293 - OCTOBER 1999
electrical characteristics over recommended operating free-air temperature range for GTL+ (unless otherwise noted)
PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, VCC = 3 15 V 3.15 VCC = 3.15 V to 3.45 V, A port VOL B port VCC = 3 15 V 3.15 VCC = 3.15 V to 3.45 V, VCC = 3.15 V VCC = 3.45 V, VCC = 3 45 V 3.45 VCC = 3.15 V, VCC = 3.15 V, VCC = 3.45 V, VCC = 3.45 V, VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND VI (B port) = VTT or GND II = -18 mA IOH = -100 A IOH = -12 mA IOH = -24 mA IOL = 100 A IOL = 12 mA IOL = 24 mA IOL = 100 A IOL = 10 mA IOL = 40 mA IOL = 50 mA VI = 0 to 1.5 V VI = 0 or VCC VI = 5.5 V VI = 0.8 V VI = 2 V VI = 0 to VCC VI = 0 to VCC Outputs high Outputs low Outputs disabled 75 -75 500 -500 50 50 50 1 mA pF pF mA MIN VCC-0.2 2.4 2 0.2 0.4 0.5 0.2 0.2 0.4 0.55 10 10 20 A A A A A V TYP MAX -1.2 UNIT V V
B port II A-port and control inputs A port A port A port A port A or B port
PRODUCT PREVIEW
IBHL IBHH IBHLO# IBHHO|| ICC ICCk Ci Ci io
VCC = 3.45 V, One A-port or control input at VCC - 0.6 V, Other A-port or control inputs at VCC or GND Control inputs A port B port VI = 3.15 V or 0 VO = 3.15 V or 0 VO = 1.5 V or 0
All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter II includes the off-state output leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. kThis is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
live-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER Ioff IOZPU IOZPD VCC = 0, VCC = 0 to 1.5 V, VCC = 1.5 V to 0, TEST CONDITIONS BIAS VCC = 0, VO = 0.5 V to 3 V, VO = 0.5 V to 3 V, VI or VO = 0 to 5.5 V OE = 0 OE = 0 MIN MAX 100 100 100 UNIT A A A
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SN74GTLPH32945 32-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES293 - OCTOBER 1999
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER Ioff IOZPU IOZPD ICC (BIAS VCC) VO IO VCC = 0, VCC = 0 to 1.5 V, VCC = 1.5 V to 0, VCC = 0 to 3.15 V VCC = 3.15 V to 3.45 V VCC = 0, VCC = 0, TEST CONDITIONS BIAS VCC = 0, VO = 0.5 V to 1.5 V, VO = 0.5 V to 1.5 V, BIAS VCC = 3 15 V to 3 45 V 3.15 3.45 V, BIAS VCC = 3.3 V BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V VI or VO = 0 to 1.5 V OE = 0 OE = 0 VO (B port) = 0 to 1.5 V 15 0.95 -1 MIN MAX 100 100 100 5 10 1.05 UNIT A A A mA A V A
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1)
PARAMETER fmax tpd ten tdis tr tf tpd ten tdis All typical values are at VCC = 3.3 V, TA = 25C. B OE FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT MHz A OE OE Rise time, B outputs (0.6 V to 1.3 V) Fall time, B outputs (1.3 V to 0.6 V) A A B B B ns
ns ns ns ns ns
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PRODUCT PREVIEW
ns
SN74GTLPH32945 32-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES293 - OCTOBER 1999
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND 1.5 V 25 From Output Under Test CL = 30 pF (see Note A)
Test Point
LOAD CIRCUIT FOR A OUTPUTS 3V Input 1.5 V 1.5 V 0V tPLH tPHL VOH Output 1V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1.5 V Input 1V 1V 0V tPLH tPHL VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) 1V VOL
LOAD CIRCUIT FOR B OUTPUTS
PRODUCT PREVIEW
3V Output Control tPZL Output Waveform 1 S1 at 6 V (see Note B) tPZH 1.5 V 1.5 V 1.5 V 0V tPLZ 3V VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port)
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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SN74GTLPH32945 32-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES293 - OCTOBER 1999
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
This data sheet is specified for and tested to the lump load shown in Figure 1. However, the designer probably uses this GTLP device in a distributed load like that shown in Figure 2, in which actual B-port backplane switching characteristics are different. Therefore, the device is modeled as shown in Figure 3, which very closely matches the results obtained using Figure 2. Switching characteristics based on Figure 3 more closely match actual backplane design requirements.
VTT
RTT
VTT
RTT
.25"
.875"
.875"
.25"
.625" Conn. 1"
.625" Conn. 1"
Rcvr
.625" Conn. 1"
Rcvr
.625" 1.5 V Conn. 1"
Rcvr
From Output Under Test
LL = 21 nH
14 Test Point CL = 13 pF
Drvr
Slot 1
Slot 2
Slot 15
Slot 16
Figure 2. Test Backplane Model
Figure 3. Distributed-Load Circuit for B Outputs
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 3)
PARAMETER tpd ten tdis tr tf All typical values are at VCC = 3.3 V, TA = 25C. FROM (INPUT) A OE Rise time, B outputs (0.6 V to 1.3 V) Fall time, B outputs (1.3 V to 0.6 V) TO (OUTPUT) B B MIN TYP MAX UNIT ns ns ns ns
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PRODUCT PREVIEW
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated

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