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SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES281 - OCTOBER 1999
D D D
Member of the Texas Instruments Widebus+TM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D D D
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) Packaged in Plastic Fine-Pitch Ball Grid Array Package
description
This 32-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH32244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH32244 is characterized for operation from -40C to 85C.
FUNCTION TABLE (each 4-bit buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus+ are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
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SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES281 - OCTOBER 1999
GKE PACKAGE (TOP VIEW)
terminal assignments
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A B C D E F G H J K L M N P R T 1 1Y2 1Y4 2Y2 2Y4 3Y2 3Y4 4Y2 4Y4 5Y2 5Y4 6Y2 6Y4 7Y2 7Y4 8Y2 8Y3 2 1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y3 5Y1 5Y3 6Y1 6Y3 7Y1 7Y3 8Y1 8Y4 3 1OE GND VCC GND GND VCC GND 4OE 5OE GND VCC GND GND VCC GND 8OE 4 2OE GND VCC GND GND VCC GND 3OE 6OE GND VCC GND GND VCC GND 7OE 5 1A1 1A3 2A1 2A3 3A1 3A3 4A1 4A3 5A1 5A3 6A1 6A3 7A1 7A3 8A1 8A4 6 1A2 1A4 2A2 2A4 3A2 3A4 4A2 4A4 5A2 5A4 6A2 6A4 7A2 7A4 8A2 8A3
1 A B C D E F G H J K L M N P R T
2
3
4
5
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SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES281 - OCTOBER 1999
logic diagram (positive logic)
1OE A3 3OE A2 H4
1A1
A5
1Y1
3A1
E5
E2
3Y1
1A2
A6
A1
1Y2
3A2
E6
E1
3Y2
1A3
B5
B2
1Y3
3A3
F5
F2
3Y3
1A4
B6
B1
1Y4
3A4
F6
F1
3Y4
2OE
A4
4OE C2
H3
2A1
C5
2Y1
4A1
G5
G2
4Y1
2A2
C6
C1
2Y2
4A2
G6
G1
4Y2
2A3
D5
D2
2Y3
4A3
H6
H1
4Y3
2A4
D6
D1
2Y4
4A4
H5
H2
4Y4
5OE
J3
7OE J2
T4
5A1
J5
5Y1
7A1
N5
N2
7Y1
5A2
J6
J1
5Y2
7A2
N6
N1
7Y2
5A3
K5
K2
5Y3
7A3
P5
P2
7Y3
5A4
K6
K1
5Y4
7A4
P6
P1
7Y4
6OE
J4
8OE L2
T3
6A1
L5
6Y1
8A1
R5
R2
8Y1
6A2
L6
L1
6Y2
8A2
R6
R1
8Y2
6A3
M5
M2
6Y3
8A3
T6
T1
8Y3
6A4
M6
M1
6Y4
8A4
T5
T2
8Y4
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SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES281 - OCTOBER 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 1.65 1.5 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 VCC VCC -4 -8 -12 -24 4 8 12 24 10 ns/V mA mA V V V V MAX 3.6 UNIT V
VIH
High-level input voltage
VIL VI VO
Low-level input voltage Input voltage Output voltage
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES281 - OCTOBER 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -4 mA VOH IOH = -8 mA IOH = -12 mA 12 IOH = -24 mA IOL = 100 A VOL IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA II VI = VCC or GND VI = 0.58 V VI = 1.07 V VI = 0.7 V II(hold) ( ) VI = 1.7 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V IOZ ICC ICC Ci Control inputs Data inputs VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, VI = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3.6 V 1.65 V 1.65 V 2.3 V 2.3 V 3V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 3.3 33V 3 6 25 -25 45 -45 75 -75 500 10 40 750 A A A pF A MIN TYP MAX UNIT VCC-0.2 1.2 1.7 2.2 2.4 2.2 0.2 0.45 0.7 0.4 0.55 5 A V V
Co Outputs VO = VCC or GND 3.3 V 7 pF All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER tpd ten FROM (INPUT) A OE TO (OUTPUT) Y Y VCC = 1.8 V 0.15 V MIN MAX VCC = 2.5 V 0.2 V MIN 1 1 1 MAX 3.7 5.7 5.2 VCC = 2.7 V MIN MAX 3.6 5.4 4.6 VCC = 3.3 V 0.3 V MIN 1 1 1 MAX 3 4.4 4.1 ns ns ns UNIT
tdis Y OE This information was not available at the time of publication.
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 0, 0 f = 10 MHz VCC = 1.8 V TYP VCC = 2.5 V TYP 16 4 VCC = 3.3 V TYP 19 5 UNIT pF
This information was not available at the time of publication.
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SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES281 - OCTOBER 1999
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 VCC/2 0V tPLH tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES281 - OCTOBER 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC/2 VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES281 - OCTOBER 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
500 S1 6V Open GND 500
From Output Under Test CL = 50 pF (see Note A)
TEST tpd tPLZ/tPZL tPHZ/tPZH
S1 Open 6V GND
tw LOAD CIRCUIT 2.7 V Input Timing Input tsu Data Input 1.5 V 2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Waveform 1 S1 at 6 V (see Note B) tPZH VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) 1.5 V Output Control (low-level enabling) tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH tPHL 2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 0V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright (c) 1999, Texas Instruments Incorporated

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